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21. 发明申请

US20120261791A1 Wide and Deep Oxide Trench in A Semiconductor Substrate with Interspersed Vertical Oxide Ribs 有权
标题翻译：半导体衬底中的宽和深氧化物沟槽，具有散射的垂直氧化物肋
公开(公告)号：US20120261791A1
公开(公告)日：2012-10-18
申请号：US13537493
申请日：2012-06-29
申请人： Xiaobin Wang , Anup Bhalla , Yeeherg Lee
发明人： Xiaobin Wang , Anup Bhalla , Yeeherg Lee
IPC分类号： H01L21/76 , H01L23/58
CPC分类号： H01L29/0657 , H01L21/76202 , H01L21/76224 , H01L21/76227 , H01L29/407 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device structure with an oxide-filled large deep trench (OFLDT) portion having trench size TCS and trench depth TCD is disclosed. A bulk semiconductor layer (BSL) is provided with a thickness BSLT>TCD. A large trench top area (LTTA) is mapped out atop BSL with its geometry equal to OFLDT. The LTTA is partitioned into interspersed, complementary interim areas ITA-A and ITA-B. Numerous interim vertical trenches of depth TCD are created into the top BSL surface by removing bulk semiconductor materials corresponding to ITA-B. The remaining bulk semiconductor materials corresponding to ITA-A are converted into oxide. If any residual space is still left between the so-converted ITA-A, the residual space is filled up with oxide deposition. Importantly, the geometry of all ITA-A and ITA-B should be configured simple and small enough to facilitate fast and efficient processes of oxide conversion and oxide filling.
摘要翻译：公开了具有沟槽尺寸TCS和沟槽深度TCD的具有氧化物填充的大深沟槽（OFLDT）部分的半导体器件结构。体积半导体层（BSL）设置有厚度BSLT> TCD。一个大的沟槽顶部区域（LTTA）映射到BSL顶部，其几何形状等于OFLDT。 LTTA被划分为散置的，互补的临时区域ITA-A和ITA-B。通过去除对应于ITA-B的散装半导体材料，在顶部BSL表面上形成了许多深度TCD的临时垂直沟槽。对应于ITA-A的剩余体积半导体材料被转化为氧化物。如果在经过转换的ITA-A之间仍然留有剩余空间，则剩余空间被氧化物沉积填满。重要的是，所有ITA-A和ITA-B的几何形状都应该被简单而小型化，以便于快速有效地进行氧化物转换和氧化物填充。

22. 发明申请

US20120126317A1 ACCUFET WITH INTEGRATED CLAMPING CIRCUIT 审中-公开
标题翻译：具有集成钳位电路的ACCUFET
公开(公告)号：US20120126317A1
公开(公告)日：2012-05-24
申请号：US12949218
申请日：2010-11-18
申请人： Daniel Ng , Anup Bhalla , Xiaobin Wang
发明人： Daniel Ng , Anup Bhalla , Xiaobin Wang
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L27/0727 , H01L27/0629 , H01L29/872
摘要： The present invention features a field effect transistor that includes a semiconductor substrate having gate, source and drain regions; and a p-n junction formed on the semiconductor substrate and in electrical communication with the gate, drain and source regions to establish a desired breakdown voltage. In one embodiment, gate region further includes a plurality of spaced-apart trench gates with the p-n junction being defined by an interface between an epitaxial layer in which the trench gates are formed and the interface with a metallization layer. The breakdown voltage provided is defined, in part by the number of p-n junctions formed. In another embodiment, the p-n junctions are formed by generating a plurality of spaced-apart p-type regions in areas of the epitaxial layer located adjacent to the trench gates.
摘要翻译：本发明的特征在于一种场效应晶体管，其包括具有栅极，源极和漏极区域的半导体衬底; 以及形成在半导体衬底上并与栅极，漏极和源极区域电连通以建立期望的击穿电压的p-n结。在一个实施例中，栅极区域还包括多个间隔开的沟槽栅极，其中p-n结由其中形成沟槽栅极的外延层与与金属化层的界面之间的界面限定。提供的击穿电压部分地由形成的p-n结的数量定义。在另一个实施例中，通过在邻近沟槽栅极定位的外延层的区域中产生多个间隔开的p型区域来形成p-n结。

23. 发明申请

US20110076815A1 Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection 有权
标题翻译：降低了具有静电放电（ESD）电路保护功率的MOSFET的掩模配置
公开(公告)号：US20110076815A1
公开(公告)日：2011-03-31
申请号：US12925820
申请日：2010-10-29
申请人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
发明人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
IPC分类号： H01L21/8234
CPC分类号： H01L29/7811 , H01L27/0255 , H01L29/0619 , H01L29/0696 , H01L29/404 , H01L29/66734 , H01L29/7808 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.
摘要翻译：支撑在半导体衬底上的半导体功率器件包括设置在半导体衬底顶部的图案化ESD多晶硅层的第一部分上的静电放电（ESD）保护电路。该半导体功率器件还包括构图的ESD多晶硅层的第二部分，其构成体部注入离子阻挡层，用于阻止注入体离子进入体内注入离子阻挡层下方的半导体衬底。在示例性实施例中，半导体衬底顶部上的静电放电（ESD）多晶硅层进一步覆盖半导体器件边缘上的划线，由此不再需要钝化层制造用于减少图案所需掩模的半导体器件钝化层。

24. 发明申请

US20160315053A1 FLEXIBLE CRSS ADJUSTMENT IN A SGT MOSFET TO SMOOTH WAVEFORMS AND TO AVOID EMI IN DC-DC APPLICATION 有权
公开(公告)号：US20160315053A1
公开(公告)日：2016-10-27
申请号：US14242851
申请日：2014-04-01
申请人： Ji Pan , Daniel Ng , Anup Bhalla , Xiaobin Wang
发明人： Ji Pan , Daniel Ng , Anup Bhalla , Xiaobin Wang
IPC分类号： H01L23/552 , H02M1/44 , H01L29/66 , H02M3/158 , H01L29/40 , H01L29/78
CPC分类号： H01L23/552 , H01L29/0638 , H01L29/401 , H01L29/407 , H01L29/41766 , H01L29/66704 , H01L29/66727 , H01L29/66734 , H01L29/7811 , H01L29/7813 , H01L29/7823 , H01L29/7825 , H02M1/44 , H02M3/158
摘要： A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.

25. 发明申请

US20140167212A1 Termination Structure with Multiple Embedded Potential Spreading Capacitive Structures for Trench MOSFET and Method 有权
标题翻译：具有多个嵌入式电位扩展结构的端接结构，用于沟槽MOSFET和方法
公开(公告)号：US20140167212A1
公开(公告)日：2014-06-19
申请号：US13712980
申请日：2012-12-13
申请人： Xiaobin Wang , Anup Bhalla , Hamza Yilmaz , Daniel Ng
发明人： Xiaobin Wang , Anup Bhalla , Hamza Yilmaz , Daniel Ng
IPC分类号： H01L21/762 , H01L29/06
CPC分类号： H01L29/407 , H01L21/76205 , H01L29/04 , H01L29/0619 , H01L29/0638 , H01L29/0649 , H01L29/0696 , H01L29/402 , H01L29/41766 , H01L29/42368 , H01L29/66727 , H01L29/66734 , H01L29/7803 , H01L29/7811 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.
摘要翻译：公开了具有多个嵌入式电位扩展电容结构（TSMEC）和方法的端接结构，用于在具有底部漏电极的体半导体层（BSL）的顶部端接邻近的沟槽MOSFET。 BSL具有支持漏极 - 源极电压（DSV）的近端体半导体壁（PBSW），并将TSMEC与沟槽MOSFET分离。 TSMEC具有由PBSW和远端体半导体壁（DBSW）界定的氧化物填充的大深沟槽（OFLDT）。 OFLDT包括位于大深度氧化物沟槽内部以及PBSW和DBSW之间的BSL中的大型深层氧化物沟槽和嵌入式电容结构（EBCS），用于在其间空间扩展DSV。在一个实施例中，EBCS包含OFLDT的交错导电嵌入式多晶半导体区域（EPSR）和氧化物柱（OXC），与PBSW相邻的近端EPSR连接到活动上部源区域，并且与DBSW相邻的远端EPSR被连接到星展集团

26. 发明授权

US08362547B2 MOS device with Schottky barrier controlling layer 有权
标题翻译：具有肖特基势垒控制层的MOS器件
公开(公告)号：US08362547B2
公开(公告)日：2013-01-29
申请号：US12005166
申请日：2007-12-21
申请人： Anup Bhalla , Xiaobin Wang , Ji Pan , Sung-Po Wei
发明人： Anup Bhalla , Xiaobin Wang , Ji Pan , Sung-Po Wei
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7811 , H01L21/26513 , H01L21/26586 , H01L29/0623 , H01L29/1083 , H01L29/1095 , H01L29/165 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66143 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7809 , H01L29/7813 , H01L29/8725
摘要： A semiconductor device formed on a semiconductor substrate includes: an epitaxial layer overlaying the semiconductor substrate; a drain formed on back of the semiconductor substrate; a drain region that extends into the epitaxial layer; and an active region. The active region includes: a body disposed in the epitaxial layer, having a body top surface; a source embedded in the body, extending from the body top surface into the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and the body into the drain region; an active region contact electrode disposed within the active region contact trench, wherein the active region contact electrode and the drain region form a Schottky diode; and a Schottky barrier controlling layer.
摘要翻译：形成在半导体衬底上的半导体器件包括：覆盖半导体衬底的外延层; 在半导体衬底背面形成的漏极; 漏极区域，其延伸到所述外延层中; 和活跃区域。有源区包括：设置在外延层中的具有主体顶表面的主体; 嵌入在体内的源体，从身体顶面延伸到体内; 延伸到外延层中的栅极沟槽; 设置在栅极沟槽中的栅极; 有源区域接触沟槽，其延伸穿过所述源极和所述本体进入所述漏极区域; 有源区接触电极，设置在有源区接触沟槽内，其中有源区接触电极和漏区形成肖特基二极管; 和肖特基势垒控制层。

27. 发明授权

US08093651B2 MOS device with integrated schottky diode in active region contact trench 有权
标题翻译：具有集成肖特基二极管的MOS器件在有源区接触沟槽中
公开(公告)号：US08093651B2
公开(公告)日：2012-01-10
申请号：US12005146
申请日：2007-12-21
申请人： Anup Bhalla , Xiaobin Wang , Ji Pan , Sung-Po Wei
发明人： Anup Bhalla , Xiaobin Wang , Ji Pan , Sung-Po Wei
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66484 , H01L21/26586 , H01L29/0623 , H01L29/1095 , H01L29/165 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813
摘要： A semiconductor device is formed on a semiconductor substrate. The device comprises a drain, an epitaxial layer overlaying the drain, and an active region. The active region comprises a body disposed in the epitaxial layer, having a body top surface and a body bottom surface, a source embedded in the body, extending from the body top surface into the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source and at least part of the body into the drain, wherein the active region contact trench is shallower than the body bottom surface, and an active region contact electrode disposed within the active region contact trench.
摘要翻译：半导体器件形成在半导体衬底上。该器件包括漏极，覆盖漏极的外延层和有源区。有源区域包括设置在外延层中的主体，具有主体顶表面和主体底表面，嵌入在主体中的源，从主体顶表面延伸到主体中，延伸到外延层中的栅沟槽，设置在所述栅极沟槽中的栅极，延伸穿过所述源极和所述主体的至少一部分进入所述漏极的有源区接触沟槽，其中所述有源区接触沟槽比所述主体底表面浅，以及设置在所述栅极沟槽内的有源区接触电极有源区接触沟槽。

28. 发明授权

US07825431B2 Reduced mask configuration for power MOSFETs with electrostatic discharge (ESD) circuit protection 有权
标题翻译：降低了具有静电放电（ESD）电路保护功能MOSFET的掩模配置
公开(公告)号：US07825431B2
公开(公告)日：2010-11-02
申请号：US12006398
申请日：2007-12-31
申请人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
发明人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
IPC分类号： H01L29/72 , H01L23/62
CPC分类号： H01L29/7811 , H01L27/0255 , H01L29/0619 , H01L29/0696 , H01L29/404 , H01L29/66734 , H01L29/7808 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.
摘要翻译：支撑在半导体衬底上的半导体功率器件包括设置在半导体衬底顶部的图案化ESD多晶硅层的第一部分上的静电放电（ESD）保护电路。该半导体功率器件还包括构图的ESD多晶硅层的第二部分，其构成体部注入离子阻挡层，用于阻止注入体离子进入体内注入离子阻挡层下方的半导体衬底。在示例性实施例中，半导体衬底顶部上的静电放电（ESD）多晶硅层进一步覆盖半导体器件边缘上的划线，由此不再需要钝化层制造用于减少图案所需掩模的半导体器件钝化层。

29. 发明申请

US20090008758A1 USE OF DISCRETE CONDUCTIVE LAYER IN SEMICONDUCTOR DEVICE TO RE-ROUTE BONDING WIRES FOR SEMICONDUCTOR DEVICE PACKAGE 有权
标题翻译：在半导体器件中使用分离导电层以重新布线用于半导体器件封装
公开(公告)号：US20090008758A1
公开(公告)日：2009-01-08
申请号：US12209106
申请日：2008-09-11
申请人： Jun Lu , Anup Bhalla , Xiaobin Wang , Allen Chang , Man Sheng Hu , Xiaotian Zhang
发明人： Jun Lu , Anup Bhalla , Xiaobin Wang , Allen Chang , Man Sheng Hu , Xiaotian Zhang
IPC分类号： H01L23/495 , H01L21/58 , H01L23/488
CPC分类号： H01L21/823487 , H01L23/4952 , H01L23/49524 , H01L23/49531 , H01L23/49562 , H01L23/49575 , H01L23/58 , H01L24/37 , H01L24/39 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/85 , H01L24/91 , H01L25/071 , H01L25/074 , H01L25/18 , H01L27/088 , H01L2224/05552 , H01L2224/0603 , H01L2224/32145 , H01L2224/32245 , H01L2224/37124 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49112 , H01L2224/4917 , H01L2224/49171 , H01L2224/49431 , H01L2224/73265 , H01L2224/83801 , H01L2224/8385 , H01L2224/85 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H02J7/0031 , H01L2224/78 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： A semiconductor package assembly may include a lead frame having a die bonding pad and plurality of leads coupled to the first die bonding pad. A vertical semiconductor device may be bonded to the die bonding pad. The device may have a conductive pad electrically connected to one lead through a first bond wire. An electrically isolated conductive trace may be formed from a layer of conductive material of the first semiconductor device. The conductive trace provides an electrically conductive path between the first bond wire and a second bond wire. The conductive path may either pass underneath a third bond wire thereby avoiding the third bond wire crossing another bond wire, or the conductive path may result in a reduced length for the first and second bond wires that is less than a predetermined maximum length.
摘要翻译：半导体封装组件可以包括引线框架，其具有管芯接合焊盘和耦合到第一管芯接合焊盘的多个引线。垂直半导体器件可以结合到芯片焊盘。该器件可以具有通过第一接合线电连接到一个引线的导电焊盘。电绝缘的导电迹线可以由第一半导体器件的导电材料层形成。导电迹线在第一接合线和第二接合线之间提供导电路径。导电路径可以通过第三接合线下方，从而避免第三接合线穿过另一接合线，或者导电路径可导致第一和第二接合线的长度小于预定最大长度。

30. 发明申请

US20130009242A1 MOS DEVICE WITH LOW INJECTION DIODE 审中-公开
标题翻译：具有低注射二极管的MOS器件
公开(公告)号：US20130009242A1
公开(公告)日：2013-01-10
申请号：US13610758
申请日：2012-09-11
申请人： Anup Bhalla , Xiaobin Wang , Ji Pan , Sung-Po Wei
发明人： Anup Bhalla , Xiaobin Wang , Ji Pan , Sung-Po Wei
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1095 , H01L21/26586 , H01L29/0623 , H01L29/165 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813
摘要： A semiconductor device is formed on a semiconductor substrate. The device includes: a drain; an epitaxial layer overlaying the drain, wherein a drain region extends into the epitaxial layer; and an active region. The active region includes: a body disposed in the epitaxial layer, having a body top surface; a source embedded in the body, extending from the body top surface into the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and into the body; and an active region contact electrode disposed within the active region contact trench. A layer of body region separates the active region contact electrode from the epitaxial layer, and a low injection diode is formed below a body/drain junction.
摘要翻译：半导体器件形成在半导体衬底上。该装置包括：排水管; 覆盖所述漏极的外延层，其中漏区延伸到所述外延层中; 和活跃区域。有源区包括：设置在外延层中的具有主体顶表面的主体; 嵌入在体内的源体，从身体顶面延伸到体内; 延伸到外延层中的栅极沟槽; 设置在栅极沟槽中的栅极; 有源区接触沟槽延伸穿过该源并进入体内; 以及设置在有源区接触沟槽内的有源区接触电极。主体区域将有源区接触电极与外延层分开，并且在主体/漏极结下方形成低注入二极管。

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