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21. 发明申请

US20140095956A1 ENDURANCE AWARE ERROR-CORRECTING CODE (ECC) PROTECTION FOR NON-VOLATILE MEMORIES 有权
标题翻译：非易失性存储器的耐久性错误修正代码（ECC）保护
公开(公告)号：US20140095956A1
公开(公告)日：2014-04-03
申请号：US13630541
申请日：2012-09-28
申请人： Serkan Ozdemir , Qiong Cai
发明人： Serkan Ozdemir , Qiong Cai
IPC分类号： H03M13/29
CPC分类号： G11C29/42 , G06F11/1048 , H03M13/05 , H03M13/11 , H03M13/19 , H03M13/2778
摘要： Embodiments of the invention relate to endurance-aware ECC protection for memories (e.g., phase change memories). According to one embodiment, a method includes calculating first metadata for data bits and second metadata for ECC bits which protect the data bits and the first metadata. Embodiments can include one or more first metadata bits (for the data bits), and one or more second metadata bits (for the ECC bits). An additional level of ECC protection protects the second metadata. In one embodiment, the wear-reduction modifications applied to the data bits and the ECC bits are different, and can be tailored to the behavior of the bits. According to one embodiment, the endurance-aware ECC protection described herein reduces wear due to accesses to memories while addressing the complications wear-reduction mechanisms introduce to error detection and correction systems.
摘要翻译：本发明的实施例涉及用于存储器（例如，相变存储器）的耐力感知ECC保护。根据一个实施例，一种方法包括为保护数据位和第一元数据的ECC位计算数据位的第一元数据和第二元数据。实施例可以包括一个或多个第一元数据比特（用于数据比特）和一个或多个第二元数据比特（用于ECC比特）。额外的ECC保护级别可保护第二个元数据。在一个实施例中，应用于数据位和ECC位的磨损减小修改是不同的，并且可以针对位的行为进行调整。根据一个实施例，本文所述的耐力感知ECC保护减少了由于访问存储器而导致的磨损，同时解决了对错误检测和校正系统引入的磨损减少机制的并发症。

22. 发明申请

US20150278096A1 METHOD, APPARATUS AND SYSTEM TO CACHE SETS OF TAGS OF AN OFF-DIE CACHE MEMORY 有权
标题翻译：方法，装置和系统，用于缓存一个离线高速缓存存储器的标签集
公开(公告)号：US20150278096A1
公开(公告)日：2015-10-01
申请号：US14227940
申请日：2014-03-27
申请人： Dyer Rolan , Nevin Hyuseinova , Blas A. Cuesta , Qiong Cai
发明人： Dyer Rolan , Nevin Hyuseinova , Blas A. Cuesta , Qiong Cai
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0833 , G06F12/0811 , G06F12/0846 , G06F12/0864 , G06F12/0871 , G06F12/0895 , G06F12/0897 , G06F12/122 , G06F12/123 , G06F12/126 , G06F2212/1024 , G06F2212/1044 , G06F2212/502 , G06F2212/604 , G06F2212/62
摘要： Techniques and mechanism to provide a cache of cache tags in determining an access to cached data. In an embodiment, a tag storage stores a first set including tags associated with respective data locations of a cache memory. A cache of cache tags store a subset of tags stored by the tag storage. In response to any determination that a tag of the first set is to be stored to the cache of cache tags, all tags of the first set are stored to the first portion. Any storage of tags of the first set to the cache of cache tags includes storage of the tags of the first set to only a first portion of the cache of cache tags. In another embodiment, a replacement table is maintained for use in determining, based on an indicated level of activity for a set of the cache of cache tags, whether the set is to be selected for eviction and replacement of cached tags.
摘要翻译：在确定对缓存数据的访问时提供高速缓存标签缓存的技术和机制。在一个实施例中，标签存储存储包括与高速缓冲存储器的相应数据位置相关联的标签的第一集合。缓存标签的缓存存储标签存储器存储的标签的子集。响应于将第一组的标签存储到高速缓存标签的高速缓存中的任何确定，第一组的所有标签都被存储到第一部分。将第一组的标签的任何存储器存储到缓存标签的高速缓存包括将第一集合的标签仅存储在高速缓存标签的高速缓存的仅第一部分。在另一个实施例中，维护替换表用于基于指定的高速缓存标签的高速缓存的一组指定的活动级别来确定该集合是否被选择用于缓存和替换高速缓存的标签。

23. 发明授权

US09003126B2 Apparatus, system and method for adaptive cache replacement in a non-volatile main memory system 有权
标题翻译：用于非易失性主存储器系统中的自适应缓存替换的装置，系统和方法
公开(公告)号：US09003126B2
公开(公告)日：2015-04-07
申请号：US13626464
申请日：2012-09-25
申请人： Qiong Cai , Nevin Hyuseinova , Serkan Ozdemir , Ferad Zyulkyarov , Marios Nicolaides , Blas Cuesta
发明人： Qiong Cai , Nevin Hyuseinova , Serkan Ozdemir , Ferad Zyulkyarov , Marios Nicolaides , Blas Cuesta
IPC分类号： G06F12/12
CPC分类号： G06F12/126 , G06F12/0866 , G06F12/127 , G06F2212/214
摘要： Techniques and mechanisms for adaptively changing between replacement policies for selecting lines of a cache for eviction. In an embodiment, evaluation logic determines a value of a performance metric which is for writes to a non-volatile memory. Based on the determined value of the performance metric, a parameter value of a replacement policy is determined. In another embodiment, cache replacement logic performs a selection of a line of cache for data eviction, where the selection is in response to the policy unit providing an indication of the determined parameter value.
摘要翻译：用于自动更改用于选择用于驱逐的缓存的行的替换策略之间的技术和机制。在一个实施例中，评估逻辑确定用于写入非易失性存储器的性能度量的值。基于确定的性能度量值，确定替换策略的参数值。在另一个实施例中，高速缓存替换逻辑执行用于数据驱逐的高速缓存行的选择，其中所述选择是响应于策略单元提供所确定的参数值的指示。

24. 发明申请

US20140189284A1 SUB-BLOCK BASED WEAR LEVELING 审中-公开
标题翻译：基于子块的磨损水平
公开(公告)号：US20140189284A1
公开(公告)日：2014-07-03
申请号：US13992636
申请日：2011-12-23
申请人： Nevin Hyuseinova , Qiong Cai
发明人： Nevin Hyuseinova , Qiong Cai
IPC分类号： G06F12/10
CPC分类号： G06F12/10 , G06F12/0238 , G06F12/0292 , G06F2212/7211 , G11C16/3495
摘要： Embodiments of the invention describe an apparatus, system and method for sub-block based wear leveling for memory devices. Embodiments of the invention may receive a write request to a physical memory address including a physical block address and a physical sub-block address. An address remapping table is accessed to translate the physical block address to a memory device block address to locate a plurality of memory device sub-blocks. A plurality of sub-block activity counters are accessed, each sub-block activity counter associated with one of the memory device sub-blocks. One of the plurality of memory device sub-blocks is selected to store write data of the write request based, at least in part, on values of the plurality of sub-block activity counters, and the value of the sub-block activity counter associated with the selected memory device sub-block is updated.
摘要翻译：本发明的实施例描述了一种用于存储器件的基于子块的磨损均衡的装置，系统和方法。本发明的实施例可以接收对包括物理块地址和物理子块地址的物理存储器地址的写入请求。访问地址重映射表以将物理块地址转换为存储器件块地址以定位多个存储器件子块。访问多个子块活动计数器，每个子块活动计数器与存储器件子块之一相关联。多个存储器件子块中的一个被选择为至少部分地基于多个子块活动计数器的值和相关联的子块活动计数器的值来存储写入请求的写入数据所选择的存储器件子块被更新。

25. 发明申请

US20140089595A1 UTILITY AND LIFETIME BASED CACHE REPLACEMENT POLICY 有权
标题翻译：实用和基于生活的快速更新策略
公开(公告)号：US20140089595A1
公开(公告)日：2014-03-27
申请号：US13992240
申请日：2011-12-23
申请人： Nevin Hyuseinova , Qiong Cai , Serkan Ozdemir , Ayose J. Falcon
发明人： Nevin Hyuseinova , Qiong Cai , Serkan Ozdemir , Ayose J. Falcon
IPC分类号： G06F12/12 , G06F12/08
CPC分类号： G06F12/121 , G06F12/08 , G06F12/0811 , G06F12/0897 , G06F12/12 , G06F12/123 , G06F12/126 , G06F12/127 , G06F13/16 , G06F2212/1024 , G06F2212/502
摘要： Embodiments of the invention describe an apparatus, system and method for utilizing a utility and lifetime based cached replacement policy as described herein. For processors having one or more processor cores and a cache memory accessible via the processor core(s), embodiments of the invention describe a cache controller to determine, for a plurality of cache blocks in the cache memory, an estimated utility and lifetime of the contents of each cache block, the utility of a cache block to indicate a likelihood of use its contents, the lifetime of a cache block to indicate a duration of use of its contents. Upon receiving a cache access request resulting in a cache miss, said cache controller may select one of the cache blocks to be replaced based, at least in part, on one of the estimated utility or estimated lifetime of the cache block.
摘要翻译：本发明的实施例描述了一种利用如本文所述的效用和基于生命周期的高速缓存替换策略的装置，系统和方法。对于具有一个或多个处理器核心的处理器和经由处理器核心可访问的高速缓存存储器，本发明的实施例描述了一种高速缓存控制器，用于为高速缓冲存储器中的多个高速缓存块确定估计的效用和寿命每个高速缓存块的内容，高速缓存块用于指示使用其内容的可能性的效用，高速缓存块的生命周期表示其内容的使用持续时间。在接收到导致高速缓存未命中的高速缓存访问请求时，所述高速缓存控制器可以至少部分地基于高速缓存块的估计效用或估计的使用寿命之一来选择要替换的高速缓存块之一。

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