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21. 发明申请

US20120159039A1 Generalized Control Registers 有权
标题翻译：广义控制寄存器
公开(公告)号：US20120159039A1
公开(公告)日：2012-06-21
申请号：US13309748
申请日：2011-12-02
申请人： Andy Kegel , Mark Hummel , Tony Asaro , Philip Ng
发明人： Andy Kegel , Mark Hummel , Tony Asaro , Philip Ng
IPC分类号： G06F12/10
CPC分类号： G06F12/1081 , G06F12/1009 , G06F12/1036 , G06F12/109 , G06F2212/151 , Y02D10/13
摘要： Methods, systems, and computer readable media generalize control registers in the context of memory address translations for I/O devices. A method includes maintaining a table including a plurality of concurrently available control register base pointers each associated with a corresponding input/output (I/O) device, associating each control register base pointer with a first translation from a guest virtual address (GVA) to a guest physical address (GPA) and a second translation from the GPA to a system physical address (SPA), and operating the first and second translations concurrently for the plurality of I/O devices.
摘要翻译：在I / O设备的存储器地址转换的上下文中，方法，系统和计算机可读介质泛化控制寄存器。一种方法包括维护包括多个同时可用的控制寄存器基本指针的表，每个与相应的输入/输出（I / O）设备相关联的表，将每个控制寄存器基本指针与来自虚拟地址（GVA）的第一个转换相关联，客户物理地址（GPA）和从GPA到系统物理地址（SPA）的第二翻译，以及为多个I / O设备同时操作第一和第二翻译。

22. 发明申请

US20110202724A1 IOMMU Architected TLB Support 有权
标题翻译： IOMMU架构的TLB支持
公开(公告)号：US20110202724A1
公开(公告)日：2011-08-18
申请号：US12707341
申请日：2010-02-17
申请人： Andrew G. KEGEL , Mark Hummel , Erich Boleyn
发明人： Andrew G. KEGEL , Mark Hummel , Erich Boleyn
IPC分类号： G06F12/10 , G06F12/08
CPC分类号： G06F12/1081 , G06F12/1027 , G06F2212/6028 , G06F2212/654
摘要： Embodiments allow a smaller, simpler hardware implementation of an input/output memory management unit (IOMMU) having improved translation behavior that is independent of page table structures and formats. Embodiments also provide device-independent structures and methods of implementation, allowing greater generality of software (fewer specific software versions, in turn reducing development costs).
摘要翻译：实施例允许具有独立于页表结构和格式的改进的翻译行为的输入/输出存储器管理单元（IOMMU）的更小，更简单的硬件实现。实施例还提供了与设备无关的结构和实现方法，允许更大程度的软件通用性（较少的特定软件版本，从而降低开发成本）。

23. 发明申请

US20110060879A1 SYSTEMS AND METHODS FOR PROCESSING MEMORY REQUESTS 有权
标题翻译：用于处理存储器请求的系统和方法
公开(公告)号：US20110060879A1
公开(公告)日：2011-03-10
申请号：US12878223
申请日：2010-09-09
申请人： Philip J. ROGERS , Warren Fritz Kruger , Mark Hummel , Eric Demers
发明人： Philip J. ROGERS , Warren Fritz Kruger , Mark Hummel , Eric Demers
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F3/14 , G06F12/0835 , G09G5/001 , G09G5/363 , G09G5/393 , G09G2350/00 , G09G2360/121
摘要： A processing system is provided. The processing system includes a first processing unit coupled to a first memory and a second processing unit coupled to a second memory. The second memory comprises a coherent memory and a private memory that is private to the second processing unit.
摘要翻译：提供处理系统。处理系统包括耦合到第一存储器的第一处理单元和耦合到第二存储器的第二处理单元。第二存储器包括对第二处理单元是私有的相干存储器和专用存储器。

24. 发明授权

US09253287B2 Speculation based approach for reliable message communications 有权
标题翻译：基于投机的方法可靠的消息通信
公开(公告)号：US09253287B2
公开(公告)日：2016-02-02
申请号：US13589463
申请日：2012-08-20
申请人： Venkata S. Krishnan , Mark Hummel , David E. Mayhew
发明人： Venkata S. Krishnan , Mark Hummel , David E. Mayhew
IPC分类号： G06F15/16 , H04L29/06
CPC分类号： H04L67/40
摘要： Described are a system and method for lossless message delivery between two processing devices. Each device includes a remote direct memory access (RDMA) messaging interface. The RDMA messaging interface at the first device generates one or more messages that are processed by the RDMA messaging interface of the second device. The RDMA messaging interface of the first device outputs a notification to the second device that a message of the one or more messages is available at the first device. A determination is made that the second device has resources to accommodate the message. The second device performs an operation in response to determining that the processing device has the resources to accommodate the message.
摘要翻译：描述了用于两个处理设备之间无损消息传递的系统和方法。每个设备包括远程直接内存访问（RDMA）消息接口。第一设备上的RDMA消息接口生成由第二设备的RDMA消息接发处理的一个或多个消息。第一设备的RDMA消息接口向第二设备输出一个或多个消息的消息在第一设备可用的通知。确定第二设备具有容纳消息的资源。第二装置响应于确定处理装置具有容纳消息的资源而执行操作。

25. 发明授权

US09176794B2 Graphics compute process scheduling 有权
标题翻译：图形计算过程调度
公开(公告)号：US09176794B2
公开(公告)日：2015-11-03
申请号：US13289260
申请日：2011-11-04
申请人： Jeffrey Gongxian Cheng , Paul Blinzer , Mark Hummel , Leendert Peter Van Doorn
发明人： Jeffrey Gongxian Cheng , Paul Blinzer , Mark Hummel , Leendert Peter Van Doorn
IPC分类号： G06F12/02 , G06T1/00 , G06T15/00 , G06F9/54
CPC分类号： G06F9/545 , G06F2209/509
摘要： A method, system, and computer program product are disclosed for providing improved access to accelerated processing device compute resources to user mode applications. The functionality disclosed allows user mode applications to provide commands to an accelerated processing device without the need for kernel mode transitions in order to access a unified ring buffer. Instead, applications are each provided with their own buffers, which the accelerated processing device hardware can access to process commands. With full operating system support, user mode applications are able to utilize the accelerated processing device in much the same way as a CPU.
摘要翻译：公开了一种方法，系统和计算机程序产品，用于提供对用户模式应用的加速处理设备计算资源的改进访问。所公开的功能允许用户模式应用程序向加速处理设备提供命令，而不需要内核模式转换以便访问统一的环形缓冲区。相反，应用程序各自提供有自己的缓冲区，加速处理设备硬件可以访问进程命令。通过完整的操作系统支持，用户模式应用程序能够以与CPU相同的方式利用加速处理设备。

26. 发明授权

US08868672B2 Server node interconnect devices and methods 有权
标题翻译：服务器节点互连设备和方法
公开(公告)号：US08868672B2
公开(公告)日：2014-10-21
申请号：US13470847
申请日：2012-05-14
申请人： Mark Hummel , David E. Mayhew , Michael J. Osborn
发明人： Mark Hummel , David E. Mayhew , Michael J. Osborn
IPC分类号： G06F15/167
CPC分类号： G06F15/1735 , G06F15/167 , H04L49/9063 , H04L67/2833
摘要： Described are systems and methods for interconnecting devices. A switch fabric is in communication with a plurality of electronic devices. A rendezvous memory is in communication with the switch fabric. Data is transferred to the rendezvous memory from a first electronic device of the plurality of electronic devices in response to a determination that the data is ready for output from a memory at the first electronic device and in response to a location allocated in the rendezvous memory for the data.
摘要翻译：描述了用于互连设备的系统和方法。交换结构与多个电子设备通信。会合记忆体与交换结构通信。响应于确定数据准备好从第一电子设备上的存储器输出并且响应于在会合存储器中分配的位置，数据被从多个电子设备的第一电子设备传送到会合存储器数据。

27. 发明授权

US08842126B2 Methods and systems to facilitate operation in unpinned memory 有权
标题翻译：方便和系统，以方便在无内存中的操作
公开(公告)号：US08842126B2
公开(公告)日：2014-09-23
申请号：US13324443
申请日：2011-12-13
申请人： Warren Fritz Kruger , Philip J. Rogers , Mark Hummel
发明人： Warren Fritz Kruger , Philip J. Rogers , Mark Hummel
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/08
摘要： In an embodiment, a method of processing memory requests in a first processing device is provided. The method includes generating a memory request associated with a memory address located in an unpinned memory space managed by an operating system running on a second processing device; and responsive to a determination that the memory address is not resident in a physical memory, transmitting a message to the second processing device. In response to the message, the operating system controls the second processing device to bring the memory address into the physical memory.
摘要翻译：在一个实施例中，提供了一种在第一处理设备中处理存储器请求的方法。该方法包括：产生与位于由在第二处理设备上运行的操作系统管理的未被固定的存储器空间中的存储器地址相关联的存储器请求; 并且响应于所述存储器地址不驻留在物理存储器中的确定，向第二处理设备发送消息。响应于该消息，操作系统控制第二处理设备以使存储器地址进入物理存储器。

28. 发明授权

US08832382B2 Sub page and page memory management apparatus and method 有权
标题翻译：子页面和页面存储管理装置和方法
公开(公告)号：US08832382B2
公开(公告)日：2014-09-09
申请号：US13332853
申请日：2011-12-21
申请人： David E. Mayhew , Mark Hummel
发明人： David E. Mayhew , Mark Hummel
IPC分类号： G06F12/12
CPC分类号： G06F12/12 , G06F12/10 , G06F12/1027 , G06F2212/2024 , G06F2212/652 , G06F2212/684
摘要： A method and apparatus for managing a virtual address to physical address translation utilize a subpage level fault detecting and access. The method and apparatus may also use an additional subpage and page store Non-Volatile Store (NVS). The method and apparatus determines whether a page fault occurs or whether a subpage fault occurs to effect an address translation and also operates such that if a subpage fault had occurred, a subpage is loaded corresponding to the fault from a NVS to a DRAM, such as DRAM or any other suitable volatile memory historically referred to as main memory. The method and apparatus, if a page fault has occurred, determines if a page fault has occurred without operating system assistance and is a hardware page fault detection system that loads a page corresponding to the fault from NVS to DRAM.
摘要翻译：用于管理虚拟地址以进行物理地址转换的方法和装置利用子页级别的故障检测和访问。该方法和装置还可以使用附加的子页面和页面存储非易失性存储（NVS）。该方法和装置确定页面故障是否发生或是否发生子页面故障以实现地址转换，并且还操作使得如果发生子页面故障，则将从NVS到DRAM的对应于故障的子页面加载到诸如 DRAM或历史上称为主存储器的任何其它合适的易失性存储器。如果发生页面错误，则该方法和装置在没有操作系统帮助的情况下确定页面错误是否发生，并且是将来自NVS的故障页面加载到DRAM的硬件页面故障检测系统。

29. 发明申请

US20140068205A1 SYSTEMS AND METHODS FOR MANAGING QUEUES 有权
标题翻译：管理队伍的系统和方法
公开(公告)号：US20140068205A1
公开(公告)日：2014-03-06
申请号：US13602725
申请日：2012-09-04
申请人： David E. Mayhew , Mark Hummel , Michael J. Osborn
发明人： David E. Mayhew , Mark Hummel , Michael J. Osborn
IPC分类号： G06F12/12
CPC分类号： G06F12/121 , H04L49/356 , H04L49/508
摘要： Described are systems and methods for transmitting data at an aggregation device. The aggregation device includes a record queue and an output bypass queue. The data is received from an electronic device. A record is generated of the received data. The record is placed in the record queue. A determination is made that the record in the record queue is blocked. The blocked record is transferred from the record queue to the output bypass queue.
摘要翻译：描述了在聚合设备处传送数据的系统和方法。聚合设备包括记录队列和输出旁路队列。从电子设备接收数据。生成接收到的数据的记录。记录被放置在记录队列中。确定记录队列中的记录被阻止。被阻止的记录从记录队列传送到输出旁路队列。

30. 发明申请

US20130304841A1 SERVER NODE INTERCONNECT DEVICES AND METHODS 有权
标题翻译：服务器节点互连设备和方法
公开(公告)号：US20130304841A1
公开(公告)日：2013-11-14
申请号：US13470847
申请日：2012-05-14
申请人： Mark Hummel , David E. Mayhew , Michael J. Osborn
发明人： Mark Hummel , David E. Mayhew , Michael J. Osborn
IPC分类号： G06F15/167
CPC分类号： G06F15/1735 , G06F15/167 , H04L49/9063 , H04L67/2833
摘要： Described are systems and methods for interconnecting devices. A switch fabric is in communication with a plurality of electronic devices. A rendezvous memory is in communication with the switch fabric. Data is transferred to the rendezvous memory from a first electronic device of the plurality of electronic devices in response to a determination that the data is ready for output from a memory at the first electronic device and in response to a location allocated in the rendezvous memory for the data.
摘要翻译：描述了用于互连设备的系统和方法。交换结构与多个电子设备通信。会合记忆体与交换结构通信。响应于确定数据准备好从第一电子设备上的存储器输出并且响应于在会合存储器中分配的位置，数据被从多个电子设备的第一电子设备传送到会合存储器数据。

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