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21. 发明授权

US6114186A Hydrogen silsesquioxane thin films for low capacitance structures in integrated circuits 失效
标题翻译：用于集成电路中低电容结构的氢倍半硅氧烷薄膜
公开(公告)号：US6114186A
公开(公告)日：2000-09-05
申请号：US893653
申请日：1997-07-11
申请人： Shin-Puu Jeng , Kelly J. Taylor , Amitava Chatterjee
发明人： Shin-Puu Jeng , Kelly J. Taylor , Amitava Chatterjee
IPC分类号： H01L21/312 , H01L21/314 , H01L21/316 , H01L21/762 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/02134 , H01L21/02164 , H01L21/022 , H01L21/02274 , H01L21/02282 , H01L21/02304 , H01L21/02337 , H01L21/02362 , H01L21/3121 , H01L21/3124 , H01L21/31612 , H01L21/76232 , H01L21/76801 , H01L21/76829 , H01L21/76835 , H01L23/5329 , H01L2924/0002 , Y10S438/902
摘要： An improved method is provided for integrating HSQ into integrated circuit structures and processes, especially those requiring multiple levels of interconnect lines. In a preferred embodiment, interconnect lines 14 are first patterned and etched on a substrate 10. A low-k material such as hydrogen silsesquioxane (HSQ) 18 is spun across the surface of the wafer to fill areas between interconnect lines. A capping layer such as SiO.sub.2 20 is applied to on top of the low-k material. The HSQ is then heated to cure. A thick SiO.sub.2 planarization layer 22 may then be applied and planarized. In other embodiments, the HSQ and SiO.sub.2 process steps can be repeated for multiple layers of HSQ.
摘要翻译：提供了一种改进的方法，用于将HSQ集成到集成电路结构和过程中，特别是需要多级互连线的那些。在优选实施例中，互连线14首先被图案化并蚀刻在衬底10上。低k材料例如氢倍半硅氧烷（HSQ）18跨越晶片的表面旋转以填充互连线之间的区域。将覆盖层如SiO 2 20施加到低k材料的顶部。然后将HSQ加热固化。然后可以施加和平坦化厚的SiO 2平坦化层22。在其他实施例中，可以针对多层HSQ重复HSQ和SiO 2工艺步骤。

22. 发明授权

US5818111A Low capacitance interconnect structures in integrated circuits using a stack of low dielectric materials 失效
标题翻译：使用低电介质材料的集成电路中的低电容互连结构
公开(公告)号：US5818111A
公开(公告)日：1998-10-06
申请号：US821989
申请日：1997-03-21
申请人： Shin-Puu Jeng , Kelly J. Taylor
发明人： Shin-Puu Jeng , Kelly J. Taylor
IPC分类号： H01L21/312 , H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48 , H01L29/52 , H01L29/40
CPC分类号： H01L23/5222 , H01L21/76801 , H01L21/76829 , H01L23/5329 , H01L21/3121 , H01L2924/0002
摘要： An improved method and structure is provided for integrating HSQ and other low dielectric constant materials, which may have undesirable properties, into integrated circuit structures and processes, especially those requiring multiple levels of interconnect lines. The present invention combines the advantages of SiO.sub.2 and low dielectric constant materials by creating a multilayer dielectric stack of alternating layers of low-k materials and traditional dielectrics. A stabilizing layer is inserted between layers of low-k films. Since the thickness of problematic low-k materials remain less than the cracking threshold, many of the problems discussed above are alleviated. The stabilizing prevents the nucleation and propagation of micro cracks. In a preferred embodiment, interconnect lines 14 are first patterned and etched on a substrate 10. A low-k material such as hydrogen silsesquioxane (HSQ) 18 is spun across the surface of the wafer to fill areas between interconnect lines. The HSQ is then heated on a hot plate to cure. A thin dielectric stabilizing layer such as SiO.sub.2 20 can then be applied to on top of the low-k material. A thick SiO.sub.2 planarization layer 22 may then be applied and planarized. In other embodiments, the HSQ and SiO.sub.2 process steps can be repeated for multiple layers of HSQ.
摘要翻译：提供了一种改进的方法和结构，用于将HSQ和其它可能具有不期望的性质的其它低介电常数材料整合到集成电路结构和工艺中，特别是需要多层互连线的那些。本发明通过产生低k材料和传统电介质的交替层的多层电介质堆叠来组合SiO 2和低介电常数材料的优点。将稳定层插入低k膜的层之间。由于有问题的低k材料的厚度仍然小于裂纹阈值，所以上述问题的许多都得到了缓解。稳定防止微裂纹的成核和扩散。在优选实施例中，互连线14首先被图案化并蚀刻在衬底10上。低k材料例如氢倍半硅氧烷（HSQ）18跨越晶片的表面旋转以填充互连线之间的区域。然后将HSQ加热到热板上以固化。然后可以将诸如SiO 2 20的薄介电稳定层施加到低k材料的顶部。然后可以施加和平坦化厚的SiO 2平坦化层22。在其他实施例中，可以针对多层HSQ重复HSQ和SiO 2工艺步骤。

23. 发明授权

US5751582A Controlling process modules using site models and monitor wafer control 失效
标题翻译：使用现场模型控制流程模块并监控晶圆控制
公开(公告)号：US5751582A
公开(公告)日：1998-05-12
申请号：US719104
申请日：1996-09-24
申请人： Sharad Saxena , Purnendu K. Mozumder , Gregory B. Shinn , Kelly J. Taylor
发明人： Sharad Saxena , Purnendu K. Mozumder , Gregory B. Shinn , Kelly J. Taylor
IPC分类号： H01L21/66 , G05B19/418 , H01L21/02 , G06F19/00
CPC分类号： G05B19/41875 , G05B2219/37576 , G05B2219/45026 , G05B2219/45199 , Y02P90/22
摘要： A method is described for controlling a plurality of nonuniformity parameters in processing discrete products such as semiconductor wafers through a module consisting of several individual processes using site models. The method uses a controlled process to compensate for a subsequent uncontrolled process, which allows process goals of one process to be optimized to enhance the output of a subsequent process of the same module.
摘要翻译：描述了一种用于通过使用现场模型的几个单独处理的模块来控制处理离散产物（例如半导体晶片）中的多个不均匀性参数的方法。该方法使用受控过程来补偿后续的不受控制的过程，这允许一个过程的过程目标被优化以增强同一模块的后续过程的输出。

24. 发明授权

US5528153A Method for non-destructive, non-contact measurement of dielectric constant of thin films 失效
标题翻译：非破坏性，非接触式测量薄膜介电常数的方法
公开(公告)号：US5528153A
公开(公告)日：1996-06-18
申请号：US335030
申请日：1994-11-07
申请人： Kelly J. Taylor , Wei-Yung Hsu
发明人： Kelly J. Taylor , Wei-Yung Hsu
IPC分类号： G01R27/26 , G01R31/28 , H01L21/66
CPC分类号： G01R31/2831 , G01R27/2623 , H01L22/14
摘要： A method for measurement of dielectric constant of a thin film is disclosed which is non-destructive and avoids contact with the film and the substrate carrying it. A first characteristic of the substrate is measured using a capacitance measuring device. Then, the thin film is deposited on the substrate. The first characteristic of the substrate is measured a second time after the film has been deposited. Thereafter, the true film thickness is measured. A ratio of the measurements made with the capacitance measuring device is then established with the actual thickness measurement. The dielectric constant can then be derived from a lookup table or graph calibrated for the tools being used for the measurements.
摘要翻译：公开了一种用于测量介电常数的方法，其是非破坏性的，并且避免与膜和携带它的基板接触。使用电容测量装置测量衬底的第一特性。然后，将薄膜沉积在基板上。在膜沉积后第二次测量基板的第一特性。此后，测量真实的膜厚度。然后用实际厚度测量建立用电容测量装置进行的测量的比率。然后可以从为用于测量的工具校准的查找表或图形中导出介电常数。

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