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21. 发明授权

US07977201B2 Methods for forming back-end-of-line resistive semiconductor structures 有权
标题翻译：形成后端电阻半导体结构的方法
公开(公告)号：US07977201B2
公开(公告)日：2011-07-12
申请号：US12191633
申请日：2008-08-14
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , Robert Robison , Yun Shi , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , Robert Robison , Yun Shi , William R. Tonti
IPC分类号： H01L21/20
CPC分类号： H01L23/5228 , H01L21/76816 , H01L23/5226 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a second metal line embedded in a second dielectric layer overlies a first metal line embedded in a first dielectric layer. A portion of the second dielectric layer overlying the first metal line is recessed employing a photoresist and the second metal line as an etch mask. A doped semiconductor spacer is formed within the recess to provide a resistive link between the first metal line and the second metal line. In another embodiment, a first metal line and a second metal line are embedded in a dielectric layer. An area of the dielectric layer laterally abutting the first and second metal lines is recessed employing a photoresist and the first and second metal lines as an etch mask. A doped semiconductor spacer is formed on sidewalls of the first and second metal lines, providing a resistive link between the first and second metal lines.
摘要翻译：在一个实施例中，嵌入在第二介电层中的第二金属线覆盖在嵌入第一介电层中的第一金属线上。覆盖第一金属线的第二电介质层的一部分是使用光致抗蚀剂凹陷的，而第二金属线作为蚀刻掩模。在凹槽内形成掺杂半导体衬垫，以在第一金属线和第二金属线之间提供电阻连接。在另一个实施例中，第一金属线和第二金属线嵌入在电介质层中。使用光致抗蚀剂和第一和第二金属线作为蚀刻掩模来凹入与第一和第二金属线横向邻接的电介质层的区域。掺杂半导体衬垫形成在第一和第二金属线的侧壁上，提供第一和第二金属线之间的电阻连接。

22. 发明授权

US07916531B2 Memory elements and methods of using the same 有权
标题翻译：内存元素和使用方法
公开(公告)号：US07916531B2
公开(公告)日：2011-03-29
申请号：US12351872
申请日：2009-01-12
申请人： Wagdi W. Abadeer , Anthony R Bonaccio , Jack A Mandelman , William R. Tonti , Sebastian T Ventrone
发明人： Wagdi W. Abadeer , Anthony R Bonaccio , Jack A Mandelman , William R. Tonti , Sebastian T Ventrone
IPC分类号： G11C11/34
CPC分类号： G11C16/0466
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由存储元件在第一模式下操作。提供了许多其他方面。

23. 发明授权

US07847605B2 Voltage detection circuit in an integrated circuit and method of generating a trigger flag signal 有权
标题翻译：集成电路中的电压检测电路和产生触发标志信号的方法
公开(公告)号：US07847605B2
公开(公告)日：2010-12-07
申请号：US12242114
申请日：2008-09-30
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , Albert M. Chu , John A. Fifield
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , Albert M. Chu , John A. Fifield
IPC分类号： H03L7/00
CPC分类号： H03K5/153
摘要： An integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.
摘要翻译：一种集成电路，其包括用于产生触发标志信号的至少一个隧道装置电压检测电路。隧道装置电压检测电路包括接收电源电压并具有对应的相应的第一和第二内部节点输出电压的第一和第二分压器。第一和第二分压器被配置为使得第一输出电压相对于电源电压是线性的，并且使得第二输出电压相对于电源电压是非线性的。随着电源电压上升，第一和第二输出电压的曲线在特定电压下交叉。运算放大器电路检测第一和第二输出电压何时相等，并且响应于此，输出指示电源电压达到一定水平的触发信号。

24. 发明授权

US07804124B2 Device structures for a memory cell of a non-volatile random access memory and design structures for a non-volatile random access memory 失效
标题翻译：用于非易失性随机存取存储器的存储器单元的装置结构和用于非易失性随机存取存储器的设计结构
公开(公告)号：US07804124B2
公开(公告)日：2010-09-28
申请号：US12118241
申请日：2008-05-09
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , Yun Shi , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , Yun Shi , William R. Tonti
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/42324
摘要： Device and design structures for memory cells in a non-volatile random access memory (NVRAM). The device structure includes a semiconductor body in direct contact with the insulating layer, a control gate electrode, and a floating gate electrode in direct contact with the insulating layer. The semiconductor body includes a source, a drain, and a channel between the source and the drain. The floating gate electrode is juxtaposed with the channel of the semiconductor body and is disposed between the control gate electrode and the insulating layer. A first dielectric layer is disposed between the channel of the semiconductor body and the floating gate electrode. A second dielectric layer is disposed between the control gate electrode and the floating gate electrode.
摘要翻译：非易失性随机存取存储器（NVRAM）中存储单元的器件和设计结构。器件结构包括与绝缘层直接接触的半导体本体，控制栅电极和与绝缘层直接接触的浮栅电极。半导体本体包括源极，漏极以及源极和漏极之间的沟道。浮置栅电极与半导体本体的沟道并置并且设置在控制栅电极和绝缘层之间。第一电介质层设置在半导体本体的沟道和浮栅之间。第二介电层设置在控制栅电极和浮栅电极之间。

25. 发明申请

US20100230732A1 FIELD EFFECT TRANSISTOR WITH AIR GAP DIELECTRIC 有权
标题翻译：具有气隙介质的场效应晶体管
公开(公告)号：US20100230732A1
公开(公告)日：2010-09-16
申请号：US12547529
申请日：2009-08-26
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , WiIliam R. Tonti , Yun Shi
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , WiIliam R. Tonti , Yun Shi
IPC分类号： H01L29/772 , H01L21/336 , H01L21/30
CPC分类号： H01L29/66795 , H01L29/785
摘要： A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.
摘要翻译：一种场效应晶体管（FET），包括形成在第一平面中的漏极，形成在第一平面中的源极，形成在第一平面中，在漏极和源极之间的沟道以及形成在第一平面中的栅极。门通过气隙与身体的至少一部分分离。气隙也在第一平面。

26. 发明申请

US20100096536A1 ON DEMAND CIRCUIT FUNCTION EXECUTION EMPLOYING OPTICAL SENSING 有权
标题翻译：使用光电传感器的需求电路功能执行
公开(公告)号：US20100096536A1
公开(公告)日：2010-04-22
申请号：US12646292
申请日：2009-12-23
申请人： Wagdi W. Abadeer , James W. Adkisson , Jeffrey S. Brown , Kiran V. Chatty , Robert J. Gauthier, JR. , Michael J. Hauser , Jed H. Rankin , William R. Tonti
发明人： Wagdi W. Abadeer , James W. Adkisson , Jeffrey S. Brown , Kiran V. Chatty , Robert J. Gauthier, JR. , Michael J. Hauser , Jed H. Rankin , William R. Tonti
IPC分类号： G01J1/44
CPC分类号： H01L23/5256 , H01L23/525 , H01L27/14609 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of executing an electrical function, such as a fusing operation, by activation through a chip embedded photodiode through spectrally selected external light activation, and corresponding structure and circuit. The present invention is based on having incident light with specific intensity/wave length characteristics, in conjunction with additional circuit elements to an integrated circuit, perform the implementation of repairs, i.e., replacing failing circuit elements with redundant ones for yield and/or reliability. Also to perform disconnection of ESD protection device from input pad one the packaged chip is placed in system. No additional pins on the package are necessary.
摘要翻译：公开了通过光谱选择的外部光激活通过芯片嵌入式光电二极管的激活以及相应的结构和电路来执行诸如定影操作之类的电功能的方法。本发明基于将具有特定强度/波长特性的入射光结合到集成电路的附加电路元件，执行维修的实现，即用冗余电路替换故障电路元件以获得和/或可靠性。此外，为了将ESD保护装置与输入板断开，将封装的芯片放置在系统中。不需要额外的引脚。

27. 发明申请

US20090267178A1 DEVICE STRUCTURES FOR ACTIVE DEVICES FABRICATED USING A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE AND DESIGN STRUCTURES FOR A RADIOFREQUENCY INTEGRATED CIRCUIT 失效
标题翻译：使用半导体绝缘体衬底制造的主动器件的器件结构和无线电集成电路的设计结构
公开(公告)号：US20090267178A1
公开(公告)日：2009-10-29
申请号：US12108924
申请日：2008-04-24
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William R. Tonti
IPC分类号： H01L29/06
CPC分类号： H01L29/7436 , H01L21/76229 , H01L29/0649 , H01L29/6625 , H01L29/66265 , H01L29/7317 , H01L29/735
摘要： Device structure for active devices fabricated in a semiconductor-on-insulator (SOI) substrate and design structures for a radiofrequency integrated circuit. The device structure includes a first isolation region in the semiconductor layer that extends from a top surface of a semiconductor layer to a first depth, a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth, and a first doped region in the semiconductor layer. The first doped region is disposed vertically between the first isolation region and an insulating layer disposed between the semiconductor layer and a handle wafer of the SOI substrate. The device structure may be included in a design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit.
摘要翻译：用于在绝缘体上半导体（SOI）衬底中制造的有源器件的器件结构和用于射频集成电路的设计结构。器件结构包括半导体层中从半导体层的顶表面延伸到第一深度的第一隔离区域，半导体层中的从半导体层的顶表面延伸到第二深度更大的第二隔离区域比第一深度，以及半导体层中的第一掺杂区域。第一掺杂区域垂直地设置在第一隔离区域和设置在SOI衬底的半导体层和处理晶片之间的绝缘层之间。装置结构可以包括在体现在用于设计，制造或测试集成电路的机器可读介质中的设计结构中。

28. 发明申请

US20090144689A1 Structure for a Voltage Detection Circuit in an Integrated Circuit and Method of Generating a Trigger Flag Signal 有权
标题翻译：集成电路中的电压检测电路的结构和产生触发标志信号的方法
公开(公告)号：US20090144689A1
公开(公告)日：2009-06-04
申请号：US11948308
申请日：2007-11-30
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , Albert M. Chu , John A. Fifield
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , Albert M. Chu , John A. Fifield
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F2217/78
摘要： A design structure for an integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.
摘要翻译：一种用于集成电路的设计结构，其包括用于产生触发标志信号的至少一个隧道装置电压检测电路。隧道装置电压检测电路包括接收电源电压并具有对应的相应的第一和第二内部节点输出电压的第一和第二分压器。第一和第二分压器被配置为使得第一输出电压相对于电源电压是线性的，并且使得第二输出电压相对于电源电压是非线性的。随着电源电压上升，第一和第二输出电压的曲线在特定电压下交叉。运算放大器电路检测第一和第二输出电压何时相等，并且响应于此，输出指示电源电压达到一定水平的触发信号。

29. 发明申请

US20090057804A1 THRESHOLD VOLTAGE COMPENSATION FOR PIXEL DESIGN OF CMOS IMAGE SENSORS 有权
标题翻译： CMOS图像传感器像素设计的阈值电压补偿
公开(公告)号：US20090057804A1
公开(公告)日：2009-03-05
申请号：US11850488
申请日：2007-09-05
申请人： Wagdi W. Abadeer , John A. Fifield
发明人： Wagdi W. Abadeer , John A. Fifield
IPC分类号： H01L31/00 , G06F17/50
CPC分类号： H04N5/374 , H04N5/365 , H04N5/3651 , H04N5/378
摘要： The present disclosure is directed to a CMOS active pixel sensor that compensates for variations in a threshold voltage of a source follower contained therein. A structure in accordance with an embodiment includes: a replica source follower transistor; a system for creating a current in said replica source follower transistor such that a gate-source voltage of said replica source follower is substantially equal to a threshold voltage of said replica source follower; and a current mirror for biasing the isolation source follower transistor at a same current density as the replica source follower transistor.
摘要翻译：本公开涉及一种CMOS有源像素传感器，其补偿其中包含的源极跟随器的阈值电压的变化。根据实施例的结构包括：复制源极跟随器晶体管; 用于在所述复制源跟随器晶体管中产生电流的系统，使得所述复制源极跟随器的栅极 - 源极电压基本上等于所述复制源极跟随器的阈值电压; 以及电流镜，用于以与复制源极跟随器晶体管相同的电流密度偏置隔离源跟随器晶体管。

30. 发明申请

US20090033395A1 MULTIPLE SOURCE-SINGLE DRAIN FIELD EFFECT SEMICONDUCTOR DEVICE AND CIRCUIT 有权
标题翻译：多源单向漏磁场效应半导体器件与电路
公开(公告)号：US20090033395A1
公开(公告)日：2009-02-05
申请号：US11833538
申请日：2007-08-03
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
IPC分类号： H03H11/16 , H03H11/26
CPC分类号： H01L27/0705 , H01L21/823418
摘要： Disclosed are embodiments of a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple source regions is/are selectively biased as well as a function of gate resistance and capacitance. Such a variable-delay FET can be incorporated into a phase adjusting circuit, which uses gate propagation delays to selectively phase adjust an input signal. The phase adjusting circuit can be tuned by incorporating non-salicided resistances and additional capacitance at various positions on the gate structure. The phase adjusting circuit can further be modified into a phase adjusting mixer circuit that enables a phase adjusted signal to be combined with an additional signal.
摘要翻译：公开了具有多个源极区域的可变延迟场效应晶体管（FET）的实施例，其可被单独和选择性地偏置以提供到单个漏极区域的电连接。延迟是多个源极区域中的哪一个被选择性偏置以及栅极电阻和电容的函数的函数。这样的可变延迟FET可以并入相位调整电路中，该相位调整电路使用栅极传播延迟来选择性地相位调整输入信号。相位调整电路可以通过在栅极结构上的各个位置并入非水银电阻和附加电容来调节。相位调整电路可以进一步修改为使相位调整信号与附加信号组合的相位调整混频器电路。

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