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21. 发明授权

US06946747B1 Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US06946747B1
公开(公告)日：2005-09-20
申请号：US10385745
申请日：2003-03-12
申请人： Yukari Mori , Takayuki Ezaki , Teruo Hirayama , Naoto Sasaki , Hiroshi Ozaki , Natsuya Ishikawa
发明人： Yukari Mori , Takayuki Ezaki , Teruo Hirayama , Naoto Sasaki , Hiroshi Ozaki , Natsuya Ishikawa
IPC分类号： H01L25/18 , H01L23/48 , H01L23/52 , H01L25/04 , H01L25/065 , H01L27/10 , H01L29/40
CPC分类号： H01L25/0655 , H01L25/0657 , H01L2224/0401 , H01L2224/04042 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/73207 , H01L2924/15192 , H01L2924/15311 , H01L2924/19107
摘要： A semiconductor device of the MCM type capable of high-speed operation and low power consumption and its manufacturing method are provided. A plurality of semiconductor chips, each having an internal circuit as well as an external connection circuit drawn from the internal circuit, are mounted on the same supporting substrate of this semiconductor device. Semiconductor chips are connected with each other, not by way of the external connection circuits, but directly at a portion between the internal circuits through wiring. This wiring is patterned on an insulating film provided on the supporting substrate and covers the semiconductor chips. Accordingly, through connection holes formed on the insulating film, connection can be established to the internal circuits or the wiring can be formed on the supporting substrate side. If the wiring is formed on the supporting substrate side, the semiconductor chips are to be mounted facing down relative to the supporting substrate.
摘要翻译：提供了能够高速运行和低功耗的MCM型半导体器件及其制造方法。在该半导体装置的同一支撑基板上安装有从内部电路抽出的内部电路以及外部连接电路的多个半导体芯片。半导体芯片彼此连接，而不是通过外部连接电路连接，而是通过布线直接连接在内部电路之间的部分。该布线在设置在支撑基板上的绝缘膜上图案化并覆盖半导体芯片。因此，通过形成在绝缘膜上的连接孔，可以建立与内部电路的连接，或者可以在支撑基板侧上形成布线。如果布线形成在支撑基板侧，则半导体芯片将相对于支撑基板朝下安装。

22. 发明授权

US5814895A Static random access memory having transistor elements formed on side walls of a trench in a semiconductor substrate 失效
标题翻译：具有形成在半导体衬底中的沟槽的侧壁上的晶体管元件的静态随机存取存储器
公开(公告)号：US5814895A
公开(公告)日：1998-09-29
申请号：US769121
申请日：1996-12-19
申请人： Teruo Hirayama
发明人： Teruo Hirayama
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/94
CPC分类号： H01L27/11 , H01L27/1112 , Y10S257/904
摘要： In a static random access memory (SRAM), a memory cell ratio is increased without deteriorating an integration degree of this SRAM. The static random access memory is arranged by: trenches formed in a semiconductor substrate and an insulating layer for isolating elements within a memory cell forming region; one pair of word transistors; one pair of driver transistors for constituting a flip-flop by forming channel regions of the driver transistors in side surfaces of the trenches and by cross-connecting gate electrodes thereof and drain electrodes thereof at one pair of input/output terminals of the flip-flop; and one pair of word transistors connected between the one pair of input/output terminals of the flip-flop and a bit line.
摘要翻译：在静态随机存取存储器（SRAM）中，存储单元比率增加而不降低该SRAM的积分度。静态随机存取存储器通过以下方式排列：形成在半导体衬底中的沟槽和用于隔离存储单元形成区域内的元件的绝缘层; 一对字晶体管; 一对驱动器晶体管，用于通过在沟槽的侧表面中形成驱动晶体管的沟道区域以及通过在其触发器的一对输入/输出端子上与其栅电极和漏电极交叉连接来构成触发器 ; 以及连接在触发器的一对输入/输出端子和位线之间的一对字晶体管。

23. 发明授权

US5719446A Multilayer interconnect structure for semiconductor device and method of manufacturing same 失效
标题翻译：用于半导体器件的多层互连结构及其制造方法
公开(公告)号：US5719446A
公开(公告)日：1998-02-17
申请号：US797925
申请日：1997-02-12
申请人： Mitsuru Taguchi , Keiichi Maeda , Hiroshi Suzawa , Hidenori Kenmotsu , Teruo Hirayama
发明人： Mitsuru Taguchi , Keiichi Maeda , Hiroshi Suzawa , Hidenori Kenmotsu , Teruo Hirayama
IPC分类号： H01L21/203 , H01L21/205 , H01L21/3205 , H01L21/324 , H01L21/768 , H01L23/12 , H01L23/52 , H01L23/522 , H01L23/532 , H01L29/41
CPC分类号： H01L23/5226 , H01L23/53223 , H01L2924/0002 , Y10S257/915
摘要： A multilayer interconnect structure for a semiconductor device. The structure comprises a lower patterned metallization layer, a higher patterned metallization layer, and filled holes for electrically interconnecting these two layers. The two metallization layers are formed out of aluminum or an aluminum alloy by high-temperature aluminum sputtering or aluminum reflow techniques. A suction-preventing layer is formed either at the bottoms of the contact holes or on the surface of the lower metallization layer to prevent the material of the lower metallization layer from being sucked into the overlying contact holes.
摘要翻译：一种用于半导体器件的多层互连结构。该结构包括下图案化的金属化层，较高图案化的金属化层和用于电连接这两层的填充孔。两个金属化层由铝或铝合金通过高温铝溅射或铝回流技术形成。在接触孔的底部或下部金属化层的表面上形成防吸水层，以防止下部金属化层的材料被吸入上覆的接触孔中。

24. 发明授权

US5707919A Catalyst for preparing chlorine from hydrogen chloride 失效
标题翻译：从氯化氢制备氯的催化剂
公开(公告)号：US5707919A
公开(公告)日：1998-01-13
申请号：US552775
申请日：1995-11-03
申请人： Katsuharu Miyata , Jyoji Morisaki , Teruo Hirayama , Hironori Kamachi , Kunihiro Yamada
发明人： Katsuharu Miyata , Jyoji Morisaki , Teruo Hirayama , Hironori Kamachi , Kunihiro Yamada
IPC分类号： B01J23/885 , C01B7/04 , B01J23/26 , B01J23/04 , B01J23/72
CPC分类号： B01J23/885 , C01B7/04 , Y02P20/228
摘要： A method for preparing an improved catalyst for use in the preparation of chlorine by the oxidization of hydrogen chloride with an oxygen-containing gas. The catalyst mainly comprises chromium oxide and can be used for a long period of time particularly under low oxygen content conditions, and the activity of the catalyst does not easily deteriorate, and in other words, the catalyst has a long life. Furthermore, there are disclosed the catalyst obtained by this preparation method, and a method for preparing chlorine from hydrogen chloride by the use of the catalyst. The method for preparing the improved catalyst comprises adding copper, an alkali metal and a rare earth metal, or adding chromium, copper, an alkali metal and a rare earth metal to a catalyst containing chromium oxide as a main component, and then calcining the catalyst at a temperature of 800.degree. C. or less.
摘要翻译：一种通过用含氧气体氧化氯化氢制备用于制备氯的改进催化剂的方法。催化剂主要包含氧化铬，可长时间使用，特别是低氧含量条件下，催化剂的活性不易劣化，换句话说，催化剂寿命长。此外，公开了通过该制备方法获得的催化剂，以及通过使用催化剂从氯化氢制备氯的方法。制备改性催化剂的方法包括加入铜，碱金属和稀土金属，或在含有氧化铬作为主要成分的催化剂中加入铬，铜，碱金属和稀土金属，然后煅烧催化剂温度在800℃以下。

25. 发明授权

US07135378B2 Process for fabricating a semiconductor device having a plurality of encrusted semiconductor chips 有权
标题翻译：用于制造具有多个包层半导体芯片的半导体器件的工艺
公开(公告)号：US07135378B2
公开(公告)日：2006-11-14
申请号：US10719926
申请日：2003-11-21
申请人： Yuji Takaoka , Yukihiro Kamide , Teruo Hirayama , Masaki Hatano
发明人： Yuji Takaoka , Yukihiro Kamide , Teruo Hirayama , Masaki Hatano
IPC分类号： H01L21/76 , H01L21/46 , H01L23/544
CPC分类号： H01L24/82 , H01L21/568 , H01L23/5384 , H01L23/5389 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/24137 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01078 , H01L2924/01082 , H01L2924/12042 , H01L2924/18162 , H01L2924/3512 , H01L2924/00
摘要： A semiconductor device of MCM type allowing high-density assembly and a process of fabricating the same is provided. There are provided semiconductor chips mounted on a supporting substrate and incrusted in an insulation film on the supporting substrate and wiring formed in the insulation film so as to connect to each semiconductor chip through connection holes provided in the insulation film. Then, an interlayer dielectric covers such wiring that is connected to an upper layer wiring, through connection holes provided in such interlayer dielectric. In addition, an upper layer insulation film covers the upper layer wiring, and an electrode, connected to such upper layer wiring through another connection hole, is provided on such upper layer insulation film.
摘要翻译：提供允许高密度组装的MCM型半导体器件及其制造方法。提供安装在支撑基板上的半导体芯片，并且被覆在支撑基板上的绝缘膜和形成在绝缘膜中的布线，以便通过设置在绝缘膜中的连接孔连接到每个半导体芯片。然后，通过设置在该层间电介质中的连接孔，层间电介质覆盖与上层布线连接的布线。此外，上层绝缘膜覆盖上层布线，并且在这种上层绝缘膜上设置有通过另一连接孔连接到这种上层布线的电极。

26. 发明授权

US5225693A CMOS gate array configured as a SRAM with load resistors over gate electrodes 失效
标题翻译： CMOS栅格阵列配置为具有栅极电极的负载电阻的SRAM
公开(公告)号：US5225693A
公开(公告)日：1993-07-06
申请号：US652772
申请日：1991-02-08
申请人： Teruo Hirayama
发明人： Teruo Hirayama
IPC分类号： H01L27/118 , H01L21/82 , H01L21/8244 , H01L27/11
CPC分类号： H01L27/1112 , H01L27/11807 , Y10S257/904
摘要： In a semiconductor memory serving as an SRAM mounted on a CMOS gate array, a memory cell is constituted by a pair of transistors of a first conductivity type channel and a pair of transistors of a second conductivity type channel of the CMOS gate array and load resistances formed on the gate electrodes of the pair of transistors of the first conductivity type channel. Although the CMOS gate array is used, a memory cell area is small and a large capacity can be easily obtained.

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