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    • 21. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US07701786B2
    • 2010-04-20
    • US11528641
    • 2006-09-28
    • Sang-Hee Lee
    • Sang-Hee Lee
    • G11C7/00
    • G11C5/145G11C7/065G11C7/08G11C11/4091G11C2207/065
    • A semiconductor memory device changes a pulse width of an over driving signal according to operation modes, which differ by a degree of accessing memory banks during an over driving operation. An over driver supplies an RTO line of the bit line sense amplifier with an over driving voltage in response to the over driving signal and an over driving signal generator changes a pulse width of the over driving signal according to the operation modes. An increase in the VCORE due to excess supply voltage VDD in the over driving operation is prevented.
    • 半导体存储器件根据操作模式改变过驱动信号的脉冲宽度,该操作模式在过驱动操作期间存取存储体的程度不同。 过驱动器响应于过驱动信号而提供具有过驱动电压的位线读出放大器的RTO线,并且过驱动信号发生器根据操作模式改变过驱动信号的脉冲宽度。 防止过驱动时电源电压VDD过大导致的VCORE增加。
    • 25. 发明授权
    • Semiconductor device and operation method thereof
    • 半导体装置及其动作方法
    • US07616030B2
    • 2009-11-10
    • US12157240
    • 2008-06-09
    • Sang-Hee Lee
    • Sang-Hee Lee
    • H03L7/00
    • H03K5/135H03K5/1565
    • Semiconductor device and operation method thereof includes an aspect of the present invention, there is provided a clock generator configured to receive an external clock signal to generate a first clock signal corresponding to a rising edge of the external clock and a second clock signal corresponding to a falling edge of the external clock, a drive control signal generator configured to restrict an activation period of the first clock signal within a deactivation period of the second clock signal to generate a first drive control signal, and restrict an activation period of the second clock signal within a deactivation period of the first clock signal to generate a second drive control signal and an output driver configured to receive a drive data in response to the first and second drive control signal to drive an output terminal in response to the drive data.
    • 半导体器件及其操作方法包括本发明的一个方面,提供了一种时钟发生器,其被配置为接收外部时钟信号以产生对应于外部时钟的上升沿的第一时钟信号和对应于外部时钟的第二时钟信号 外部时钟的下降沿;驱动控制信号发生器,被配置为在所述第二时钟信号的去激活时段内限制所述第一时钟信号的激活周期,以产生第一驱动控制信号,并且限制所述第二时钟信号的激活周期 在所述第一时钟信号的去激活期间内产生第二驱动控制信号,以及输出驱动器,被配置为响应于所述第一和第二驱动控制信号接收驱动数据,以响应于驱动数据来驱动输出端。
    • 27. 发明申请
    • SEMICONDUCTOR MEMORY DEVICE AND DATA MASKING METHOD OF THE SAME
    • 半导体存储器件及其数据掩蔽方法
    • US20090161445A1
    • 2009-06-25
    • US12137699
    • 2008-06-12
    • Sang Hee Lee
    • Sang Hee Lee
    • G11C7/00G11C8/00
    • G11C7/1078G11C7/1006G11C7/1096
    • A semiconductor memory device has a data masking function during a write operation. The semiconductor memory device includes a data mask input unit that receives a data mask signal. A data input unit receives data and delays the output of the data more than the output of the data mask signal. A write driver selectively drives the data outputted from the data input unit according to the data mask signal outputted from the data mask input unit. The semiconductor memory device ensures that the data mask signal is inputted into the write driver prior to the input of the data, thus preventing a timing mismatch between data and the data masking signal and poor data masking.
    • 半导体存储器件在写入操作期间具有数据屏蔽功能。 半导体存储器件包括接收数据掩模信号的数据掩模输入单元。 数据输入单元接收数据并延迟数据的输出超过数据屏蔽信号的输出。 写入驱动器根据从数据掩码输入单元输出的数据屏蔽信号选择性地驱动从数据输入单元输出的数据。 半导体存储器件确保在输入数据之前将数据掩码信号输入到写入驱动器,从而防止数据与数据屏蔽信号之间的定时失配以及差的数据屏蔽。