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21. 发明授权

US08877594B2 CMOS device for reducing radiation-induced charge collection and method for fabricating the same 有权
标题翻译：用于减少辐射诱导的电荷收集的CMOS器件及其制造方法
公开(公告)号：US08877594B2
公开(公告)日：2014-11-04
申请号：US13509170
申请日：2011-11-30
申请人： Ru Huang , Fei Tan , Xia An , Qianqian Huang , Dong Yang , Xing Zhang
发明人： Ru Huang , Fei Tan , Xia An , Qianqian Huang , Dong Yang , Xing Zhang
IPC分类号： H01L21/00 , H01L29/10 , H01L29/66 , H01L29/78
CPC分类号： H01L29/6653 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： A CMOS device for reducing a radiation-induced charge collection and a method for fabricating the same. In the CMOS device, a heavily doped charge collection-suppressed region is disposed directly under the source region and the drain region. The region has a doping type opposite that of the source region and the drain region, and has a doping concentration not less than that of the source region and the drain region. The charge collection-suppressed region has a lateral part slightly less than or equal to that of the source region and the drain region, and has a lateral range toward to the channel not exceed the edges of the source region and the drain region. The CMOS device may greatly reduce a range of the funnel that appears under the action of a single particle, so that charges collected instantaneously under a force of an electric field may be reduced.
摘要翻译：用于减少辐射诱导的电荷收集的CMOS器件及其制造方法。在CMOS器件中，重掺杂电荷收集抑制区域直接设置在源极区域和漏极区域的正下方。该区域具有与源极区域和漏极区域相反的掺杂类型，并且具有不小于源极区域和漏极区域的掺杂浓度。电荷收集抑制区域具有稍小于或等于源极区域和漏极区域的横向部分，并且具有朝向沟道的横向范围不超过源极区域和漏极区域的边缘。 CMOS器件可以大大减少在单个粒子的作用下出现的漏斗的范围，使得可以在电场的力作用下立即收集的电荷减少。

22. 发明授权

US08807791B2 Illuminating device with adjustable light beams and method for assembling the same 有权
标题翻译：具有可调光束的照明装置及其组装方法
公开(公告)号：US08807791B2
公开(公告)日：2014-08-19
申请号：US13452065
申请日：2012-04-20
申请人： Chun-Ru Huang , Chien-Yueh Chen
发明人： Chun-Ru Huang , Chien-Yueh Chen
IPC分类号： F21V1/00
CPC分类号： F21V5/002 , F21V3/00 , F21V5/04 , F21V7/06 , F21V7/07 , F21V7/08 , F21V23/04 , F21Y2105/10 , F21Y2105/12 , F21Y2115/10 , H05B33/0842
摘要： An illuminating device with adjustable light beams and a method for assembling the same. The light-emitting units are disposed on the substrate. The optical element is disposed in the path of a light emitted by at least one of the light-emitting units. The driving unit drives a first or second set of the light-emitting units, wherein a light beam formed by light that is emitted by the first set of the light-emitting units and passes through the optical element has a different shape or projection angle from a light beam formed by light that is emitted by the second set of the light-emitting units and passes through the optical element.
摘要翻译：具有可调节光束的照明装置及其组装方法。发光单元设置在基板上。光学元件设置在由至少一个发光单元发射的光的路径中。驱动单元驱动第一组或第二组发光单元，其中由第一组发光单元发射并通过光学元件的由光形成的光束具有与由第二组发光单元发射并通过光学元件的由光形成的光束。

23. 发明申请

US20140167080A1 LIGHT EMITTING DEVICE 有权
标题翻译：发光装置
公开(公告)号：US20140167080A1
公开(公告)日：2014-06-19
申请号：US13831965
申请日：2013-03-15
申请人： Jing-En Huang , Yi-Ru Huang , Chih-Ling Wu , Yu-Yun Lo
发明人： Jing-En Huang , Yi-Ru Huang , Chih-Ling Wu , Yu-Yun Lo
IPC分类号： H01L27/15
CPC分类号： H01L27/153 , H01L33/10 , H01L33/20 , H01L33/36 , H01L33/40 , H01L33/405 , H01L33/44 , H01L33/46 , H01L33/62 , H01L2924/0002 , H01L2924/00
摘要： A light emitting device includes a substrate, light emitting units, an insulation layer, a current distribution layer and a reflective layer. The substrate has an upper surface. The light emitting units are disposed on the upper surface and include at least one first light emitting diode (LED) and at least one second LED. A first side wall of the first LED is adjacent to a second side wall of the second LED so as to define a concave portion exposing a portion of the upper surface. The insulation layer at least covers the first side wall and the second side wall. The current distribution layer covers the concave portion and at least covers a portion of the second LED. The reflective layer covers the current distribution layer and is electrically connected to the first LED and the second LED.
摘要翻译：发光器件包括衬底，发光单元，绝缘层，电流分布层和反射层。基板具有上表面。发光单元设置在上表面上并且包括至少一个第一发光二极管（LED）和至少一个第二LED。第一LED的第一侧壁与第二LED的第二侧壁相邻，以限定暴露上表面的一部分的凹部。绝缘层至少覆盖第一侧壁和第二侧壁。电流分布层覆盖凹部，并且至少覆盖第二LED的一部分。反射层覆盖电流分布层并电连接到第一LED和第二LED。

24. 发明授权

US08652929B2 CMOS device for reducing charge sharing effect and fabrication method thereof 有权
标题翻译：用于降低电荷共享效应的CMOS器件及其制造方法
公开(公告)号：US08652929B2
公开(公告)日：2014-02-18
申请号：US13582034
申请日：2012-04-16
申请人： Ru Huang , Fei Tan , Xia An , Qianqian Huang , Dong Yang , Xing Zhang
发明人： Ru Huang , Fei Tan , Xia An , Qianqian Huang , Dong Yang , Xing Zhang
IPC分类号： H01L21/00 , H01L21/02 , H01L21/3063 , H01L21/84
CPC分类号： H01L21/02203 , H01L21/02216 , H01L21/3063 , H01L21/823878 , H01L27/0921
摘要： The present invention discloses a CMOS device of reducing charge sharing effect and a fabrication method thereof. The present invention has an additional isolation for trapping carriers disposed right below an isolation region. the material of the additional isolation region is porous silicon. Since porous silicon is a functional material of spongy structure by electrochemistry anodic oxidizing monocrystalline silicon wafer, there are a large number of microvoids and dangling bonds on the surface layer of the porous silicon. These defects may form defect states in a center of forbidden band of the porous silicon, the defect states may trap carriers so as to cause an increased resistance. And with an increase of density of corrosion current, porosity increases, and defects in the porous silicon increase. The present invention can reduce the charge sharing effect due to heavy ions by using a feature that the defect states in the porous silicon trap carriers, the formation of a shallow trench isolation (STI) region and a isolation region underneath only needs one time photolithography, and the process is simple, so that radioresistance performance of an integrated circuit may be greatly increased.
摘要翻译：本发明公开了一种降低电荷共享效应的CMOS器件及其制造方法。本发明对于设置在隔离区域正下方的捕获载体具有额外的隔离。附加隔离区的材料是多孔硅。由于多孔硅是通过电化学阳极氧化单晶硅晶片的海绵结构的功能材料，因此在多孔硅的表面层上存在大量微孔和悬挂键。这些缺陷可能在多孔硅的禁带的中心形成缺陷状态，缺陷状态可能会捕获载体以引起增加的电阻。随着腐蚀电流密度的增加，孔隙率增加，多孔硅中的缺陷增加。本发明可以通过使用多孔硅捕集载体中的缺陷状态，浅沟槽隔离（STI）区域的形成和下面的隔离区域仅需要一次光刻来降低由于重离子引起的电荷共享效应，并且该工艺简单，从而可以大大提高集成电路的射电阻性能。

25. 发明授权

US08598636B2 Heat dissipation structure of SOI field effect transistor 有权
标题翻译： SOI场效应晶体管的散热结构
公开(公告)号：US08598636B2
公开(公告)日：2013-12-03
申请号：US13582624
申请日：2011-08-17
申请人： Ru Huang , Xin Huang , Shoubin Xue , Yujie Ai
发明人： Ru Huang , Xin Huang , Shoubin Xue , Yujie Ai
IPC分类号： H01L29/80
CPC分类号： H01L23/38 , H01L27/16 , H01L2924/0002 , H01L2924/00
摘要： The present invention discloses a heat dissipation structure for a SOI field effect transistor having a schottky source/drain, which relates to a field of microelectronics. The heat dissipation structure includes two holes connected with a drain terminal or with both a source terminal and a drain terminal, which are filled with an N-type material with high thermoelectric coefficient and a P-type material with high thermoelectric coefficient respectively. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a high potential with respect to the drain terminal, and a metal wire for the P-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a low potential with respect to the drain terminal. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the source terminal is applied a high potential with respect to the source terminal, and a metal wire for the P-type material in the vicinity of the source terminal is applied a lower potential with respect to the source terminal. By way of a Peltier effect, in the present invention heat can be absorbed at a contact portion between the thermoelectric material and the source/drain, and at the same time dissipated at a connection portion between the thermoelectric material and a bottom electrode metal, so that the heat generated in an active region of the device is effectively transferred to the substrate and dissipated through a heat sink.
摘要翻译：本发明公开了一种具有肖特基源极/漏极的SOI场效应晶体管的散热结构，涉及微电子领域。散热结构包括与漏极端子或者源极端子和漏极端子连接的两个孔，其分别填充有高热电系数的N型材料和具有高热电系数的P型材料。在漏极端子附近，用于具有高热电系数的N型材料的金属线相对于漏极端子施加高电位，并且用于具有高热电系数的P型材料的金属线漏极端子相对于漏极端子施加低电位。在源极端子附近具有高热电系数的N型材料的金属线相对于源极端子施加高电位，并且在源极端子附近的用于P型材料的金属线是相对于源极端子施加较低的电位。通过珀耳帖效应，在本发明中，热量可以在热电材料和源极/漏极之间的接触部分处被吸收，并且同时在热电材料和底部电极金属之间的连接部分消散，因此在器件的有源区域中产生的热量有效地传递到衬底并通过散热器散发。

26. 发明授权

US08563370B2 Method for fabricating surrounding-gate silicon nanowire transistor with air sidewalls 有权
标题翻译：用于制造具有空气侧壁的环形栅极硅纳米线晶体管的方法
公开(公告)号：US08563370B2
公开(公告)日：2013-10-22
申请号：US13384215
申请日：2011-07-04
申请人： Ru Huang , Jing Zhuge , Jiewen Fan , Yujie Ai , Runsheng Wang , Xin Huang
发明人： Ru Huang , Jing Zhuge , Jiewen Fan , Yujie Ai , Runsheng Wang , Xin Huang
IPC分类号： H01L21/338
CPC分类号： H01L29/78696 , H01L21/76289 , H01L29/0673 , H01L29/42392 , H01L29/66772
摘要： A method for fabricating a surrounding-gate silicon nanowire transistor with air sidewalls is provided. The method is compatible with the CMOS process; the introduced air sidewalls can reduce the parasitic capacitance effectively and increase the transient response characteristic of the device, thus being applicable to a high-performance logic circuit.
摘要翻译：提供了一种制造具有空气侧壁的环形栅极硅纳米线晶体管的方法。该方法与CMOS工艺兼容; 引入的空气侧壁可以有效地减小寄生电容并增加器件的瞬态响应特性，从而适用于高性能逻辑电路。

27. 发明授权

US08536639B2 I-shape floating gate for flash memory device and fabricating the same 有权
标题翻译：用于闪存器件的I形浮动栅极和制造它们
公开(公告)号：US08536639B2
公开(公告)日：2013-09-17
申请号：US13498585
申请日：2011-11-30
申请人： Yimao Cai , Song Mei , Ru Huang
发明人： Yimao Cai , Song Mei , Ru Huang
IPC分类号： H01L29/788 , H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28273
摘要： The present invention discloses a floating gate structure of a flash memory device and a method for fabricating the same, which relates to a nonvolatile memory in a manufacturing technology of an ultra-large-scaled integrated circuit. In the invention, by modifying a manufacturing of a floating gate in the a standard process for the flash memory, that is, by adding three steps of deposition, two steps of etching and one step of CMP, an -shaped floating gate is formed. In addition to these steps, all the other steps are the same as those of the standard process for the flash memory process. By the invention, a coupling ratio may be improved effectively and a crosstalk between adjacent devices may be lowered, without adding additional photomasks and barely increasing a process complexity, which are very important to improve programming speed and reliability.
摘要翻译：本发明公开了一种闪存器件的浮动栅极结构及其制造方法，涉及超大规模集成电路的制造技术中的非易失性存储器。在本发明中，通过在闪速存储器的标准处理中，即通过添加三个步骤的沉积，两个步骤的蚀刻和CMP的一个步骤来修改浮动栅极的制造，形成一个形状的浮动栅极。除了这些步骤之外，所有其他步骤与闪存过程的标准过程相同。通过本发明，可以有效地改善耦合比，并且可以降低相邻器件之间的串扰，而不增加额外的光掩模，并且几乎不增加工艺复杂性，这对于提高编程速度和可靠性非常重要。

28. 发明授权

US08526242B2 Flash memory and fabrication method and operation method for the same 有权
标题翻译：闪存及其制作方法及操作方法相同
公开(公告)号：US08526242B2
公开(公告)日：2013-09-03
申请号：US13321120
申请日：2011-03-07
申请人： Ru Huang , Yimao Cai , Shiqiang Qin , Qianqian Huang , Poren Tang , Yu Tang , Gengyu Yang
发明人： Ru Huang , Yimao Cai , Shiqiang Qin , Qianqian Huang , Poren Tang , Yu Tang , Gengyu Yang
IPC分类号： G11C11/34
CPC分类号： H01L27/11556 , H01L29/7391 , H01L29/7889 , H01L29/8616
摘要： The present invention discloses a flash memory and the fabrication method and the operation method for the same. The flash memory comprises two memory cells of vertical channels, wherein a lightly-doped N type (or P type) silicon is used as a substrate; a P+ region (or an N+ region) is provided on each of the both ends of the silicon surface, and two channel regions perpendicular to the surface are provided therebetween; an N+ region (or a P+ region) shared by two channels is provided over the channels; a tunneling oxide layer, a polysilicon floating gate, a block oxide layer and a polysilicon control gate are provided sequentially on the outer sides of each channel from inside to outside; and the polysilicon floating gate and the polysilicon control gate are isolated from the P+ region by a sidewall oxide layer. The whole device is a two-bit TFET type flash memory with vertical channels which has better compatibility with prior-art standard CMOS process. As compared with a conventional MOSFET-based flash memory, the flash memory according to the present invention possesses various advantages such as high programming efficiency, low power consumption, effective inhibition of punch-through effect, and high density, etc.
摘要翻译：本发明公开了一种闪存及其制作方法及其操作方法。闪速存储器包括两个垂直通道的存储单元，其中使用轻掺杂N型（或P型）硅作为衬底; 在硅表面的两端分别设置有P +区域（或N +区域），并且在两面之间设置与该表面垂直的2个沟道区域。在通道上设置由两个通道共享的N +区域（或P +区域）; 隧道氧化物层，多晶硅浮置栅极，块状氧化物层和多晶硅控制栅极，从内向外依次设置在每个沟道的外侧上; 并且多晶硅浮置栅极和多晶硅控制栅极通过侧壁氧化物层与P +区域隔离。整个器件是具有垂直通道的两位TFET型闪存，与现有的标准CMOS工艺具有更好的兼容性。与传统的基于MOSFET的闪存相比，根据本发明的闪速存储器具有诸如编程效率高，功耗低，穿透效果有效抑制和高密度等各种优点。

29. 发明授权

US08476672B2 Electrostatic discharge protection device and method for fabricating the same 有权
标题翻译：静电放电保护装置及其制造方法
公开(公告)号：US08476672B2
公开(公告)日：2013-07-02
申请号：US13201370
申请日：2011-04-02
申请人： Ru Huang , Lijie Zhang
发明人： Ru Huang , Lijie Zhang
IPC分类号： H01L29/86 , H01L21/329
CPC分类号： H01L29/87 , H01L27/0262 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an ESD protection device comprising a SCR structure that is a transverse PNPN structure formed by performing a P-type implantation and an N-type implantation in an N-well and a P-well on a silicon substrate, respectively, wherein a P-type doped region in the N-well is used as an anode, and N-type doped region in the P-well is used as a cathode, characterized in that, N-type dopants are implanted into the N-well to form one lead-out terminal of a resistor, P-type dopants are implanted into the P-well to form another lead-out terminal for the resistor, and the two leading-out terminals are connected by the resistor.
摘要翻译：本发明提供一种ESD保护装置，其包括SCR结构，其是分别通过在硅衬底上的N阱和P阱中执行P型注入和N型注入而形成的横向PNPN结构，其中 N阱中的P型掺杂区域用作阳极，P阱中的N型掺杂区域用作阴极，其特征在于，将N型掺杂剂注入到N阱中，形成电阻器的一个引出端子，将P型掺杂剂注入到P阱中以形成用于电阻器的另一引出端子，并且两个引出端子由电阻器连接。

30. 发明申请

US20130141183A1 DIRECTIONAL COUPLER INTEGRATED BY CMOS PROCESS 有权
标题翻译： CMOS工艺集成的方向耦合器
公开(公告)号：US20130141183A1
公开(公告)日：2013-06-06
申请号：US13641647
申请日：2012-04-16
申请人： Le Ye , Jiayi Wang , Huailin Liao , Ru Huang
发明人： Le Ye , Jiayi Wang , Huailin Liao , Ru Huang
IPC分类号： H01P5/16
CPC分类号： H01P5/184 , H01P5/187
摘要： A directional coupler is disclosed integrated on a single chip and an integrated circuit based on a standard CMOS process and relates to a field of radio frequency communication. In exemplary implementations, by using a standard CMOS process technology, the directional coupler integrated by a CMOS process is formed by a coil winded by a upper layer of metal lines, a coil winded by a lower layer of metal lines, two tuning capacitor array, and a matching resistor. Two terminals of the coil are a direct terminal and an input terminal; two terminals of the coil are a coupled terminal and an isolation terminal; the terminals of the coils and are intersected at 90°; the coil is winded by an upper metal layer and the coil is winded by a lower metal layer. Further, the insertion loss is low and the isolation degree is large.
摘要翻译：公开了一种集成在单个芯片上的定向耦合器和基于标准CMOS工艺的集成电路，涉及射频通信领域。在示例性实施方案中，通过使用标准CMOS工艺技术，由CMOS工艺集成的定向耦合器由金属线上层缠绕的线圈，由金属线下层缠绕的线圈，两个调谐电容器阵列，和匹配电阻。线圈的两个端子是直接端子和输入端子; 线圈的两个端子是耦合端子和隔离端子; 线圈的端子和90°相交; 线圈被上金属层缠绕，线圈被下金属层缠绕。此外，插入损耗低，隔离度大。

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