专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07283417B2 Write control circuitry and method for a memory array configured with multiple memory subarrays 失效
标题翻译：用于配置有多个存储器子阵列的存储器阵列的写控制电路和方法
公开(公告)号：US07283417B2
公开(公告)日：2007-10-16
申请号：US11054059
申请日：2005-02-09
申请人： John D. Davis , Paul A. Bunce , Donald W. Plass , Kenneth J. Reyer
发明人： John D. Davis , Paul A. Bunce , Donald W. Plass , Kenneth J. Reyer
IPC分类号： G11C8/00
CPC分类号： G11C11/413 , G11C7/18
摘要： Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal.
摘要翻译：为配置有多个存储器子阵列的存储器阵列提供写控制电路和控制方法。写控制电路包括与多个存储器子阵列相关联的多个子阵列写控制器，每个子阵列写控制器选择性地使本地写控制信号到其相关的存储器子阵列。选择性地使能响应于接收的子阵列选择信号，其中一次只有一个子阵列选择信号是有效的。至少一些子阵列写控制器至少部分地通过交换式电源节点供电，其中，在子阵列写入控制器之间分配地实现切换的功率节点的供电。在一个示例中，通过分布在子阵列写控制器之间的多个反相器实现开关电源节点的分布式实现的供电，每个反相器具有耦合到开关电源节点的输出，以及耦合以接收全局写使能信号的输入。

22. 发明授权

US07266737B2 Method for enabling scan of defective ram prior to repair 有权
标题翻译：修复前能够对有缺陷的公牛进行扫描的方法
公开(公告)号：US07266737B2
公开(公告)日：2007-09-04
申请号：US11180416
申请日：2005-07-13
申请人： Paul A. Bunce , John D. Davis , Patrick J. Meaney , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , Patrick J. Meaney , Donald W. Plass
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G01R31/318533 , G11C29/88 , G11C2029/3202
摘要： A semiconductor memory circuit enabling replacement of defective memory elements and associated circuitry with non-defective spare elements of the RAM and associated circuitry, is scanned to enable replacement of a defective RAM element prior to repair of the RAM. A set of set/reset latches are coupled to receive the signal from the memory elements, and a multiplexer control circuit coupled to receive a shift signal and a ram_inhibit signal from a multiplexer to provide specific input signals to the multiplexer components. When a scan operation begins an active clock signal sets a set/reset latch to ram_inhibit mode and this blocks the memory elements from influencing the state of memory output latches, whereby when an memory operation begins, an active clocking signal will reset the set/reset latch into system mode to cause the multiplexers pass appropriate signals from the memory elements to the output latches, and the spare memory element is activated to replace a defective memory element.
摘要翻译：扫描能够用RAM和关联电路的无缺陷备用元件替换缺陷存储器元件和相关电路的半导体存储器电路，以便在修复RAM之前更换有缺陷的RAM元件。耦合一组置位/复位锁存器以接收来自存储器元件的信号，以及多路复用器控制电路，其被耦合以从多路复用器接收移位信号和ram_inhibit信号以向多路复用器部件提供特定的输入信号。当扫描操作开始时，活动时钟信号将设置/复位锁存器设置为ram_inhibit模式，并且阻止存储器元件影响存储器输出锁存器的状态，由此当存储器操作开始时，有源时钟信号将复位置位/复位锁存到系统模式以使多路复用器将适当的信号从存储器元件传递到输出锁存器，并且备用存储器元件被激活以替换有缺陷的存储器元件。

23. 发明申请

US20070033459A1 Method for enabling scan of defective ram prior to repair 有权
公开(公告)号：US20070033459A1
公开(公告)日：2007-02-08
申请号：US11180416
申请日：2005-07-13
申请人： Paul A. Bunce , John D. Davis , Patrick J. Meaney , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , Patrick J. Meaney , Donald W. Plass
IPC分类号： G01R31/28
CPC分类号： G11C29/48 , G01R31/318533 , G11C29/88 , G11C2029/3202
摘要： A semiconductor memory circuit enabling replacement of defective memory elements and associated circuitry with non-defective spare elements of the RAM and associated circuitry, is scanned to enable replacement of a defective RAM element prior to repair of the RAM. A set of set/reset latches are coupled to receive the signal from the memory elements, and a multiplexer control circuit coupled to receive a shift signal and a ram_inhibit signal from a multiplexer to provide specific input signals to the multiplexer components. When a scan operation begins an active clock signal sets a set/reset latch to ram_inhibit mode and this blocks the memory elements from influencing the state of memory output latches, whereby when an memory operation begins, an active clocking signal will reset the set/reset latch into system mode to cause the multiplexers pass appropriate signals from the memory elements to the output latches, and the spare memory element is activated to replace a defective memory element.

24. 发明授权

US07075855B1 Memory output timing control circuit with merged functions 失效
标题翻译：具有合并功能的存储器输出定时控制电路
公开(公告)号：US07075855B1
公开(公告)日：2006-07-11
申请号：US11053612
申请日：2005-02-08
申请人： Paul A. Bunce , John D. Davis , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , Donald W. Plass
IPC分类号： G11C8/00
CPC分类号： G11C11/413 , G11C7/12 , G11C29/846
摘要： An output timing control circuit for use with a memory array. The output timing control circuit includes a redundancy decode circuit and a bit column output circuit. The bit column output circuit includes a first bit column output gate and a second bit column output gate, each bit column output gate is coupled to a bitline in the memory array. A precharge circuit is coupled to an output of the first bit column output gate and the second bit column output gate. The precharge circuit is responsive to a port enable signal. The redundancy decode circuit receives the port enable signal and a fuse signal and activates one of the first bit column output gate and the second bit column output gate.
摘要翻译：一种与存储器阵列一起使用的输出定时控制电路。输出定时控制电路包括冗余解码电路和位列输出电路。位列输出电路包括第一位列输出栅极和第二位列输出栅极，每个位列输出栅极耦合到存储器阵列中的位线。预充电电路耦合到第一位列输出栅极和第二位列输出栅极的输出端。预充电电路响应端口使能信号。冗余解码电路接收端口使能信号和熔丝信号，并激活第一位列输出栅极和第二位列输出栅极之一。

25. 发明授权

US06822885B2 High speed latch and compare function 失效
标题翻译：高速锁存和比较功能
公开(公告)号：US06822885B2
公开(公告)日：2004-11-23
申请号：US10413615
申请日：2003-04-14
申请人： Paul A. Bunce , John D. Davis , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , Donald W. Plass
IPC分类号： G11C700
CPC分类号： G06F12/0895 , G11C7/1006 , G11C15/04 , G11C2207/104 , G11C2207/2245
摘要： A high speed latch and compare function providing rapid cache comparison through the use of a dual rail comparison circuit having transmission gate exclusive or (XOR) circuits.
摘要翻译：通过使用具有传输门专用或（XOR）电路的双轨比较电路，提供快速缓存比较的高速锁存和比较功能。

26. 发明授权

US08345497B2 Internal bypassing of memory array devices 有权
标题翻译：内存阵列设备的内部旁路
公开(公告)号：US08345497B2
公开(公告)日：2013-01-01
申请号：US12822058
申请日：2010-06-23
申请人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
发明人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
IPC分类号： G11C7/00
CPC分类号： G11C16/02 , G11C7/1048 , G11C11/413 , G11C2207/002
摘要： An output control circuit for a memory array includes a latched output node precharged to a first logic state prior to both a read and write operation; first logic that couples memory cell data from a memory read path to the output node during the read operation, the first logic controlled by a timing signal; second logic that internally bypasses the memory read path during a write operation by decoupling it from the output node, such that a logical derivative of write data written to the memory array is also coupled to the output node, the second logic also controlled by the timing signal; and wherein a transition of the output node from the first logic state to a second logic state during the write operation occurs within a time range as that of the same transition during the read operation.
摘要翻译：用于存储器阵列的输出控制电路包括在读取和写入操作之前预先充电到第一逻辑状态的锁存输出节点; 在读取操作期间将存储器单元数据从存储器读取路径耦合到输出节点的第一逻辑，由定时信号控制的第一逻辑; 第二逻辑，其在写入操作期间通过将其与输出节点分离而在内部旁路存储器读取路径，使得写入存储器阵列的写入数据的逻辑导数也耦合到输出节点，第二逻辑也由定时控制信号; 并且其中，所述输出节点在所述写入操作期间从所述第一逻辑状态到第二逻辑状态的转变在与所述读取操作期间相同转换的时间范围内发生。

27. 发明授权

US07299374B2 Clock control method and apparatus for a memory array 有权
标题翻译：用于存储器阵列的时钟控制方法和装置
公开(公告)号：US07299374B2
公开(公告)日：2007-11-20
申请号：US11050580
申请日：2005-02-03
申请人： James W. Dawson , Paul A. Bunce , Donald W. Plass , Kenneth J. Reyer
发明人： James W. Dawson , Paul A. Bunce , Donald W. Plass , Kenneth J. Reyer
IPC分类号： G06F1/08 , G06F1/04
CPC分类号： G06F1/04 , G11C7/22 , G11C7/222 , G11C7/227
摘要： A clock control method and apparatus are provided employing a clock control circuit which generates an array clock for a memory array from a system clock and a reset control signal. The reset control signal is one of a plurality of input control signals to the clock control circuit. When the system clock is below a predefined frequency threshold, the reset control signal is an array tracking reset signal, wherein the active pulse width of the array clock is system clock frequency independent, and when the system clock is above the predefined frequency threshold, the reset control signal is a mid-cycle reset signal, meaning that the active pulse width of the array clock is system clock frequency dependent. A bypass signal is provided as a third input control signal, which when active causes the clock control circuit to output an array clock which mirrors the system clock.
摘要翻译：提供了一种时钟控制方法和装置，其采用从系统时钟和复位控制信号产生用于存储器阵列的阵列时钟的时钟控制电路。复位控制信号是到时钟控制电路的多个输入控制信号之一。当系统时钟低于预定频率阈值时，复位控制信号是阵列跟踪复位信号，其中阵列时钟的有效脉冲宽度是系统时钟频率无关的，当系统时钟高于预定频率阈值时，复位控制信号是中周期复位信号，意味着阵列时钟的有效脉冲宽度取决于系统时钟。提供旁路信号作为第三输入控制信号，当有效时，时钟控制电路输出反映系统时钟的阵列时钟。

28. 发明授权

US07099203B1 Circuit and method for writing a binary value to a memory cell 失效
标题翻译：将二进制值写入存储单元的电路和方法
公开(公告)号：US07099203B1
公开(公告)日：2006-08-29
申请号：US11057281
申请日：2005-02-11
申请人： Paul A. Bunce , John D. Davis , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , Donald W. Plass
IPC分类号： G11C7/10 , G11C11/00
CPC分类号： G11C7/22 , G11C2207/2263
摘要： A circuit and a method for writing a binary value to a memory cell are provided. The circuit includes a first field-effect transistor having a first drain, a first drain, and a first gate operably coupled between the first drain and the first source. The first drain is operably coupled to a first memory cell. The first gate configured to receive a first data signal. The circuit further includes a second field-effect transistor having a second drain, a second source, and a second gate operably coupled between the second drain and the second source. The drain source is operably coupled to the first memory cell. The second gate is configured to receive a second data signal. The circuit further includes a first signal inverter having a first input terminal and a first output terminal. The first output terminal is operably coupled to both of the first and second sources. The first signal inverter is configured to output a first control signal on the first output terminal when the first input terminal receives a second control signal. When the first control signal has a second logic level and the first data signal has a first logic level and the second data signal has the second logic level, the first and second field-effect transistors induce the first memory cell to store a first binary value.
摘要翻译：提供了一种将二进制值写入存储单元的电路和方法。电路包括具有第一漏极，第一漏极和第一栅极的第一场效应晶体管，其可操作地耦合在第一漏极和第一源极之间。第一漏极可操作地耦合到第一存储器单元。第一门被配置为接收第一数据信号。电路还包括第二场效应晶体管，其具有可操作地耦合在第二漏极和第二源之间的第二漏极，第二源极和第二栅极。漏源可操作地耦合到第一存储单元。第二门被配置为接收第二数据信号。电路还包括具有第一输入端和第一输出端的第一信号反相器。第一输出端子可操作地耦合到第一和第二源两者。第一信号反相器被配置为当第一输入端子接收到第二控制信号时，在第一输出端子上输出第一控制信号。当第一控制信号具有第二逻辑电平且第一数据信号具有第一逻辑电平且第二数据信号具有第二逻辑电平时，第一和第二场效应晶体管感应第一存储器单元以存储第一二进制值。

29. 发明授权

US06728912B2 SOI cell stability test method 失效
标题翻译： SOI电池稳定性试验方法
公开(公告)号：US06728912B2
公开(公告)日：2004-04-27
申请号：US09833724
申请日：2001-04-12
申请人： James W. Dawson , Paul A. Bunce , Donald W. Plass
发明人： James W. Dawson , Paul A. Bunce , Donald W. Plass
IPC分类号： G11C2900
CPC分类号： G11C29/12 , G11C8/08 , G11C29/34
摘要： A method for testing SOI technology memory circuits, such as in SRAMs, for weak SOI cells, uses a reset test circuit with a wordline pulse width control circuit which can be implemented without performance impact and allows using unused silicon to minimize area usage impact and permits screening of integrated SOI memory array circuits for weak SOI cells using the test reset circuit to selectively change the wordline pulse width to a reduced time while the memory cell bit select and write signals turn off at normal times to stress the cell write margin. Further, during test, the word line pulse width can be extended by blocking the reset signal of the reset path test circuit to the word path to produce a longer than normal pulse width. In addition, during a test for normal operations the reset signal is allowed to pass through a pass gate multiplexer of the reset test circuit.
摘要翻译：用于测试SOI技术存储器电路（例如SRAM）中用于弱SOI单元的方法使用具有字线脉冲宽度控制电路的复位测试电路，该电路可以在没有性能影响的情况下实现，并允许使用未使用的硅来最小化区域使用影响并允许使用测试复位电路筛选用于弱SOI单元的集成SOI存储器阵列电路，以便在正常时间存储单元位选择和写入信号关断以压缩单元写入裕度时选择性地将字线脉冲宽度改变为减小的时间。此外，在测试期间，可以通过将复位路径测试电路的复位信号阻塞到字路径来延长字线脉冲宽度，以产生比正常脉冲宽度更长的字线。此外，在正常操作的测试期间，允许复位信号通过复位测试电路的通过门极复用器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式