专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20120221909A1 SHADOW ACCESS PORT METHOD AND APPARATUS 有权
标题翻译：阴影访问端口方法和设备
公开(公告)号：US20120221909A1
公开(公告)日：2012-08-30
申请号：US13469812
申请日：2012-05-11
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177 , G01R31/318536 , G01R31/318544 , G01R31/318555
摘要： The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.
摘要翻译：本公开描述了一种用于在设备内提供影子接入端口的新颖的方法和装置。访问影子访问端口，通过重用用于操作设备中测试访问端口的TDI，TMS，TCK和TDO信号来对设备执行操作。影子访问端口的存在和操作对于测试访问端口的存在和操作是透明的。根据本公开，阴影访问端口在TCK信号的下降沿操作，而测试访问端口通常在TCK信号的上升沿操作。

22. 发明授权

US08255751B2 Scan router connected with TAM core and test circuitry 有权
标题翻译：连接TAM核心和测试电路的扫描路由器
公开(公告)号：US08255751B2
公开(公告)日：2012-08-28
申请号：US13093414
申请日：2011-04-25
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/318555 , G01R31/318563
摘要： A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.
摘要翻译：提供了一种器件测试体系结构和接口，可以高效地测试器件内的嵌入式内核。测试架构与标准IEEE 1500核心测试包装器相连接，并从外部测试仪器向封装器提供高测试数据带宽。测试架构包括比较电路，允许比较要在设备内执行的测试响应数据。测试架构还包括用于存储测试响应比较结果的存储器。测试架构包括一个可编程测试控制器，通过从外部测试仪简单地向可编程测试控制器输入指令来允许各种测试控制操作。测试架构包括用于选择用于测试的核心的选择器电路。还公开了设备测试架构的附加特征和实施例。

23. 发明授权

US08225157B2 Shadow protocol circuit having full and reduced pin select outputs 有权
标题翻译：阴影协议电路具有完整和降低的引脚选择输出
公开(公告)号：US08225157B2
公开(公告)日：2012-07-17
申请号：US13078621
申请日：2011-04-01
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/31713 , G01R31/2815 , G01R31/2851 , G01R31/2884 , G01R31/3025 , G01R31/31703 , G01R31/31725 , G01R31/31727 , G01R31/3177 , G01R31/318558
摘要： The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.
摘要翻译：本公开描述了用于访问基板上的设备的过程和设备。衬底可以仅包括全引脚JTAG器件（504），只有减少的引脚JTAG器件（506），或者是完全引脚和降低引脚JTAG器件的混合。使用在基板（408）和JTAG控制器（404）之间的单个接口（502）来实现访问。访问接口可以是有线接口或无线接口，并且可以用于基于JTAG的设备测试，调试，编程或其他类型的基于JTAG的操作。

24. 发明授权

US08201036B2 IC with test and shadow access ports and output circuit 有权
标题翻译： IC具有测试和影子访问端口和输出电路
公开(公告)号：US08201036B2
公开(公告)日：2012-06-12
申请号：US13183113
申请日：2011-07-14
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/318536 , G01R31/318544 , G01R31/318555
摘要： The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.
摘要翻译：本公开描述了一种用于在设备内提供影子接入端口的新颖的方法和装置。访问影子访问端口，通过重用用于操作设备中测试访问端口的TDI，TMS，TCK和TDO信号来对设备执行操作。影子访问端口的存在和操作对于测试访问端口的存在和操作是透明的。根据本公开，阴影访问端口在TCK信号的下降沿操作，而测试访问端口通常在TCK信号的上升沿操作。

25. 发明申请

US20120117434A1 PROBELESS TESTING OF PAD BUFFERS ON WAFER 有权
公开(公告)号：US20120117434A1
公开(公告)日：2012-05-10
申请号：US13352484
申请日：2012-01-18
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177 , G01R31/31715 , G01R31/318505 , G01R31/318511 , G01R31/318533 , G01R31/318558 , G01R31/318572 , G01R31/318594 , G11C29/006 , G11C29/022 , G11C29/48 , G11C2029/3202
摘要： The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.

26. 发明授权

US08095839B2 Position independent testing of circuits 有权
标题翻译：电路位置独立测试
公开(公告)号：US08095839B2
公开(公告)日：2012-01-10
申请号：US13100726
申请日：2011-05-04
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/318536 , G01R31/318558 , G01R31/318572
摘要： Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.
摘要翻译：扫描分配器，收集器和控制器电路连接到集成电路上的核心电路的功能输入和输出，以通过这些功能输入和输出提供测试。多路复用器和解复用器电路在扫描电路和功能输入和输出之间进行选择。核心电路还可以提供内置的扫描分配器，收集器和控制器电路，以避免将其添加到核心电路的外部。通过适当放置的内置扫描分配器和集电极电路，将核心电路的功能输入和输出连接在一起，将每个核心中的扫描分配器和集电极电路连接在一起。这可以提供扫描电路的层次结构，并减少对单独的测试互连和多路复用器的需求。

27. 发明申请

US20110320897A1 CORE CIRCUIT TEST ARCHITECTURE 有权
标题翻译：核心电路测试架构
公开(公告)号：US20110320897A1
公开(公告)日：2011-12-29
申请号：US13230367
申请日：2011-09-12
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G06F11/267
CPC分类号： G01R31/31723 , G01R31/2851 , G01R31/3172 , G01R31/31724 , G01R31/3173 , G01R31/3177 , G01R31/318563 , G01R31/318575
摘要： A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each scan path passes through a multiplexer to compare circuits on the semiconductor substrate. The compare circuits also receive expected data and mask data. The compare circuits provide a fail flag output from the semiconductor substrate.
摘要翻译：扫描测试架构通过将串行扫描路径选择性地分成较短的部分来促进半导体电路的低功率测试。部分之间的多路复用器控制将部分连接到更长或短路的路径。选择并启用信号控制扫描路径部分的操作。每个扫描路径的输出通过多路复用器来比较半导体衬底上的电路。比较电路还接收预期数据和掩模数据。比较电路提供从半导体衬底输出的故障标志。

28. 发明申请

US20110314348A1 SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS 有权
标题翻译：使用嵌入式命令扫描框架进行扫描测试
公开(公告)号：US20110314348A1
公开(公告)日：2011-12-22
申请号：US13217851
申请日：2011-08-25
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177 , G01R31/3172 , G01R31/31723 , G01R31/31725 , G01R31/31727 , G01R31/318536 , G01R31/318572 , G01R31/318577
摘要： Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.
摘要翻译：集成电路的测试是通过利用扫描帧输入移位寄存器，扫描帧输出移位寄存器，测试控制器和包括扫描输入，扫描时钟，测试使能和扫描输出的测试接口的测试架构实现的。输入到扫描帧输入移位寄存器的扫描帧包含测试激励数据部分和测试命令部分。从扫描帧输出移位寄存器输出的扫描帧包含测试响应数据部分和可选地用于输出其他数据的部分。输入扫描帧的命令部分控制测试架构以执行所需的测试操作。

29. 发明申请

US20110283154A1 ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION 有权
标题翻译：适应低功耗操作的扫描架构
公开(公告)号：US20110283154A1
公开(公告)日：2011-11-17
申请号：US13184077
申请日：2011-07-15
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31721 , G01R31/31723 , G01R31/31724 , G01R31/3177 , G01R31/318536 , G01R31/318575
摘要： A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.
摘要翻译： Scan-BIST架构适用于低功耗Scan-BIST架构。发电机102，压实机106和控制器110保持与已知技术相同。已知的Scan-BIST架构和低功率Scan-BIST架构之间的变化包括将已知扫描路径修改为扫描路径502，以插入扫描路径A 506，B 508和C 510，以及插入适配器电路 504在控制器110和扫描路径502之间的控制路径114中。

30. 发明申请

US20110273204A1 PARALLEL SCAN DISTRIBUTORS AND COLLECTORS AND PROCESS OF TESTING INTEGRATED CIRCUITS 有权
标题翻译：并行扫描分配器和收集器以及测试集成电路的过程
公开(公告)号：US20110273204A1
公开(公告)日：2011-11-10
申请号：US13185895
申请日：2011-07-19
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： H03K19/00
CPC分类号： G01R31/2851 , G01R31/31715 , G01R31/3177 , G01R31/318536 , G01R31/318555 , G01R31/318563 , G01R31/31919
摘要： An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together. The scan distributor and collector circuits can be formed in core circuits (704). The core circuits then can be connected to other core circuits and functional circuits with simple connections to the parallel scan circuits through the scan distributor and collector circuits.
摘要翻译：具有并行扫描路径（824-842,924-942）的集成电路（70）包括一对或一对扫描分配器（800,900）和扫描收集器（844,944）电路。扫描路径将激励测试数据应用于集成电路上的功能电路（702），并从功能电路接收响应测试数据。扫描分配器电路（800）从外围接合焊盘（802）接收串行测试数据，并将其分配到每个并行扫描路径。扫描收集器电路（844）从并行扫描路径收集测试数据并将其应用于外围接合焊盘（866）。这使得更长的并行扫描路径能够连接到功能电路。扫描分配器和集电极电路可以分别串联连接以提供并行连接到更平行的扫描路径。另外，多路复用器电路（886,890）可以将扫描分配器和集电极电路对选择性地连接在一起。扫描分配器和集电极电路可以形成在核心电路（704）中。然后，核心电路可以通过扫描分配器和集电极电路与并行扫描电路的简单连接连接到其他核心电路和功能电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式