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21. 发明申请

US20130313121A1 Method of Forming Interconnects for Three Dimensional Integrated Circuit 有权
标题翻译：形成三维集成电路互连的方法
公开(公告)号：US20130313121A1
公开(公告)日：2013-11-28
申请号：US13481517
申请日：2012-05-25
申请人： Chun Hui Yu , Kuo-Chung Yee , Chen-Hua Yu , Yeong-Jyh Lin , Chia-Hsiang Lin , Liang-Ju Yen , Lawrence Chiang Sheu
发明人： Chun Hui Yu , Kuo-Chung Yee , Chen-Hua Yu , Yeong-Jyh Lin , Chia-Hsiang Lin , Liang-Ju Yen , Lawrence Chiang Sheu
IPC分类号： C25D5/02 , C25D7/12 , C25D7/00
CPC分类号： H01L21/486 , H01L23/49816 , H01L23/49827 , H01L2224/13099 , H01L2224/16238 , H01L2924/15311 , H01L2924/00014
摘要： A method of forming interconnects for three dimensional integrated circuits comprises attaching a metal layer on a first carrier, attaching a first side of a packaging component on the metal layer, wherein the packaging component comprises a plurality of through vias. The method further comprises filling the plurality of through vias with a metal material using an electrochemical plating process, wherein the metal layer functions as an electrode for the electrochemical plating process, attaching a second carrier on a second side of the packaging component, detaching the first carrier from the packaging component, forming a photoresist layer on the metal layer, patterning the photoresist layer and detaching exposed portions of the metal layer.
摘要翻译：形成用于三维集成电路的互连的方法包括将金属层附接在第一载体上，将包装部件的第一侧附着在金属层上，其中该封装部件包括多个通孔。该方法还包括使用电化学电镀工艺用金属材料填充多个通孔，其中金属层用作用于电化学电镀工艺的电极，将第二载体附着在包装部件的第二侧上，将第一载体，在金属层上形成光致抗蚀剂层，图案化光致抗蚀剂层并分离金属层的暴露部分。

22. 发明申请

US20110159639A1 Method for Making a Stackable Package 有权
标题翻译：制作可堆叠封装的方法
公开(公告)号：US20110159639A1
公开(公告)日：2011-06-30
申请号：US12856401
申请日：2010-08-13
申请人： Kuo-Chung Yee , Meng-Jen Wang
发明人： Kuo-Chung Yee , Meng-Jen Wang
IPC分类号： H01L21/50
CPC分类号： H01L23/49816 , H01L21/568 , H01L21/6835 , H01L21/76898 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2221/68327 , H01L2221/68381 , H01L2224/0401 , H01L2224/04105 , H01L2224/06181 , H01L2224/12105 , H01L2224/131 , H01L2224/16225 , H01L2224/221 , H01L2224/2518 , H01L2225/06548 , H01L2225/1035 , H01L2225/1041 , H01L2225/1052 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01075 , H01L2924/014 , H01L2924/181 , H01L2924/00015 , H01L2924/00
摘要： The present invention relates to a method for making a stackable package. The method includes the following steps: (a) providing a first carrier; (b) disposing at least one chip on the first carrier; (c) forming a molding compound so as to encapsulate the chip; (d) removing the first carrier; (e) forming a first redistribution layer and at least one first bump; (f) providing a second carrier; (g) disposing on the second carrier; (h) removing part of the chip and part of the molding compound; (i) forming a second redistribution layer; and (j) removing the second carrier. Therefore, to the second redistribution layer enables the stackable package to have more flexibility to be utilized.
摘要翻译：本发明涉及一种制造可堆叠包装的方法。该方法包括以下步骤：（a）提供第一载体; （b）在所述第一载体上设置至少一个芯片; （c）形成模塑料以封装芯片; （d）移除第一载体; （e）形成第一再分布层和至少一个第一凸起; （f）提供第二载体; （g）设置在第二载体上; （h）去除芯片的一部分和模塑料的一部分; （i）形成第二重分布层; 和（j）移除第二载体。因此，对于第二再分配层，可堆叠的包装具有更多的灵活性被利用。

23. 发明授权

US07456051B2 Photoelectric device grinding process and device grinding process 有权
标题翻译：光电器件研磨过程和器件研磨过程
公开(公告)号：US07456051B2
公开(公告)日：2008-11-25
申请号：US10710696
申请日：2004-07-29
申请人： Kuo-Chung Yee , Chih-Lung Chen
发明人： Kuo-Chung Yee , Chih-Lung Chen
IPC分类号： H01L21/30
CPC分类号： H01L21/6836 , B81C1/00896 , H01L2221/68327
摘要： A photoelectric device grinding process comprising the following steps is disclosed. A wafer comprising a plurality of chip units is provided. Each chip unit has at least a photoelectric device disposed on a surface layer. A dielectric substrate is attached to the wafer with glue having a plurality of spacers therein such that the photoelectric devices face the dielectric layer. The spacers maintain a gap between the dielectric substrate and the wafer. Thereafter, the dielectric substrate surface away from the wafer or the wafer surface away from the dielectric substrate or both is ground. The grinding process is particularly suitable for preventing any possible damage to the photoelectric devices on a wafer.
摘要翻译：公开了包括以下步骤的光电装置研磨过程。提供了包括多个芯片单元的晶片。每个芯片单元至少具有设置在表面层上的光电装置。电介质基板用胶水附着在晶片上，其中多个间隔物在其中，使得光电器件面向电介质层。间隔物在电介质基片和晶片之间保持间隙。此后，离开晶片或离开电介质基片或两者的晶片表面的电介质基片表面被研磨。研磨过程特别适用于防止对晶片上的光电装置的任何可能的损坏。

24. 发明申请

US20050164426A1 MICRO-MIRROR PACKAGE 有权
标题翻译： MICRO-MIRROR包装
公开(公告)号：US20050164426A1
公开(公告)日：2005-07-28
申请号：US10905400
申请日：2004-12-31
申请人： Kuo-Chung Yee
发明人： Kuo-Chung Yee
IPC分类号： B81B3/00 , G02B26/08 , H01L21/00 , H01L21/70
CPC分类号： G02B26/0816 , H01L2224/48091 , H01L2224/73265 , H01L2924/01019 , H01L2924/00014
摘要： A micro-mirror package comprising a substrate, a bottom substrate, a cover substrate, a semiconductor chip, a first adhesive, a second adhesive, a plurality of wires and a lid is provided. The substrate has a circular wall. The bottom substrate is disposed on the substrate within the circular wall. The first adhesive is provided with first spacers for attaching the cover substrate to the semiconductor chip and setting the cover substrate and the semiconductor chip apart. The second adhesive is provided with second spacers for attaching the semiconductor chip to the bottom substrate and setting the semiconductor chip and the bottom substrate apart. The wires are used for electrically connecting the semiconductor chip and the substrate. The lid is disposed on top of the circular wall.
摘要翻译：提供了包括基板，底部基板，盖基板，半导体芯片，第一粘合剂，第二粘合剂，多根电线和盖子的微反射镜封装。基板具有圆形壁。底部基板设置在圆形壁内的基板上。第一粘合剂设置有用于将盖基板附接到半导体芯片并将盖基板和半导体芯片分开的第一间隔件。第二粘合剂设置有用于将半导体芯片附接到底部基板并将半导体芯片和底部基板分开的第二间隔件。电线用于电连接半导体芯片和基板。盖子设置在圆形壁的顶部。

25. 发明申请

US20050139848A1 Image sensor package and method for manufacturing the same 审中-公开
标题翻译：图像传感器封装及其制造方法
公开(公告)号：US20050139848A1
公开(公告)日：2005-06-30
申请号：US11028150
申请日：2004-12-30
申请人： Kuo-Chung Yee
发明人： Kuo-Chung Yee
IPC分类号： H01L27/14 , H01L31/0203 , H01L31/0232 , H04N5/335 , H04N5/372 , H04N5/374
CPC分类号： H01L31/0203 , H01L27/14618 , H01L27/14625 , H01L27/14687 , H01L31/02325 , H01L2224/32013 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/00014
摘要： An image sensor package includes a substrate, a chip, a transparent cover, and a lens module. The substrate has an upper surface and a lower surface, and has a plurality of connection pads disposed on the lower surface and a though opening. The chip has an active surface, and has an image sensor disposed on the active surface, corresponding to the through opening of the substrate. Also and, a plurality of bumps are disposed at peripheral region of the active surface and are electrically connected to the pads. The transparent cover is disposed in the through opening of the substrate and covers the image sensor. The lens module is disposed on the upper surface for transmitting light to the image sensor.
摘要翻译：图像传感器封装包括基板，芯片，透明盖和透镜模块。基板具有上表面和下表面，并且具有设置在下表面上的多个连接焊盘和通孔。芯片具有活性表面，并且具有对应于基板的通孔设置在活性表面上的图像传感器。此外，多个凸块设置在有源表面的周边区域并且电连接到焊盘。透明盖设置在基板的贯通孔中并覆盖图像传感器。透镜模块设置在上表面上，用于将光传输到图像传感器。

26. 发明授权

US06693364B2 Optical integrated circuit element package and process for making the same 有权
标题翻译：光集成电路元件封装及其制造方法
公开(公告)号：US06693364B2
公开(公告)日：2004-02-17
申请号：US10355152
申请日：2003-01-31
申请人： Su Tao , Kuo Chung Yee , Jen Chieh Kao , Chih Lung Chen , Hsing Jung Liau
发明人： Su Tao , Kuo Chung Yee , Jen Chieh Kao , Chih Lung Chen , Hsing Jung Liau
IPC分类号： H01L2348
CPC分类号： H01L31/0203 , H01L21/563 , H01L23/49816 , H01L25/0657 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2224/73203 , H01L2224/73253 , H01L2924/00014 , H01L2924/01079 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2224/05599
摘要： An optical integrated circuit element package comprises a substrate, an upper chip, a lower chip, an optical-transparent underfill, and a sealing compound. The substrate has a plurality of solder balls disposed on a surface of the substrate, a plurality of bonding pads electrically connected to the solder balls, a cover attached to the other surface of the substrate, and a cavity to expose the cover. The upper chip is provided with a plurality of bumps and is adhered to the exposed cover in the cavity by a thermal gap fill. The lower chip has a plurality of bonding pads electrically connected to the plurality of bumps of the upper chip and has a plurality of bumps electrically connected to the plurality of bonding pads of the substrate. The optical-transparent underfill is disposed between the lower chip and the upper chip. The sealing compound hermetically seals the space between the lower chip and the substrate.
摘要翻译：一种光学集成电路元件封装，包括衬底，上部芯片，下部芯片，光学透明底部填充物和密封化合物。衬底具有设置在衬底的表面上的多个焊球，与焊球电连接的多个接合焊盘，附接到衬底的另一个表面的盖以及露出罩的空腔。上芯片设置有多个凸块，并且通过热间隙填充而粘附到空腔中的暴露盖。下部芯片具有电连接到上部芯片的多个凸起的多个焊盘，并且具有电连接到该衬底的多个焊盘的多个凸块。光学透明底部填充物设置在下部芯片和上部芯片之间。密封组合物密封下部芯片和基板之间的空间。

27. 发明授权

US08003426B2 Method for manufacturing package structure of optical device 有权
标题翻译：制造光器件封装结构的方法
公开(公告)号：US08003426B2
公开(公告)日：2011-08-23
申请号：US12471455
申请日：2009-05-25
申请人： Kuo-Chung Yee
发明人： Kuo-Chung Yee
IPC分类号： H01L21/00
CPC分类号： H01L27/14618 , H01L24/97 , H01L2224/05553 , H01L2224/48091 , H01L2224/49175 , H01L2224/73265 , H01L2924/14 , H01L2924/15787 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A package structure of optical devices has a chip, a sealant, a cover, a substrate, a plurality of bonding wires, and a transparent encapsulant. The chip has at least an optical device and a plurality of chip connection pads. The sealant is disposed around the optical elements. The cover is disposed on the sealant. The substrate supports the chip and has a plurality of connection pads. The bonding wires are used for electrically connecting the chip connection pads of the chip to the connection pads of the substrate. The transparent encapsulant is formed over the substrate and the cover, and encapsulates the bonding wires.
摘要翻译：光学器件的封装结构具有芯片，密封剂，盖子，衬底，多个接合线和透明密封剂。芯片至少具有光学器件和多个芯片连接焊盘。密封剂设置在光学元件周围。盖子设置在密封剂上。衬底支撑芯片并且具有多个连接焊盘。接合线用于将芯片的芯片连接焊盘电连接到衬底的连接焊盘。透明密封剂形成在衬底和盖上，并封装接合线。

28. 发明申请

US20090239329A1 METHOD FOR MANUFACTURING PACKAGE STRUCTURE OF OPTICAL DEVICE 有权
标题翻译：制造光器件封装结构的方法
公开(公告)号：US20090239329A1
公开(公告)日：2009-09-24
申请号：US12471455
申请日：2009-05-25
申请人： Kuo-Chung Yee
发明人： Kuo-Chung Yee
IPC分类号： H01L21/50
CPC分类号： H01L27/14618 , H01L24/97 , H01L2224/05553 , H01L2224/48091 , H01L2224/49175 , H01L2224/73265 , H01L2924/14 , H01L2924/15787 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A package structure of optical devices has a chip, a sealant, a cover, a substrate, a plurality of bonding wires, and a transparent encapsulant. The chip has at least an optical device and a plurality of chip connection pads. The sealant is disposed around the optical elements. The cover is disposed on the sealant. The substrate supports the chip and has a plurality of connection pads. The bonding wires are used for electrically connecting the chip connection pads of the chip to the connection pads of the substrate. The transparent encapsulant is formed over the substrate and the cover, and encapsulates the bonding wires.
摘要翻译：光学器件的封装结构具有芯片，密封剂，盖子，衬底，多个接合线和透明密封剂。芯片至少具有光学器件和多个芯片连接焊盘。密封剂设置在光学元件周围。盖子设置在密封剂上。衬底支撑芯片并且具有多个连接焊盘。接合线用于将芯片的芯片连接焊盘电连接到衬底的连接焊盘。透明密封剂形成在衬底和盖上，并封装接合线。

29. 发明授权

US07446404B2 Three-dimensional package and method of making the same 有权
标题翻译：三维包装及其制作方法
公开(公告)号：US07446404B2
公开(公告)日：2008-11-04
申请号：US11645177
申请日：2006-12-26
申请人： Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
发明人： Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
IPC分类号： H01L23/02 , H01L23/053 , H01L23/12 , H01L23/34 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L25/0657 , H01L21/76898 , H01L25/50 , H01L2224/48145 , H01L2225/06506 , H01L2225/06524 , H01L2225/06541 , H01L2924/01019 , H01L2924/01078 , H01L2924/00012
摘要： A three-dimensional package including a first wafer having at least one first pad and a first protection layer exposing the first pad. A first hole penetrates the first wafer. A first isolation layer is disposed on the side wall of the first hole. The lower end of a first conductive layer extends below the surface of the first wafer. A first metal is disposed in the first hole, and is electrically connected to the first pad via the first conductive layer. A first solder is disposed on the first metal in the first hole, wherein the melting point of the first solder is lower than that of the first metal. A second wafer is configured similarly as the first wafer. A lower end of a second conductive layer of the second wafer extends below the surface of the second wafer and contacts the upper end of the first solder.
摘要翻译：一种三维封装，其包括具有至少一个第一焊盘的第一晶片和暴露第一焊盘的第一保护层。第一孔穿透第一晶片。第一隔离层设置在第一孔的侧壁上。第一导电层的下端在第一晶片的表面下方延伸。第一金属设置在第一孔中，并经由第一导电层与第一焊盘电连接。第一焊料设置在第一孔中的第一金属上，其中第一焊料的熔点低于第一焊料的熔点。第二晶片被配置为类似于第一晶片。第二晶片的第二导电层的下端在第二晶片的表面下方延伸并接触第一焊料的上端。

30. 发明授权

US07352071B2 Method of fabricating anti-warp package 有权
标题翻译：制造抗翘曲包装的方法
公开(公告)号：US07352071B2
公开(公告)日：2008-04-01
申请号：US10904760
申请日：2004-11-26
申请人： Kuo-Chung Yee
发明人： Kuo-Chung Yee
IPC分类号： H01L23/29
CPC分类号： H01L21/565 , H01L23/16 , H01L23/3121 , H01L2924/0002 , H01L2924/00
摘要： An anti-warp package comprising a packaging substrate, a chip and a stiffening member is provided. The chip is disposed on a top surface of the packaging substrate. The stiffening member is disposed on a bottom surface of the packaging substrate in a location underneath the surrounding area of the chip. Through the disposition of a stiffening member, warping stress on the packaging substrate when the chip is encapsulated by molding compound is counterbalanced.
摘要翻译：提供了一种包括封装基板，芯片和加强部件的抗翘曲包装。芯片设置在封装基板的顶表面上。加强构件在芯片的周围区域下方的位置设置在封装基板的底面上。通过加强构件的设置，当通过模塑料封装芯片时，封装衬底上的翘曲应力是平衡的。

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