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21. 发明申请

US20130168822A1 SELF ALIGNED STRUCTURES AND DESIGN STRUCTURE THEREOF 失效
标题翻译：自对准结构及其设计结构
公开(公告)号：US20130168822A1
公开(公告)日：2013-07-04
申请号：US13343287
申请日：2012-01-04
申请人： William F. CLARK, JR. , John J. PEKARIK , Yun SHI , Yanli ZHANG
发明人： William F. CLARK, JR. , John J. PEKARIK , Yun SHI , Yanli ZHANG
IPC分类号： H01L29/732 , G06F17/50 , H01L21/331
CPC分类号： H01L29/66272 , H01L21/8249 , H01L21/84 , H01L27/1203 , H01L29/732
摘要： Vertical bipolar junction structures, methods of manufacture and design structures. The method includes forming one or more sacrificial structures for a bipolar junction transistor (BJT) in a first region of a chip. The method includes forming a mask over the one or more sacrificial structures. The method further includes etching an opening in the mask, aligned with the one or more sacrificial structures. The method includes forming a trench through the opening and extending into diffusion regions below the one or more sacrificial structures. The method includes forming a base region of the BJT by depositing an epitaxial material in the trench, in contact with the diffusion regions. The method includes forming an emitter contact by depositing a second epitaxial material on the base region within the trench. The epitaxial material for the emitter region is of an opposite dopant type than the epitaxial material of the base region.
摘要翻译：垂直双极结结构，制造方法和设计结构。该方法包括在芯片的第一区域中形成用于双极结型晶体管（BJT）的一个或多个牺牲结构。该方法包括在一个或多个牺牲结构上形成掩模。该方法还包括蚀刻掩模中与该一个或多个牺牲结构对准的开口。该方法包括通过该开口形成沟槽并延伸到一个或多个牺牲结构下方的扩散区域中。该方法包括通过在沟槽中沉积与扩散区接触的外延材料来形成BJT的基极区域。该方法包括通过在沟槽内的基极区域上沉积第二外延材料来形成发射极接触。用于发射极区域的外延材料具有与基极区域的外延材料相反的掺杂剂类型。

22. 发明授权

US07666720B2 Method and apparatus for improving integrated circuit device performance using hybrid crystal orientations 失效
标题翻译：使用混合晶体取向提高集成电路器件性能的方法和装置
公开(公告)号：US07666720B2
公开(公告)日：2010-02-23
申请号：US12100615
申请日：2008-04-10
申请人： John J. Pekarik , Xudong Wang
发明人： John J. Pekarik , Xudong Wang
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L29/045
摘要： A method of forming a current mirror device for an integrated circuit includes configuring a reference current source; forming a first field effect transistor (FET) in series with the reference current source, the first FET of a first conductivity type formed on a first portion of a substrate having a first crystal lattice orientation; and forming a second FET of the first conductivity type on a second portion of the substrate having a second crystal lattice orientation, with a gate terminal of the first FET coupled to a gate terminal of the second FET, and the gate terminals of the first and second FETs coupled to the reference current source; wherein the carrier mobility of the first FET formed on the first portion of the substrate is different than the carrier mobility of the second FET formed on the second portion of the substrate.
摘要翻译：形成用于集成电路的电流镜装置的方法包括：配置参考电流源; 形成与参考电流源串联的第一场效应晶体管（FET），形成在具有第一晶格取向的衬底的第一部分上的第一导电类型的第一FET; 以及在具有第二晶格取向的衬底的第二部分上形成具有第一导电类型的第二FET，其中第一FET的栅极端耦合到第二FET的栅极端子，以及第一FET的栅极端子耦合到参考电流源的第二FET; 其中形成在衬底的第一部分上的第一FET的载流子迁移率不同于形成在衬底的第二部分上的第二FET的载流子迁移率。

23. 发明授权

US07517806B2 Integrated circuit having pairs of parallel complementary FinFETs 失效
标题翻译：具有成对的并联互补FinFET的集成电路
公开(公告)号：US07517806B2
公开(公告)日：2009-04-14
申请号：US11186748
申请日：2005-07-21
申请人： Andres Bryant , William F. Clark, Jr. , David M. Fried , Mark D. Jaffe , Edward J. Nowak , John J. Pekarik , Christopher S. Putnam
发明人： Andres Bryant , William F. Clark, Jr. , David M. Fried , Mark D. Jaffe , Edward J. Nowak , John J. Pekarik , Christopher S. Putnam
IPC分类号： H01L21/302
CPC分类号： H01L21/84 , H01L21/3086 , H01L21/3088 , H01L21/823821 , H01L27/1203 , H01L29/66795 , H01L29/785 , Y10S438/947
摘要： A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin and the second fin have approximately the same width.
摘要翻译：公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。本发明具有包括第一鳍片的第一类型的FinFET和包括与第一鳍片平行的第二鳍片的第二类型的FinFET。本发明还具有位于第一第一类型FinFET的源极/漏极区域和第二类型FinFET之间的绝缘体鳍片。绝缘体鳍片具有与第一鳍片和第二鳍片大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍片的宽度。本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极。栅极包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。第一鳍片和第二鳍片具有大致相同的宽度。

24. 发明授权

US06795468B2 Electric pumping of rare-earth-doped silicon for optical emission 失效
标题翻译：用于光发射的稀土掺杂硅的电泵浦
公开(公告)号：US06795468B2
公开(公告)日：2004-09-21
申请号：US10461919
申请日：2003-06-16
申请人： John J. Pekarik , Walter J. Varhue
发明人： John J. Pekarik , Walter J. Varhue
IPC分类号： H01S500
CPC分类号： H01L33/343 , H01L33/0016 , H01S3/0959 , H01S3/1603 , H01S3/1608 , H01S3/1611 , H01S3/1613 , H01S3/1628
摘要： A structure having a p-n junction in a semiconductor having a first p-type region and a first n-type region along with a region located in the vicinity of the p-n junction that is doped with a rare-earth element. In addition, the structure includes a charge source coupled to one of the p-type region and n-type region for providing charge carriers to excite atoms of the rare-earth element. Also provided is a method for producing the structure that includes providing a bipolar junction transistor; doping a region in a collector of the transistor with a rare-earth element; and biasing the transistor to generate light emission from the rare-earth element doped region.
摘要翻译：在具有第一p型区域和第一n型区域的半导体中具有p-n结的结构以及位于被掺杂有稀土元素的p-n结附近的区域。此外，该结构包括耦合到p型区域和n型区域中的一个的电荷源，用于提供电荷载流子以激发稀土元素的原子。还提供了一种用于制造包括提供双极结型晶体管的结构的方法; 用稀土元素掺杂在晶体管的集电极中的区域; 并且偏置晶体管以产生来自稀土元素掺杂区域的发光。

25. 发明授权

US06038168A Hot-electron programmable latch for integrated circuit fuse applications and method of programming therefor 失效
标题翻译：用于集成电路保险丝应用的热电子可编程锁存器及其编程方法
公开(公告)号：US06038168A
公开(公告)日：2000-03-14
申请号：US105339
申请日：1998-06-26
申请人： Archibald J. Allen , Jerome B. Lasky , John J. Pekarik , Jed H. Rankin , Francis R. White
发明人： Archibald J. Allen , Jerome B. Lasky , John J. Pekarik , Jed H. Rankin , Francis R. White
IPC分类号： G11C17/16 , G11C17/18 , G11C7/00
CPC分类号： G11C17/18 , G11C17/16
摘要： A method and apparatus for conditioning an integrated circuit to always enter a desired operating state when actuated by permanently altering at least one component device. An integrated circuit is provided with at least one component transistor wherein a constant high voltage is applied only once to the drain electrode of the transistor for one predetermined period of time while concurrently a constant voltage lower than the high voltage is applied only once to the gate electrode of the transistor, thus causing a permanent channel hot-electron alteration of a gate oxide of the transistor. The integrated circuit may include a plurality of programmable circuits, each capable of assuming a plurality of readable data states when powered up, and each including a plurality of programmable devices for permanently biasing its corresponding programmable circuit to assume one of the readable states upon subsequent power ups.
摘要翻译：一种用于调节集成电路以在通过永久地改变至少一个组件装置致动时始终进入期望操作状态的方法和装置。集成电路设置有至少一个元件晶体管，其中恒定的高电压仅施加一次到晶体管的漏极一个预定时间段，同时将低于高电压的恒定电压仅施加一次到栅极电极，从而导致晶体管的栅极氧化物的永久性通道热电子改变。集成电路可以包括多个可编程电路，每个可编程电路能够在通电时呈现多个可读数据状态，并且每个可编程电路包括多个可编程器件，用于永久地偏置其相应的可编程电路，以在后续电源中呈现可读状态之一 UPS。

26. 发明授权

US08552532B2 Self aligned structures and design structure thereof 失效
标题翻译：自对准结构及其设计结构
公开(公告)号：US08552532B2
公开(公告)日：2013-10-08
申请号：US13343287
申请日：2012-01-04
申请人： William F. Clark, Jr. , John J. Pekarik , Yun Shi , Yanli Zhang
发明人： William F. Clark, Jr. , John J. Pekarik , Yun Shi , Yanli Zhang
IPC分类号： H01L29/1004
CPC分类号： H01L29/66272 , H01L21/8249 , H01L21/84 , H01L27/1203 , H01L29/732
摘要： Vertical bipolar junction structures, methods of manufacture and design structures. The method includes forming one or more sacrificial structures for a bipolar junction transistor (BJT) in a first region of a chip. The method includes forming a mask over the one or more sacrificial structures. The method further includes etching an opening in the mask, aligned with the one or more sacrificial structures. The method includes forming a trench through the opening and extending into diffusion regions below the one or more sacrificial structures. The method includes forming a base region of the BJT by depositing an epitaxial material in the trench, in contact with the diffusion regions. The method includes forming an emitter contact by depositing a second epitaxial material on the base region within the trench. The epitaxial material for the emitter region is of an opposite dopant type than the epitaxial material of the base region.
摘要翻译：垂直双极结结构，制造方法和设计结构。该方法包括在芯片的第一区域中形成用于双极结型晶体管（BJT）的一个或多个牺牲结构。该方法包括在一个或多个牺牲结构上形成掩模。该方法还包括蚀刻掩模中与该一个或多个牺牲结构对准的开口。该方法包括通过该开口形成沟槽并延伸到一个或多个牺牲结构下方的扩散区域中。该方法包括通过在沟槽中沉积与扩散区接触的外延材料来形成BJT的基极区域。该方法包括通过在沟槽内的基极区域上沉积第二外延材料来形成发射极接触。用于发射极区域的外延材料具有与基极区域的外延材料相反的掺杂剂类型。

27. 发明申请

US20130134483A1 BIPOLAR TRANSISTOR WITH A RAISED COLLECTOR PEDASTAL FOR REDUCED CAPACITANCE AND A METHOD OF FORMING THE TRANSISTOR 有权
标题翻译：具有用于降低电容的集电器底座的双极晶体管和形成晶体管的方法
公开(公告)号：US20130134483A1
公开(公告)日：2013-05-30
申请号：US13307412
申请日：2011-11-30
申请人： James W. Adkisson , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
发明人： James W. Adkisson , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
IPC分类号： H01L29/737 , H01L21/331 , H01L29/73
CPC分类号： H01L29/66234 , H01L29/0826 , H01L29/66287 , H01L29/732 , H01L29/7371
摘要： Disclosed are a transistor and a method of forming the transistor with a raised collector pedestal in reduced dimension for reduced base-collector junction capacitance. The raised collector pedestal is on the top surface of a substrate, extends vertically through dielectric layer(s), is un-doped or low-doped, is aligned above a sub-collector region contained within the substrate and is narrower than that sub-collector region. An intrinsic base layer is above the raised collector pedestal and the dielectric layer(s). An extrinsic base layer is above the intrinsic base layer. Thus, the space between the extrinsic base layer and the sub-collector region is increased. This increased space is filled by dielectric material and the electrical connection between the intrinsic base layer and the sub-collector region is provided by the relatively narrow, un-doped or low-doped, raised collector pedestal. Consequently, base-collector junction capacitance is reduced and, consequently, the maximum oscillation frequency is increased.
摘要翻译：公开了晶体管和以缩小的尺寸形成具有凸起的集电极基座的晶体管的方法，以减小基极 - 集电极结电容。凸起的收集器基座位于基板的顶表面上，垂直延伸穿过绝缘层（未掺杂或低掺杂）在衬底内的子集电极区域上方排列，收集区域。本征基层在凸起的收集器基座和介电层之上。外在基层在本征基层之上。因此，外部基极层和副集电极区域之间的空间增加。该增加的空间由电介质材料填充，并且本征基极层和次集电极区域之间的电连接由相对窄的未掺杂或低掺杂的升高的集电极基座提供。因此，集电极结电容减小，因此最大振荡频率增加。

28. 发明申请

US20130119508A1 BIPOLAR JUNCTION TRANSISTOR WITH MULTIPLE EMITTER FINGERS 有权
标题翻译：具有多个发光指示器的双极接头晶体管
公开(公告)号：US20130119508A1
公开(公告)日：2013-05-16
申请号：US13294671
申请日：2011-11-11
申请人： Renata Camillo-Castillo , David L. Harame , Qizhi Liu , Ramana M. Malladi , John J. Pekarik
发明人： Renata Camillo-Castillo , David L. Harame , Qizhi Liu , Ramana M. Malladi , John J. Pekarik
IPC分类号： H01L29/73 , G06F17/50 , H01L21/331
CPC分类号： H01L29/66303 , G06F17/5045 , H01L29/0649 , H01L29/0804 , H01L29/0808 , H01L29/0821 , H01L29/1008 , H01L29/66234 , H01L29/7322 , H01L29/735
摘要： Methods for fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. The bipolar junction transistor may include a plurality of emitters that are arranged in distinct emitter fingers. A silicide layer is formed that covers an extrinsic base layer of the bipolar junction transistor and that fills the gaps between adjacent emitters. Non-conductive spacers on the emitter sidewalls electrically insulate the emitters from the silicide layer. The emitters extend through the extrinsic base layer and the silicide layer to contact the intrinsic base layer. The emitters may be formed using sacrificial emitter pedestals in a replacement-type process.
摘要翻译：用于制造双极结型晶体管的方法，双极结型晶体管以及用于双极结型晶体管的设计结构。双极结晶体管可以包括布置在不同的发射极指中的多个发射极。形成了覆盖双极结型晶体管的非本征基极层并填充相邻发射极之间的间隙的硅化物层。发射极侧壁上的非导电间隔物使发射体与硅化物层电绝缘。发射极延伸通过外部基极层和硅化物层与本征基极层接触。发射器可以在替代型工艺中使用牺牲发射器基座形成。

29. 发明申请

US20130119442A1 JUNCTION FIELD-EFFECT TRANSISTOR WITH RAISED SOURCE AND DRAIN REGIONS FORMED BY SELECTIVE EPITAXY 有权
标题翻译：具有选择性外延形成的上升源和漏区的连接场效应晶体管
公开(公告)号：US20130119442A1
公开(公告)日：2013-05-16
申请号：US13294731
申请日：2011-11-11
申请人： Kevin K. Chan , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
发明人： Kevin K. Chan , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
IPC分类号： H01L21/337 , G06F17/50 , H01L29/808
CPC分类号： H01L29/8086 , G06F17/5045 , H01L27/0623 , H01L29/0817 , H01L29/0826 , H01L29/1004 , H01L29/1058 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/66242 , H01L29/66893 , H01L29/66901 , H01L29/732 , H01L29/7375 , H01L29/808
摘要： Junction field-effect transistors, methods for fabricating junction field-effect transistors, and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A gate is formed that is aligned with a channel laterally disposed in the semiconductor layer between the source and the drain. The source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from a first semiconductor material comprising the gate.
摘要翻译：结型场效应晶体管，用于制造结型场效应晶体管的方法，以及结型场效应晶体管的设计结构。结场效应晶体管的源极和漏极由通过选择性外延生长并与半导体层的顶表面直接接触的半导体材料组成。形成与在源极和漏极之间横向设置在半导体层中的沟道对准的栅极。源极，漏极和半导体层各自包括与包括栅极的第一半导体材料具有相反导电类型的第二半导体材料。

30. 发明授权

US07670889B2 Structure and method for fabrication JFET in CMOS 失效
标题翻译： CMOS中制造JFET的结构和方法
公开(公告)号：US07670889B2
公开(公告)日：2010-03-02
申请号：US12132638
申请日：2008-06-04
申请人： John J. Pekarik , Richard A. Phelps , Robert M. Rassel , Yun Shi
发明人： John J. Pekarik , Richard A. Phelps , Robert M. Rassel , Yun Shi
IPC分类号： H01L21/337 , H01L21/84
CPC分类号： H01L29/8086 , H01L29/66901
摘要： A design structure, and more particularly, to a design structure for manufacturing a JFET in SOI, a JFET and methods of manufacturing the JFET are provided. The JFET includes a gate poly formed directly on an SOI layer and a gate oxide layer interposed between outer edges of the gate poly and the SOI layer.
摘要翻译：更具体地，涉及用于制造SOI中的JFET的设计结构，JFET和制造JFET的方法。 JFET包括直接在SOI层上形成的栅极多晶硅，并且栅极氧化层插入在栅极多晶硅和SOI层的外边缘之间。

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