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21. 发明申请

US20130070549A1 Single-Ended Sense Amplifier with Read-Assist 失效
标题翻译：具有读辅助功能的单端读出放大器
公开(公告)号：US20130070549A1
公开(公告)日：2013-03-21
申请号：US13234218
申请日：2011-09-16
申请人： Amlan Ghosh , Jente B. Kuang
发明人： Amlan Ghosh , Jente B. Kuang
IPC分类号： G11C7/12
CPC分类号： G11C11/412 , G11C7/067
摘要： A sense amplifier is provided that comprises, responsive to receiving a set signal to turn on a set device and a precharged voltage level read bit line signal, a keeper device that turns on responsive to receiving a LOW signal from an inverting amplifier and pulls up the voltage at a first node so that a HIGH signal is output onto a global bit line. Responsive to receiving the set signal to turn on the set device and a read bit line signal that is discharging through a read stack path to ground and responsive to the read bit line signal discharging below a first predesigned voltage level, a read assist device in the sense amplifier turns on responsive to receiving a HIGH signal from the inverting amplifier and pulls down the voltage at the first node so that a LOW state is output onto a global bit line.
摘要翻译：提供了一种读出放大器，其包括响应于接收到设置信号以打开设备设备和预充电电压电平读取位线信号，保持器设备响应于从反相放大器接收低电平信号而接通，并且将上拉电压在第一节点处，使得HIGH信号被输出到全局位线。响应于接收所设置的信号以使所述设置装置和读取的位线信号通过读取堆叠路径放电到地并且响应于读取位线信号放电低于第一预先设计的电压电平，读取辅助装置在读出放大器响应于从反相放大器接收到高电平信号并且降低第一节点处的电压而导通，使得LOW状态输出到全局位线。

22. 发明申请

US20120212997A1 TEST STRUCTURE FOR CHARACTERIZING MULTI-PORT STATIC RANDOM ACCESS MEMORY AND REGISTER FILE ARRAYS 失效
标题翻译：表征多端口静态随机访问存储器和寄存器文件阵列的测试结构
公开(公告)号：US20120212997A1
公开(公告)日：2012-08-23
申请号：US13459932
申请日：2012-04-30
申请人： Leland Chang , Jente B. Kuang , Robert K. Montoye , Hung C. Ngo , Kevin J. Nowka
发明人： Leland Chang , Jente B. Kuang , Robert K. Montoye , Hung C. Ngo , Kevin J. Nowka
IPC分类号： G11C29/00
CPC分类号： G11C8/16 , G11C29/32 , G11C29/50 , G11C29/50012
摘要： A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes. Selection control circuitry selectively enables the multiple data path access nodes for the SRAM cells within the characterization circuit.
摘要翻译：用于表征生产静态随机存取存储器（SRAM）阵列的测试结构。测试结构包括具有串联连接的多个存储单元列的表征电路，以形成环形结构。表征电路在与生产SRAM阵列相同并且靠近生产SRAM阵列的晶片衬底上制造。表征电路优选地包括具有与生产SRAM阵列内的存储器单元的电路拓扑基本相同的电路拓扑的SRAM单元。在一个实施例中，测试结构用于表征多端口存储器阵列，并且包括串联连接的多个存储单元列，以形成环形振荡器表征电路。表征电路中的每个单元列包括多个具有锁存节点和多个数据路径接入节点的SRAM单元。选择控制电路选择性地启用表征电路内的SRAM单元的多个数据路径接入节点。

23. 发明授权

US08102194B2 Dual frequency divider having phase-shifted inputs and outputs 失效
标题翻译：双分频器具有相移输入和输出
公开(公告)号：US08102194B2
公开(公告)日：2012-01-24
申请号：US12860302
申请日：2010-08-20
申请人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
发明人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
IPC分类号： H03K3/01
CPC分类号： H02M3/073 , H02M2003/077 , H03L5/00
摘要： A distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power. Clock signal division and phase offset may be extended to multiple levels for further smoothing of the pump clock signal transitions. A dual frequency divider may be used which receives the clock signal and its complement, and generates two divided signals that are 90° out of phase. In an illustrative embodiment the clock generator comprises a variable-frequency clock source, and a voltage regulator senses an output voltage of the charge pumps, generates a reference voltage based on a currently selected frequency of the variable-frequency clock source, and temporarily disables the charge pumps (by turning off local pump clocks) when the output voltage is greater than the reference voltage.
摘要翻译：分布式电荷泵系统使用延迟元件和分频器产生驱动不同电荷泵的异相泵浦时钟信号，以抵消每个电荷泵的峰值电流时钟边缘，从而降低总体峰值功率。时钟信号分频和相位偏移可以扩展到多个级别，以进一步平滑泵时钟信号转换。可以使用双分频器，其接收时钟信号及其补码，并产生相位差为90°的两个分频信号。在说明性实施例中，时钟发生器包括可变频率时钟源，并且电压调节器感测电荷泵的输出电压，基于当前选择的可变频率时钟源的频率产生参考电压，并暂时禁用当输出电压大于参考电压时，电荷泵（通过关闭本地泵浦时钟）。

24. 发明申请

US20110225438A1 COMPUTER PROGRAM PRODUCT FOR CONTROLLING A STORAGE DEVICE HAVING PER-ELEMENT SELECTABLE POWER SUPPLY VOLTAGES 有权
标题翻译：用于控制具有各元件选择电源电压的存储设备的计算机程序产品
公开(公告)号：US20110225438A1
公开(公告)日：2011-09-15
申请号：US13115149
申请日：2011-05-25
申请人： Rajiv V. Joshi , Jente B. Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B. Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G06F1/32
CPC分类号： G11C11/417 , G11C5/14
摘要： A computer program product for controlling a storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.
摘要翻译：用于使用每元件可选择的电源电压来控制存储设备的计算机程序产品在保持特定性能水平的同时在存储设备中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非元件满足性能要求需要更高的电源电压。可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

25. 发明授权

US07994845B2 Switched-capacitor charge pumps 有权
标题翻译：开关电容充电泵
公开(公告)号：US07994845B2
公开(公告)日：2011-08-09
申请号：US12778960
申请日：2010-05-12
申请人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
发明人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
IPC分类号： G05F3/16 , G05F1/46 , H02M3/18
CPC分类号： H02M3/07 , G11C5/145 , G11C11/4074 , G11C2207/104
摘要： A switched-capacitor charge pump comprises a two-phase charging circuit, cross-coupled transistors connected to output nodes of the switched capacitors, and a pump output connected to source terminals of the cross-coupled transistors. The charge pump has side transistors for boosting charge transfer, and gating logic of the side transistors includes level shifters which control connections to the pump output or a reference voltage. Negative and positive charge pump embodiments are provided. The charging circuit utilizes non-overlapping wide and narrow clock signals to generate multiple gating signals. The pump clock circuit preferably provides independent, programmable adjustment of the widths of the wide and narrow clock signals. An override mode can be provided using clamping circuits which shunt the pump output to the second nodes of the switched capacitors.
摘要翻译：开关电容器电荷泵包括两相充电电路，连接到开关电容器的输出节点的交叉耦合晶体管和连接到交叉耦合晶体管的源极端子的泵浦输出。电荷泵具有用于升压电荷转移的侧晶体管，并且侧晶体管的选通逻辑包括电平转换器，其控制与泵输出的连接或参考电压。提供负电荷泵和正电荷泵实施例。充电电路利用不重叠的宽和窄时钟信号来产生多个门控信号。泵时钟电路优选地提供宽和窄时钟信号的宽度的独立的可编程调整。可以使用将泵浦输出分流到开关电容器的第二节点的钳位电路来提供覆盖模式。

26. 发明申请

US20090129193A1 ENERGY EFFICIENT STORAGE DEVICE USING PER-ELEMENT SELECTABLE POWER SUPPLY VOLTAGES 失效
标题翻译：使用全能选择电源电压的能源效率存储设备
公开(公告)号：US20090129193A1
公开(公告)日：2009-05-21
申请号：US11941168
申请日：2007-11-16
申请人： Rajiv V. Joshi , Jente B. Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B. Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G11C5/14 , G06F12/00
CPC分类号： G11C11/417 , G11C5/14
摘要： An energy efficient storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.
摘要翻译：使用每元件可选择的电源电压的节能存储装置在保持特定的性能水平的同时在存储装置中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非元件满足性能要求需要更高的电源电压。可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

27. 发明申请

US20080225615A1 PULSED RING OSCILLATOR CIRCUIT FOR STORAGE CELL READ TIMING EVALUATION 有权
标题翻译：用于存储单元的脉冲振荡器电路读取时序评估
公开(公告)号：US20080225615A1
公开(公告)日：2008-09-18
申请号：US12128526
申请日：2008-05-28
申请人： Gary D. Carpenter , Jente B. Kuang , Kevin J. Nowka , Liang-Teck Pang
发明人： Gary D. Carpenter , Jente B. Kuang , Kevin J. Nowka , Liang-Teck Pang
IPC分类号： G11C29/00
CPC分类号： G01R31/31725 , G01R31/31727 , G01R31/318511 , G11C29/1201 , G11C29/50 , G11C2029/5002 , G11C2029/5006
摘要： A pulsed ring oscillator circuit for storage cell read timing evaluation provides read strength information. A pulse generator is coupled to a bitline to which the storage cell to be measured is connected. The storage cell thereby forms part of the ring oscillator and the read strength of the storage cell is reflected in the frequency of oscillation. A pulse regeneration circuit is included in the ring so that the storage cell read loading does not cause the oscillation to decay. Alternatively, a counter may be used to count the number of oscillations until the oscillations decay, which also yields a measure of the read strength of the storage cell. The pulse generator may have variable output current, and the current varied to determine a change in current with the storage cell enabled and disabled that produces the same oscillation frequency. The read current is the difference between currents.
摘要翻译：用于存储单元读取定时评估的脉冲环形振荡器电路提供读取强度信息。脉冲发生器耦合到待测量的存储单元连接到的位线。因此，存储单元形成环形振荡器的一部分，并且存储单元的读取强度被反映在振荡频率中。在环中包括脉冲再生电路，使得存储单元读取负载不会导致振荡衰减。或者，可以使用计数器对振荡次数进行计数，直到振荡衰减，这也产生存储单元的读取强度的量度。脉冲发生器可以具有可变输出电流，并且电流变化以确定产生相同振荡频率的存储单元的使能和禁用的电流变化。读取电流是电流之间的差异。

28. 发明申请

US20080155362A1 Test Structure for Characterizing Multi-Port Static Random Access Memory and Register File Arrays 有权
标题翻译：用于表征多端口静态随机存取存储器和寄存器文件数组的测试结构
公开(公告)号：US20080155362A1
公开(公告)日：2008-06-26
申请号：US11552158
申请日：2006-10-24
申请人： Leland Chang , Jente B. Kuang , Robert K. Montoye , Hung C. Ngo , Kevin J. Nowka
发明人： Leland Chang , Jente B. Kuang , Robert K. Montoye , Hung C. Ngo , Kevin J. Nowka
IPC分类号： G11C29/00
CPC分类号： G11C8/16 , G11C29/32 , G11C29/50 , G11C29/50012
摘要： A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes. Selection control circuitry selectively enables the multiple data path access nodes for the SRAM cells within the characterization circuit.
摘要翻译：用于表征生产静态随机存取存储器（SRAM）阵列的测试结构。测试结构包括具有串联连接的多个存储单元列的表征电路，以形成环形结构。表征电路在与生产SRAM阵列相同并且靠近生产SRAM阵列的晶片衬底上制造。表征电路优选地包括具有与生产SRAM阵列内的存储器单元的电路拓扑基本相同的电路拓扑的SRAM单元。在一个实施例中，测试结构用于表征多端口存储器阵列，并且包括串联连接的多个存储单元列，以形成环形振荡器表征电路。表征电路中的每个单元列包括多个具有锁存节点和多个数据路径接入节点的SRAM单元。选择控制电路选择性地启用表征电路内的SRAM单元的多个数据路径接入节点。

29. 发明申请

US20080137455A1 Storage Cell Design Evaluation Circuit Including a Wordline Timing and Cell Access Detection Circuit 失效
标题翻译：包括字线定时和单元访问检测电路的存储单元设计评估电路
公开(公告)号：US20080137455A1
公开(公告)日：2008-06-12
申请号：US11609598
申请日：2006-12-12
申请人： Sebastian Ehrenreich , Jente B Kuang , Chun-Tao Li , Hung Cai Ngo
发明人： Sebastian Ehrenreich , Jente B Kuang , Chun-Tao Li , Hung Cai Ngo
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/02 , G11C29/025 , G11C29/50012
摘要： A method for storage cell design evaluation provides accurate information about state changes in static storage cells. A wordline select pulse is propagated along the wordline select path of the test row to an output driver circuit, in order to test the clock and/or address timing of the row, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. An access detection cell holds the input of the output driver circuit until a simulated access operation activated by the wordline select pulse is complete. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.
摘要翻译：用于存储单元设计评估的方法提供关于静态存储单元中的状态变化的准确信息。字线选择脉冲沿着测试行的字线选择路径传播到输出驱动器电路，以便测试该行的时钟和/或地址时序，使得访问时序，读取稳定性和可写性与字线强度的变化 /访问电压可以确定。访问检测单元保持输出驱动器电路的输入，直到由字线选择脉冲激活的模拟访问操作完成。多个测试行可以在列之间级联，以提供长延迟线或环形振荡器，以提高测量分辨率。

30. 发明申请

US20080122490A1 Circular Edge Detector 失效
标题翻译：圆形边缘检测器
公开(公告)号：US20080122490A1
公开(公告)日：2008-05-29
申请号：US11563888
申请日：2006-11-28
申请人： Jerry C. Kao , Jente B. Kuang , Alan J. Drake , Gary D. Carpenter , Fadi H. Gebara
发明人： Jerry C. Kao , Jente B. Kuang , Alan J. Drake , Gary D. Carpenter , Fadi H. Gebara
IPC分类号： H03K5/22
CPC分类号： H03K5/1534
摘要： A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell signal, and a state capture block operably connected to receive the present cell signal. The present cell signal of each of the plurality of edge detector cells is provided to a next of the plurality of edge detector cells as the previous cell signal for the next of the plurality of edge detector cells, and the present cell signal from a last edge detector cell is provided to a first edge detector cell as the previous cell signal for the first edge detector cell.
摘要翻译：在包括多个边缘检测器单元的集成电路上的圆形边缘检测器，所述多个边缘检测器单元中的每一个具有可操作以接收数据信号和先前信元信号并产生当前信元信号的输入选择块，以及状态捕捉块可操作地连接以接收当前信元信号。将多个边缘检测器单元中的每一个的当前单元信号提供给多个边缘检测器单元中的下一个，作为用于下一个边缘检测器单元的先前单元信号，并且来自最后边沿的当前单元信号检测器单元被提供给第一边缘检测器单元作为用于第一边缘检测器单元的先前单元信号。

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