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21. 发明授权

US06256713B1 Bus optimization with read/write coherence including ordering responsive to collisions 失效
标题翻译：具有读/写一致性的总线优化，包括响应于冲突的顺序
公开(公告)号：US06256713B1
公开(公告)日：2001-07-03
申请号：US09303365
申请日：1999-04-29
申请人： Srinath Audityan , James Nolan Hardage, Jr. , Thomas Albert Petersen
发明人： Srinath Audityan , James Nolan Hardage, Jr. , Thomas Albert Petersen
IPC分类号： G06F1200
CPC分类号： G06F13/18 , G06F12/0831
摘要： The present invention provides a method and apparatus for optimizing bus utilization while maintaining read and write coherence. More specifically the invention provides bus utilization optimization by prioritizing read transactions before write transactions, where there is no collision pending. When a collision pending is determined, then the read and write transactions are processed according to the age of the transaction(s) allowing for data coherency.
摘要翻译：本发明提供了一种在保持读写一致性的同时优化总线利用的方法和装置。更具体地，本发明通过在写入事务之前对读取事务进行优先级来提供总线利用率优化，其中没有冲突挂起。当确定冲突挂起时，则根据允许数据一致性的事务的年龄来处理读和写事务。

22. 发明授权

US09081581B2 Size mis-match hazard detection 有权
标题翻译：尺寸误匹配危险检测
公开(公告)号：US09081581B2
公开(公告)日：2015-07-14
申请号：US12926414
申请日：2010-11-16
申请人： James Nolan Hardage , Conrado Blasco Allue , Glen Andrew Harris
发明人： James Nolan Hardage , Conrado Blasco Allue , Glen Andrew Harris
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40 , G06F9/38
CPC分类号： G06F9/3861 , G06F9/30112 , G06F9/3016 , G06F9/384 , G06F9/3842
摘要： An out-of-order processor 4 groups program instructions together to control their commitment to complete processing. If an instruction within a group has a source operand dependent upon a plurality of destination operands of other instructions then this is identified as a size mismatch hazard. When the program instruction having the size mismatch hazard reaches a commit point within the processor, then it is flushed together with any speculatively executed succeeding program instructions. Furthermore, the group of program instructions containing the program instruction containing the program instruction having the size mismatch is divided into a plurality of groups of program instructions each containing a single program instruction which are then replayed through the processing mechanisms.
摘要翻译：无序处理器将程序指令组合在一起，以控制其完成处理的承诺。如果组内的指令具有取决于其他指令的多个目的地操作数的源操作数，则将其识别为大小不匹配危险。当具有大小不匹配危险的程序指令到达处理器内的提交点时，它与任何推测性执行的后续程序指令一起被刷新。此外，包含包含具有尺寸不匹配的程序指令的程序指令的程序指令组被划分为多个程序指令组，每组程序指令都包含单个程序指令，然后通过处理机制重播程序指令。

23. 发明申请

US20110208950A1 PROCESSES, CIRCUITS, DEVICES, AND SYSTEMS FOR SCOREBOARD AND OTHER PROCESSOR IMPROVEMENTS 审中-公开
标题翻译：过程，电路，设备和系统的分数和其他处理器改进
公开(公告)号：US20110208950A1
公开(公告)日：2011-08-25
申请号：US13053000
申请日：2011-03-21
申请人： Thang Minh Tran , Raul A. Garibay, JR. , James Nolan Hardage
发明人： Thang Minh Tran , Raul A. Garibay, JR. , James Nolan Hardage
IPC分类号： G06F9/30
CPC分类号： G06F9/3826 , G06F9/3838
摘要： A method of instruction issue (3200) in a microprocessor (1100, 1400, or 1500) with execution pipestages (E1, E2, etc.) and that executes a producer instruction Ip and issues a candidate instruction I0 (3245) having a source operand dependency on a destination operand of instruction Ip. The method includes issuing the candidate instruction I0 as a function (1720, 1950, 1958, 3235) of a pipestage EN(I0) of first need by the candidate instruction for the source operand, a pipestage EA(Ip) of first availability of the destination operand from the producer instruction, and the one execution pipestage E(Ip) currently associated with the producer instruction. A method of data forwarding (3300) in a microprocessor (1100, 1400, or 1500) having a pipeline (1640) having pipestages (E1, E2, etc.), wherein the method includes scoreboarding information E(Ip) (1710, 2220) to represent a changing pipestage position for data from a producer instruction Ip, and selectively forwarding (2310, 3360) the data from the pipestage having the represented pipestage position E(Ip), based on the information (1710), to a receiving pipestage (1682, E1) for a dependent instruction. Wireless communications devices (1010, 1010′, 1040, 1050, 1060, 1080), systems, circuits, devices, scoreboards (1700.N), processes and methods of operation, processes and articles of manufacture (FIGS. 13-16), are also disclosed.
摘要翻译：一种在具有执行分支（E1，E2等）的微处理器（1100,1400或1500）中执行指令发出（3200）的方法，并且执行生成器指令Ip并发出具有源操作数的候选指令I0（3245）依赖于指令Ip的目标操作数。该方法包括作为源操作数的候选指令首先需要的分支管理EN（I0）的函数（1720,195，...，1935，3235）发出候选指令I0，以及源操作数的第一可用性的分支EA（Ip）来自生产者指令的目的地操作数和当前与生产者指令相关联的一个执行管道E（Ip）。一种具有具有分支（E1，E2等）的流水线（1640）的微处理器（1100,1400或1500）中的数据转发（3300）方法，其中该方法包括记分板信息E（Ip）（1710,2220 ）表示来自生产者指令Ip的数据的变化的管道位置，并且基于所述信息（1710）从具有所述管道位置E（Ip）的所述管道选择性地将（2310,3360）的数据转发到接收管道（1682，E1）用于依赖指令。无线通信设备（1010,1010'，1040,1050,1060,1080），系统，电路，设备，记分板（1700.N），操作过程和方法，过程和制品（图13-16）也被披露。

24. 发明授权

US06636980B1 System for launching data on a bus by using first clock for alternately selecting data from two data streams and using second clock for launching data thereafter 失效
标题翻译：用于通过使用第一时钟用于从两个数据流交替地选择数据并且之后使用第二时钟启动数据来在总线上启动数据的系统
公开(公告)号：US06636980B1
公开(公告)日：2003-10-21
申请号：US09377632
申请日：1999-08-19
申请人： Gilles Gervais , David George Caffo , James Nolan Hardage, Jr. , Stephen Douglas Weitzel
发明人： Gilles Gervais , David George Caffo , James Nolan Hardage, Jr. , Stephen Douglas Weitzel
IPC分类号： G06F106
CPC分类号： G06F13/4243
摘要： A bus interface apparatus and method are implemented. A pair of data streams is generated from the stream of data to be launched onto a data bus. Each stream is staged along a corresponding data path that includes a plurality of storage elements. Each path feeds an input of a multiplexer (MUX). The output of the MUX drives the bus, and the MUX selects a data value for launching onto the bus in response to a signal derived from an internal bus clock. The internal bus clock is also used to generate a bus clock that is output to the bus along with the data. The period of the bus clock may be a preselected multiple of the period of a processor clock. The data is staged along the two data streams in response to clocking signals derived from the processor clock. Each of the clocking signals is qualified by a corresponding hold signal, that, when asserted, holds the clocking signals in a predetermined state. The hold signals are generated in response to a plurality of control signals that are used to select the ratio of bus clock period to processor clock period. The bus interface may be asynchronously started in response to a signal from the startup logic in the central processing unit (CPU).
摘要翻译：实现总线接口装置和方法。从要发送到数据总线上的数据流生成一对数据流。每个流沿着包括多个存储元件的对应数据路径进行分级。每个路径馈送多路复用器（MUX）的输入。 MUX的输出驱动总线，并且MUX响应于从内部总线时钟导出的信号，选择用于发送到总线上的数据值。内部总线时钟也用于生成与数据一起输出到总线的总线时钟。总线时钟的周期可以是处理器时钟周期的预选倍数。响应于从处理器时钟导出的时钟信号，数据沿着两个数据流分段。每个时钟信号由相应的保持信号限定，当被断言时，将时钟信号保持在预定状态。响应于用于选择总线时钟周期与处理器时钟周期的比率的多个控制信号而产生保持信号。响应于来自中央处理单元（CPU）中的启动逻辑的信号，总线接口可以异步启动。

25. 发明授权

US06415362B1 Method and system for write-through stores of varying sizes 失效
标题翻译：不同大小的直写存储器的方法和系统
公开(公告)号：US06415362B1
公开(公告)日：2002-07-02
申请号：US09303364
申请日：1999-04-29
申请人： James Nolan Hardage , Alexander Edward Okpisz , Thomas Albert Petersen
发明人： James Nolan Hardage , Alexander Edward Okpisz , Thomas Albert Petersen
IPC分类号： G06F1200
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/0886
摘要： A method and system for performing write-through store operations of valid data of varying sizes in a data processing system, where the data processing system includes multiple processors that are coupled to an interconnect through a memory hierarchy, where the memory hierarchy includes multiple levels of cache, where at least one lower level of cache of the multiple of levels of cache requires store operations of all valid data of at least a predetermined size. First, it is determined whether or not a write-through store operation is a cache hit in a higher level of cache of the multiple levels of cache. In response to a determination that cache hit has occurred in the higher level of cache, the write-through store operation is merged with data read from the higher level of cache to provide a merged write-through operation of all valid data of at least the predetermined size to a lower level of cache. The merged write-through operation is performed in the lower level of cache, such that write-through operations of varying sizes to a lower level of cache which requires write operations of all valid data of at least a predetermined size are performed with data merged from a higher level of cache.
摘要翻译：一种用于在数据处理系统中执行不同大小的有效数据的直写存储操作的方法和系统，其中所述数据处理系统包括通过存储器层级耦合到互连的多个处理器，其中所述存储器层级包括高速缓存，其中多个级别的高速缓存的至少一个较低级别的高速缓存需要至少预定大小的所有有效数据的存储操作。首先，确定直写存储操作是否是多级高速缓存的更高级别的高速缓存命中。响应于在较高级别的缓存中发生高速缓存命中的确定，直写存储操作与从较高级别的高速缓存读取的数据合并，以提供所有有效数据的合并直写操作，所述有效数据至少为预定大小到较低级别的缓存。在较低级别的缓存中执行合并的直写操作，使得对需要至少预定大小的所有有效数据的写操作的高速缓存的较低级别的写入操作执行，其中从更高级的缓存。

26. 发明授权

US06119204A Data processing system and method for maintaining translation lookaside buffer TLB coherency without enforcing complete instruction serialization 失效
标题翻译：用于保持翻译后备缓冲器TLB一致性的数据处理系统和方法，而不强制执行完整的指令串行化
公开(公告)号：US06119204A
公开(公告)日：2000-09-12
申请号：US108157
申请日：1998-06-30
申请人： Joseph Yih Chang , James Nolan Hardage, Jr. , Jose Melanio Nunez , Thomas Albert Petersen
发明人： Joseph Yih Chang , James Nolan Hardage, Jr. , Jose Melanio Nunez , Thomas Albert Petersen
IPC分类号： G06F12/10 , G06F13/14 , G06F12/08
CPC分类号： G06F12/1027 , G06F2212/682
摘要： A data processing system includes at least a first processor and a second processor that each have a respective translation lookaside buffer (TLB). In response to detection by the second processor of a TLB entry invalidation request, the second processor marks at least one memory referent instruction that is being processed by the second processor and invalidates a TLB entry in the TLB of the second processor. In response to receipt of a synchronization request at the second processor, the second processor indicates to the first processor that the second processor has invalidated the TLB entry if the second processor has completed processing the marked instruction. During the interval between receipt of the synchronization request and indicating to the first processor that the second processor has invalidated the TLB entry, the second processor continues to process instructions, including fetching instructions for processing. In this manner, the second processor is able to continue normal instruction processing during the process of TLB synchronization.
摘要翻译：数据处理系统至少包括第一处理器和第二处理器，每个具有相应的翻译后备缓冲器（TLB）。响应于第二处理器检测到TLB条目无效请求，第二处理器标记正在由第二处理器处理的至少一个存储器指示指令，并使第二处理器的TLB中的TLB条目无效。响应于在第二处理器处接收到同步请求，第二处理器向第一处理器指示如果第二处理器已经完成处理标记的指令，则第二处理器使TLB条目无效。在接收到同步请求和向第一处理器指示第二处理器使TLB条目无效的间隔期间，第二处理器继续处理指令，包括取指令进行处理。以这种方式，第二处理器能够在TLB同步的处理期间继续正常的指令处理。

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