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1. 发明申请

US20100332805A1 Remapping source Registers to aid instruction scheduling within a processor 有权
标题翻译：重映射源寄存器以帮助处理器内的指令调度
公开(公告)号：US20100332805A1
公开(公告)日：2010-12-30
申请号：US12457905
申请日：2009-06-24
申请人： Conrado Blasco Allue , David James Williamson , James Nolan Hardage , Glen Andrew Harris , Robert Gregory McDonald
发明人： Conrado Blasco Allue , David James Williamson , James Nolan Hardage , Glen Andrew Harris , Robert Gregory McDonald
IPC分类号： G06F9/30
CPC分类号： G06F9/30112 , G06F9/3017 , G06F9/3836 , G06F9/384
摘要： An out-of-order renaming processor is provided with a register file within which aliasing between registers of different sizes may occur. In this way a program instruction having a source register of a double precision size may alias with two single precision registers being used as destinations of one or more preceding program instructions. In order to track this data dependency the double precision register may be remapped into a micro-operation specifying two single precision registers as its source register. In this way, scheduling circuitry may use its existing hazard detection and management mechanisms to handle potential data hazards and dependencies. Not all program instructions having such data hazards between registers of different sizes are handled by this source register remapping. For these other program instructions a slower mechanism for dealing with the data dependency hazard is provided. This slower mechanism may, for example, be to drain all the preceding micro-operations from the execution pipelines before issuing the micro-operation having the data hazard.
摘要翻译：无序重命名处理器具有寄存器文件，在该寄存器文件中可能发生不同大小的寄存器之间的混叠。以这种方式，具有双精度尺寸的源寄存器的程序指令可以使用两个单精度寄存器作为一个或多个先前程序指令的目的地。为了跟踪这种数据依赖关系，双精度寄存器可以重新映射成指定两个单精度寄存器作为其源寄存器的微操作。以这种方式，调度电路可以使用其现有的危险检测和管理机制来处理潜在的数据危害和依赖性。并不是所有具有不同大小的寄存器之间的数据危害的程序指令都由该源寄存器重新映射来处理。对于这些其他程序指令，提供了一种用于处理数据依赖性危害的较慢机制。例如，这种较慢的机制可能在发出具有数据危险的微操作之前从执行管线中排出所有先前的微操作。

2. 发明授权

US09081581B2 Size mis-match hazard detection 有权
标题翻译：尺寸误匹配危险检测
公开(公告)号：US09081581B2
公开(公告)日：2015-07-14
申请号：US12926414
申请日：2010-11-16
申请人： James Nolan Hardage , Conrado Blasco Allue , Glen Andrew Harris
发明人： James Nolan Hardage , Conrado Blasco Allue , Glen Andrew Harris
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40 , G06F9/38
CPC分类号： G06F9/3861 , G06F9/30112 , G06F9/3016 , G06F9/384 , G06F9/3842
摘要： An out-of-order processor 4 groups program instructions together to control their commitment to complete processing. If an instruction within a group has a source operand dependent upon a plurality of destination operands of other instructions then this is identified as a size mismatch hazard. When the program instruction having the size mismatch hazard reaches a commit point within the processor, then it is flushed together with any speculatively executed succeeding program instructions. Furthermore, the group of program instructions containing the program instruction containing the program instruction having the size mismatch is divided into a plurality of groups of program instructions each containing a single program instruction which are then replayed through the processing mechanisms.
摘要翻译：无序处理器将程序指令组合在一起，以控制其完成处理的承诺。如果组内的指令具有取决于其他指令的多个目的地操作数的源操作数，则将其识别为大小不匹配危险。当具有大小不匹配危险的程序指令到达处理器内的提交点时，它与任何推测性执行的后续程序指令一起被刷新。此外，包含包含具有尺寸不匹配的程序指令的程序指令的程序指令组被划分为多个程序指令组，每组程序指令都包含单个程序指令，然后通过处理机制重播程序指令。

3. 发明授权

US08386754B2 Renaming wide register source operand with plural short register source operands for select instructions to detect dependency fast with existing mechanism 有权
标题翻译：重新命名宽的寄存器源操作数，具有多个短寄存器源操作数，用于使用现有机制快速检测依赖关系的选择指令
公开(公告)号：US08386754B2
公开(公告)日：2013-02-26
申请号：US12457905
申请日：2009-06-24
申请人： Conrado Blasco Allue , David James Williamson , James Nolan Hardage , Glen Andrew Harris , Robert Gregory McDonald
发明人： Conrado Blasco Allue , David James Williamson , James Nolan Hardage , Glen Andrew Harris , Robert Gregory McDonald
IPC分类号： G06F9/38
CPC分类号： G06F9/30112 , G06F9/3017 , G06F9/3836 , G06F9/384
摘要： An out-of-order renaming processor is provided with a register file within which aliasing between registers of different sizes may occur. In this way a program instruction having a source register of a double precision size may alias with two single precision registers being used as destinations of one or more preceding program instructions. In order to track this data dependency the double precision register may be remapped into a micro-operation specifying two single precision registers as its source register. In this way, scheduling circuitry may use its existing hazard detection and management mechanisms to handle potential data hazards and dependencies. Not all program instructions having such data hazards between registers of different sizes are handled by this source register remapping. For these other program instructions a slower mechanism for dealing with the data dependency hazard is provided. This slower mechanism may, for example, be to drain all the preceding micro-operations from the execution pipelines before issuing the micro-operation having the data hazard.
摘要翻译：无序重命名处理器具有寄存器文件，在该寄存器文件中可能发生不同大小的寄存器之间的混叠。以这种方式，具有双精度尺寸的源寄存器的程序指令可以使用两个单精度寄存器作为一个或多个先前程序指令的目的地。为了跟踪这种数据依赖关系，双精度寄存器可以重新映射成指定两个单精度寄存器作为其源寄存器的微操作。以这种方式，调度电路可以使用其现有的危险检测和管理机制来处理潜在的数据危害和依赖性。并不是所有具有不同大小的寄存器之间的数据危害的程序指令都由该源寄存器重新映射来处理。对于这些其他程序指令，提供了一种用于处理数据依赖性危害的较慢机制。例如，这种较慢的机制可以在发出具有数据危险的微操作之前从执行管线中排出所有先前的微操作。

4. 发明申请

US20120124346A1 Decoding conditional program instructions 审中-公开
标题翻译：解码条件程序指令
公开(公告)号：US20120124346A1
公开(公告)日：2012-05-17
申请号：US12926395
申请日：2010-11-15
申请人： James Nolan Hardage , Conrado Blasco Allue , Glen Andrew Harris , David James Williamson
发明人： James Nolan Hardage , Conrado Blasco Allue , Glen Andrew Harris , David James Williamson
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/30072 , G06F9/30145 , G06F9/3017 , G06F9/3842 , G06F9/3887
摘要： A processor 2 includes instruction decoding circuitry 8 and processing circuitry 16, 18, 20, 22, 24. The instruction decoding circuitry decodes at least one conditional program instruction in accordance with a conditional prediction as one of, in accordance with the condition prediction being a condition pass, one or more micro-operation instructions that control the processing circuitry to perform the processing action together with a condition resolution micro-operation instruction, or in accordance with the condition prediction being a condition fail, at least a condition resolution micro-operation instruction. Condition resolution circuitry 24 responds to the condition resolution micro-operation instruction to determine if the condition prediction is incorrect. If the condition prediction is incorrect, then the condition resolution circuitry flushes any micro-operation instructions associated with the conditional program instruction from the processing circuitry, changes the condition prediction to a new prediction and triggers the redecoding of the conditional program instruction in accordance with the new condition prediction.
摘要翻译：处理器2包括指令解码电路8和处理电路16,18,20,22,24 24.指令解码电路根据条件预测将至少一个条件程序指令解码为根据条件预测为条件通过，一个或多个微操作指令，其控制处理电路与条件分辨率微操作指令一起执行处理动作，或者根据状态预测是条件失败，至少条件分辨率微操作指令。条件解析电路24响应条件分辨率微操作指令以确定条件预测是否不正确。如果条件预测不正确，则条件分辨率电路从处理电路刷新与条件程序指令相关联的任何微操作指令，将条件预测改变为新的预测，并根据该条件程序指令触发重新编码条件程序指令新条件预测。

5. 发明申请

US20120124337A1 Size mis-match hazard detection 有权
标题翻译：尺寸误匹配危险检测
公开(公告)号：US20120124337A1
公开(公告)日：2012-05-17
申请号：US12926414
申请日：2010-11-16
申请人： James Nolan Hardage , Conrado Blasco Allue , Glen Andrew Harris
发明人： James Nolan Hardage , Conrado Blasco Allue , Glen Andrew Harris
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/30112 , G06F9/3016 , G06F9/384 , G06F9/3842
摘要： An out-of-order processor 4 groups program instructions together to control their commitment to complete processing. If an instruction within a group has a source operand dependent upon a plurality of destination operands of other instructions then this is identified as a size mismatch hazard. When the program instruction having the size mismatch hazard reaches a commit point within the processor, then it is flushed together with any speculatively executed succeeding program instructions. Furthermore, the group of program instructions containing the program instruction containing the program instruction having the size mismatch is divided into a plurality of groups of program instructions each containing a single program instruction which are then replayed through the processing mechanisms.
摘要翻译：无序处理器将程序指令组合在一起，以控制其完成处理的承诺。如果组内的指令具有取决于其他指令的多个目的地操作数的源操作数，则将其识别为大小不匹配危险。当具有大小不匹配危险的程序指令到达处理器内的提交点时，它与任何推测性执行的后续程序指令一起被刷新。此外，包含包含具有尺寸不匹配的程序指令的程序指令的程序指令组被划分为多个程序指令组，每组程序指令都包含单个程序指令，然后通过处理机制重播程序指令。

6. 发明授权

US09946545B2 Buffer store with a main store and and auxiliary store 有权
公开(公告)号：US09946545B2
公开(公告)日：2018-04-17
申请号：US12926415
申请日：2010-11-16
申请人： James Nolan Hardage , Glen Andrew Harris , Mark Carpenter Glass
发明人： James Nolan Hardage , Glen Andrew Harris , Mark Carpenter Glass
IPC分类号： G06F15/00 , G06F9/00 , G06F9/44 , G06F9/38 , G06F5/06
CPC分类号： G06F9/3806 , G06F5/065 , G06F9/381
摘要： A loop buffer is provided with a main store 26 and an auxiliary store 28. The main store 26 stores micro-operation instructions. The auxiliary store 28 has fewer entries than the main store 26 and stores target addresses for predicted taken branch instructions stored within the main store 26. Read control circuitry serves to control reading from the main store and from an auxiliary store such that target addresses are read from the auxiliary store in association with the predicted taken branch instructions read from the main store.

7. 发明授权

US08972701B2 Setting zero bits in architectural register for storing destination operand of smaller size based on corresponding zero flag attached to renamed physical register 有权
标题翻译：在体系结构寄存器中设置零位，用于存储较小尺寸的目标操作数，并基于附加到重命名的物理寄存器的相应零标志
公开(公告)号：US08972701B2
公开(公告)日：2015-03-03
申请号：US13312131
申请日：2011-12-06
申请人： James Nolan Hardage , Glen Andrew Harris , Mark Carpenter Glass
发明人： James Nolan Hardage , Glen Andrew Harris , Mark Carpenter Glass
IPC分类号： G06F9/30 , G06F1/32
CPC分类号： G06F9/30003 , G06F1/3234 , G06F9/30014 , G06F9/30112 , G06F9/30189 , G06F9/384
摘要： A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural register value has a fixed bit width irrespective of the bit width of the destination operand being written thereto. Instead of adding these zero values everywhere in the data path, they are instead represented by zero flags in at least the physical registers utilized for register renaming operations and in the result queue prior to results being written to the architectural register file. This saves circuitry resources and reduces energy consumption.
摘要翻译：提供了一种数据处理系统，其中要存储在体系结构寄存器内的目的地操作数被限制为具有作为前缀添加的零值，以便架构寄存器值具有固定的位宽度，而与目的地操作数的写入宽度无关。而不是在数据路径中的任何地方添加这些零值，而是至少在用于寄存器重命名操作的物理寄存器和结果队列中将结果写入架构寄存器文件之前的零标志代表它们。这节省了电路资源并降低了能耗。

8. 发明授权

US08914615B2 Mapping same logical register specifier for different instruction sets with divergent association to architectural register file using common address format 有权
标题翻译：对不同的指令集映射相同的逻辑寄存器说明符，并使用通用地址格式与架构寄存器文件发散关联
公开(公告)号：US08914615B2
公开(公告)日：2014-12-16
申请号：US13309732
申请日：2011-12-02
申请人： Glen Andrew Harris , James Nolan Hardage , Mark Carpenter Glass
发明人： Glen Andrew Harris , James Nolan Hardage , Mark Carpenter Glass
IPC分类号： G06F9/34 , G06F9/38 , G06F9/30
CPC分类号： G06F9/30145 , G06F9/30098 , G06F9/30112 , G06F9/3012 , G06F9/30174 , G06F9/34 , G06F9/3824 , G06F9/384
摘要： A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.
摘要翻译：处理器核心支持从第一指令集和第二指令集两者执行程序指令。包含架构寄存器的架构寄存器文件18由两个指令集共享。两个指令集使用逻辑寄存器说明符，其中这些逻辑寄存器说明符的至少一些值对应于架构寄存器文件18内的不同结构寄存器。第一指令集的第一解码器4和用于第二指令集的第二解码器6 用于将逻辑寄存器说明符解码为公共寄存器寻址格式。该公共寄存器寻址格式用于向重命名电路10提供寄存器说明符，用于结合物理寄存器文件16和架构寄存器文件18来支持寄存器重命名。

9. 发明申请

US20120124301A1 Buffer store with a main store and an auxiliary store 有权
标题翻译：缓冲店与主店和辅助商店
公开(公告)号：US20120124301A1
公开(公告)日：2012-05-17
申请号：US12926415
申请日：2010-11-16
申请人： James Nolan Hardage , Glen Andrew Harris , Mark Carpenter Glass
发明人： James Nolan Hardage , Glen Andrew Harris , Mark Carpenter Glass
IPC分类号： G06F12/00
CPC分类号： G06F9/3806 , G06F5/065 , G06F9/381
摘要： A loop buffer is provided with a main store 26 and an auxiliary store 28. The main store 26 stores micro-operation instructions. The auxiliary store 28 has fewer entries than the main store 26 and stores target addresses for predicted taken branch instructions stored within the main store 26. Read control circuitry serves to control reading from the main store and from an auxiliary store such that target addresses are read from the auxiliary store in association with the predicted taken branch instructions read from the main store.
摘要翻译：环路缓冲器具有主存储器26和辅助存储器28.主存储器26存储微操作指令。辅助存储器28具有比主存储器26少的条目，并且存储存储在主存储器26内的预测采集分支指令的目标地址。读控制电路用于控制从主存储器和辅助存储器的读取，从而读取目标地址从辅助商店与从主店读取的预测的分支指令相关联。

10. 发明申请

US20130145127A1 ZERO VALUE PREFIXES FOR OPERANDS OF DIFFERING BIT-WIDTHS 有权
标题翻译：用于不同位宽的操作的零值前缀
公开(公告)号：US20130145127A1
公开(公告)日：2013-06-06
申请号：US13312131
申请日：2011-12-06
申请人： James Nolan Hardage , Glen Andrew Harris , Mark Carpenter Glass
发明人： James Nolan Hardage , Glen Andrew Harris , Mark Carpenter Glass
IPC分类号： G06F9/30 , G06F9/312
CPC分类号： G06F9/30003 , G06F1/3234 , G06F9/30014 , G06F9/30112 , G06F9/30189 , G06F9/384
摘要： A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural register value has a fixed bit width irrespective of the bit width of the destination operand being written thereto. Instead of adding these zero values everywhere in the data path, they are instead represented by zero flags in at least the physical registers utilised for register renaming operations and in the result queue prior to results being written to the architectural register file. This saves circuitry resources and reduces energy consumption.
摘要翻译：提供了一种数据处理系统，其中要存储在体系结构寄存器内的目的地操作数被限制为具有作为前缀添加的零值，以便架构寄存器值具有固定的位宽度，而与目的地操作数的写入宽度无关。而不是在数据路径中的任何地方添加这些零值，而是至少在用于寄存器重命名操作的物理寄存器和结果队列中将结果写入架构寄存器文件之前的零标志代表它们。这节省了电路资源并降低了能耗。

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