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21. 发明授权

US08674409B2 Heterojunction field effect transistor, method for producing heterojunction field effect transistor, and electronic device 有权
标题翻译：异质结场效应晶体管，异质结场效应晶体管的制造方法和电子器件
公开(公告)号：US08674409B2
公开(公告)日：2014-03-18
申请号：US13141449
申请日：2009-12-25
申请人： Takashi Inoue , Hironobu Miyamoto , Kazuki Ota , Tatsuo Nakayama , Yasuhiro Okamoto , Yuji Ando
发明人： Takashi Inoue , Hironobu Miyamoto , Kazuki Ota , Tatsuo Nakayama , Yasuhiro Okamoto , Yuji Ando
IPC分类号： H01L29/66
CPC分类号： H01L29/7787 , H01L29/0843 , H01L29/2003 , H01L29/41766 , H01L29/42316 , H01L29/66462
摘要： A heterojunction filed effect transistor with a low access resistance, a low on resistance, and the like, a method for producing a heterojunction filed effect transistor and an electron device are provided. In the heterojunction field effect transistor, an electron transit layer 11 formed of a III-nitride semiconductor is formed on a substrate 10, an electron supply layer 12 formed of a III-nitride semiconductor forms a heterojunction with an upper surface of the electron transit layer 11, a gate electrode 14, a source electrode 15A, and a drain electrode 15B are arranged on the electron supply layer 12, n-type conductive layer regions 13A and 13B each extended from an upper part of the electron transit layer 11 to an upper surface of the electron supply layer 12 are provided in at least a part below the source electrode 15A and a part below the drain electrode 15B, and an n-type impurity concentration at a heterojunction interface of an electron transit layer 11 part of each of the n-type conductive layer regions 13A and 13B with the electron supply layer 12 is 1×1020 cm−3 or more.
摘要翻译：提供具有低访问阻抗，低导通电阻等的异质结场效应晶体管，提供了异质结场效应晶体管和电子器件的制造方法。在异质结场效应晶体管中，在衬底10上形成由III族氮化物半导体形成的电子迁移层11，由III族氮化物半导体形成的电子供给层12与电子迁移层的上表面形成异质结如图11所示，在电子供给层12上配置有栅电极14，源电极15A和漏电极15B，从电子渡越层11的上部延伸到上部的n型导电层区域13A，13B 电子供给层12的表面设置在源电极15A的下方以及漏电极15B的下方的至少一部分以及电子迁移层11的异质界面的n型杂质浓度具有电子供给层12的n型导电层区域13A，13B为1×1020cm-3以上。

22. 发明申请

US20140013031A1 DATA STORAGE APPARATUS, MEMORY CONTROL METHOD, AND ELECTRONIC APPARATUS HAVING A DATA STORAGE APPARATUS 审中-公开
标题翻译：数据存储设备，存储器控制方法和具有数据存储设备的电子设备
公开(公告)号：US20140013031A1
公开(公告)日：2014-01-09
申请号：US13685877
申请日：2012-11-27
申请人： Yoko MASUO , Gen Ohshima , Hironobu Miyamoto , Tohru Fukuda , Yoshimasa Aoyama
发明人： Yoko MASUO , Gen Ohshima , Hironobu Miyamoto , Tohru Fukuda , Yoshimasa Aoyama
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , G06F12/0246
摘要： According to one embodiment, a data storage apparatus comprises a first controller, a second controller, a third controller, and a fourth controller. The first controller controls a flash memory, writing and reading data, in units of blocks, to and from the flash memory. The second controller detects any a write-interrupted block is interrupted by the first controller. The third controller sets the write-interrupted block detected by the second controller, as a block to be refreshed in another block. The fourth controller performs the process of refreshing.
摘要翻译：根据一个实施例，数据存储装置包括第一控制器，第二控制器，第三控制器和第四控制器。第一个控制器控制闪存，以块为单位写入和读取闪存中的数据。第二控制器检测到任何写入中断的块被第一控制器中断。第三控制器将由第二控制器检测到的写中断块设置为另一块中要刷新的块。第四个控制器执行刷新过程。

23. 发明授权

US08583859B2 Storage controller for wear-leveling and compaction and method of controlling thereof 有权
标题翻译：用于磨损平整和压实的存储控制器及其控制方法
公开(公告)号：US08583859B2
公开(公告)日：2013-11-12
申请号：US13154203
申请日：2011-06-06
申请人： Yoko Masuo , Hironobu Miyamoto , Wataru Okamoto
发明人： Yoko Masuo , Hironobu Miyamoto , Wataru Okamoto
IPC分类号： G06F12/16
CPC分类号： G06F12/0246 , G06F2212/7211
摘要： According to one embodiment, a storage controller includes a condition storage, a determination module, a wear-leveling block retainer, and a data transfer controller. The condition storage is provided in a storage including a plurality of blocks, and stores block condition information including at least one of erasure time information indicating when data is erased last time and erasure count information indicating the number of times data is erased. The determination module determines whether there is a block that requires wear leveling based on the block condition information. The wear-leveling block retainer retains block identification information that identifies a block determined to require wear leveling. The data transfer controller performs compaction to transfer data stored in blocks of the storage for collecting the data in a block, and, when the block identification information is retained, transfers data stored in the block identified by the block identification information.
摘要翻译：根据一个实施例，存储控制器包括条件存储器，确定模块，磨损均衡块保持器和数据传输控制器。条件存储被提供在包括多个块的存储器中，并且存储包括指示上次擦除数据的擦除时间信息中的至少一个的块条件信息，以及指示擦除次数数据的擦除计数信息。确定模块基于块条件信息确定是否存在需要磨损均衡的块。磨损平整块保持器保持块识别信息，其识别确定为需要磨损均匀化的块。数据传输控制器执行压缩以将存储在存储器块中的数据传送到块中以收集数据，并且当块识别信息被保留时，传送存储在由块识别信息识别的块中的数据。

24. 发明授权

US08476756B2 Semiconductor device and heat sink with 3-dimensional thermal conductivity 失效
标题翻译：具有三维导热性的半导体器件和散热片
公开(公告)号：US08476756B2
公开(公告)日：2013-07-02
申请号：US13137927
申请日：2011-09-21
申请人： Naotaka Kuroda , Akio Wakejima , Masahiro Tanomura , Hironobu Miyamoto
发明人： Naotaka Kuroda , Akio Wakejima , Masahiro Tanomura , Hironobu Miyamoto
IPC分类号： H01L23/34 , H01L23/10
CPC分类号： H01L23/367 , H01L23/373 , H01L23/66 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/072 , H01L2223/6644 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48137 , H01L2224/48247 , H01L2224/49 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01031 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/12041 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1423 , H01L2924/16195 , H01L2924/351 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device includes a semiconductor element having a rectangular two-dimensional geometry and serving as a heat source, a first heat sink section including the semiconductor element mounted thereon, and a second heat sink section joined to an opposite side of the first heat sink section that includes the semiconductor element. A relation among directional components of thermal conductivity is K1yy≧K1xx>K1zz, where directional components of a three-dimensional thermal conductivity of the heat sink section in X, Y, and Z directions are determined as Kxx, Kyy, and Kzz. A relation among directional components of a thermal conductivity of the second heat sink section is K2zz≧K2yy>K2xx or K2yy≧K2zz>K2xx, where the directional components of the thermal conductivity of the second heat sink section in X, Y, and X directions are determined as K2xx, K2yy, and K2zz.
摘要翻译：半导体器件包括具有矩形二维几何形状并用作热源的半导体元件，包括安装在其上的半导体元件的第一散热部分和与第一散热部分相对的一侧连接的第二散热部分其包括半导体元件。导热方向分量之间的关系为K1yy> = K1xx> K1zz，其中X，Y和Z方向上的散热器部分的三维热导率的方向分量被确定为Kxx，Kyy和Kzz。第二散热器部分的热导率的方向分量之间的关系是K2zz> = K2yy> K2xx或K2yy> = K2zz> K2xx，其中X，Y和Y中的第二散热器部分的热导率的方向分量 X方向确定为K2xx，K2yy和K2zz。

25. 发明申请

US20130037868A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130037868A1
公开(公告)日：2013-02-14
申请号：US13548078
申请日：2012-07-12
申请人： Yasuhiro Okamoto , Tatsuo Nakayama , Takashi Inoue , Hironobu Miyamoto
发明人： Yasuhiro Okamoto , Tatsuo Nakayama , Takashi Inoue , Hironobu Miyamoto
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/7787 , H01L21/02458 , H01L21/0254 , H01L29/2003 , H01L29/205 , H01L29/41775 , H01L29/4236 , H01L29/66462 , H01L29/7786
摘要： A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed over the first nitride semiconductor layer; and a gate electrode facing the second nitride semiconductor layer via a gate insulating film. Because the second nitride semiconductor layer is formed by stacking plural semiconductor layers with their Al composition ratios different from each other, the Al composition ratio of the second nitride semiconductor layer changes stepwise. The semiconductor layers forming the second nitride semiconductor layer are polarized in the same direction so that, among the semiconductor layers, a semiconductor layer nearer to the gate electrode has higher (or lower) intensity of polarization. In other words, the intensities of polarization of the semiconductor layers change with an inclination based on their distances from the gate electrode so that, at each interface between two semiconductor layers, the amount of negative charge becomes larger than that of positive charge.
摘要翻译：半导体器件包括：第一氮化物半导体层; 形成在第一氮化物半导体层上的第二氮化物半导体层; 以及经由栅极绝缘膜与第二氮化物半导体层相对的栅电极。由于第二氮化物半导体层通过堆叠其Al组成比彼此不同的多个半导体层而形成，所以第二氮化物半导体层的Al组成比逐步变化。形成第二氮化物半导体层的半导体层在相同的方向上极化，使得在半导体层中，更靠近栅电极的半导体层具有较高（或更低）的极化强度。换句话说，半导体层的极化强度随着与栅电极的距离的倾斜而变化，使得在两个半导体层之间的每个界面处，负电荷的量变得大于正电荷的量。

26. 发明申请

US20120217547A1 FIELD EFFECT TRANSISTOR WITH REDUCED GATE LEAKAGE CURRENT 有权
标题翻译：具有降低栅极泄漏电流的场效应晶体管
公开(公告)号：US20120217547A1
公开(公告)日：2012-08-30
申请号：US13468373
申请日：2012-05-10
申请人： Yuji ANDO , Hironobu MIYAMOTO , Tatsuo NAKAYAMA , Yasuhiro OKAMOTO , Takashi INOUE , Yasuhiro MURASE , Kazuki OTA , Akio WAKEJIMA , Naotaka KURODA
发明人： Yuji ANDO , Hironobu MIYAMOTO , Tatsuo NAKAYAMA , Yasuhiro OKAMOTO , Takashi INOUE , Yasuhiro MURASE , Kazuki OTA , Akio WAKEJIMA , Naotaka KURODA
IPC分类号： H01L29/778
CPC分类号： H01L29/7787 , H01L29/2003
摘要： Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0≦y≦1); a carrier supply layer 13 composed of AlxGa1-xN (0≦x≦1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x
摘要翻译：公开了一种HJFET 110，其包括：由In y Ga 1-y N（0＆lt; n 1; y＆n 1; 1）构成的沟道层12; 载体供给层13由Al x Ga 1-x N（0＆lt; n 1; x＆n 1; 1）组成，载流子供给层13设置在沟道层12上并且包括至少一个p型层; 以及源极电极15S，漏极电极15D和栅极电极17，其通过p型层面对沟道层12，并且设置在载流子供给层13上。满足以下关系式：5.6×10 11× NA×＆eegr×T [cm-2] <5.6×1013x，其中x表示所述载体供给层的Al组成比，t表示所述p型层的厚度，NA表示杂质浓度，＆eegr; 表示活化比。

27. 发明申请

US20120199889A1 SEMICONDUCTOR DEVICE AND FIELD EFFECT TRANSISTOR 有权
标题翻译：半导体器件和场效应晶体管
公开(公告)号：US20120199889A1
公开(公告)日：2012-08-09
申请号：US13393002
申请日：2010-06-23
申请人： Hironobu Miyamoto , Yasuhiro Okamoto , Yuji Ando , Tatsuo Nakayama , Takashi Inoue , Kazuki Ota , Kazuomi Endo
发明人： Hironobu Miyamoto , Yasuhiro Okamoto , Yuji Ando , Tatsuo Nakayama , Takashi Inoue , Kazuki Ota , Kazuomi Endo
IPC分类号： H01L29/78
CPC分类号： H01L29/8122 , H01L29/0657 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/7809 , H01L29/7812 , H01L29/7813 , H01L29/8128
摘要： Provided is a semiconductor device in which the trade-off between the withstand voltage and the on-resistance is improved and the performance is increased.A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21′, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25′, wherein the first n-type semiconductor layer 21′, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25′ are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21′ and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25′. A gate electrode 14 is arranged so as to fill an opening portion to be filled that extends from the third n-type semiconductor layer 25′ to the second n-type semiconductor layer 23, and the gate electrode 14 is in contact with the upper surface of the second n-type semiconductor layer 23, the side surfaces of the p-type semiconductor layer 24, and the side surfaces of the third n-type semiconductor layer 25′. The second n-type semiconductor layer 23 has composition that changes from the drain electrode 13 side toward the source electrode 12 side in the direction perpendicular to the plane of the substrate 1 and contains donor impurity.
摘要翻译：提供一种半导体器件，其中耐压和导通电阻之间的折衷被提高并且性能提高。半导体器件包括衬底1，第一n型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'，其中第一n型半导体层型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'依次层叠在基板1的上侧。漏电极13与第一n型半导体层21'欧姆接触，源电极12与第三n型半导体层25'欧姆接触。栅电极14被布置成填充从第三n型半导体层25'延伸到第二n型半导体层23的待填充的开口部分，并且栅电极14与上表面第二n型半导体层23，p型半导体层24的侧表面和第三n型半导体层25'的侧表面。第二n型半导体层23具有从垂直于基板1的平面的方向从漏电极13侧向源电极12侧变化的成分，并且含有施主杂质。

28. 发明授权

US08225058B2 Memory system managing a size of logs 有权
标题翻译：管理日志大小的内存系统
公开(公告)号：US08225058B2
公开(公告)日：2012-07-17
申请号：US12559983
申请日：2009-09-15
申请人： Hironobu Miyamoto , Hajime Yamazaki , Shinji Yonezawa
发明人： Hironobu Miyamoto , Hajime Yamazaki , Shinji Yonezawa
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F11/1471 , G06F2201/84 , G06F2212/7201
摘要： A memory system according to an embodiment of the present invention includes: a log overflow control unit configured, when a predetermined condition is satisfied, to prohibit a recording operation of a log and to cause a log recording unit only to perform an updating operation of a management table, and when a commit condition is satisfied after the predetermined condition has been satisfied, to prohibit a commit operation by a log reflecting unit and to cause a snapshot storing unit to perform a snapshot storing operation.
摘要翻译：根据本发明的实施例的存储器系统包括：日志溢出控制单元，当满足预定条件时，配置为禁止日志的记录操作，并且使日志记录单元仅执行日志记录单元的更新操作管理表，并且在满足预定条件之后满足提交条件时，禁止日志反射单元的提交操作，并使快照存储单元执行快照存储操作。

29. 发明授权

US08198652B2 Field effect transistor with reduced gate leakage current 有权
标题翻译：具有减小栅极漏电流的场效应晶体管
公开(公告)号：US08198652B2
公开(公告)日：2012-06-12
申请号：US12295004
申请日：2007-03-29
申请人： Yuji Ando , Hironobu Miyamoto , Tatsuo Nakayama , Yasuhiro Okamoto , Takashi Inoue , Yasuhiro Murase , Kazuki Ota , Akio Wakejima , Naotaka Kuroda
发明人： Yuji Ando , Hironobu Miyamoto , Tatsuo Nakayama , Yasuhiro Okamoto , Takashi Inoue , Yasuhiro Murase , Kazuki Ota , Akio Wakejima , Naotaka Kuroda
IPC分类号： H01L29/80
CPC分类号： H01L29/7787 , H01L29/2003
摘要： Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0≦y≦1); a carrier supply layer 13 composed of AlxGa1-xN (0≦x≦1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x
摘要翻译：公开了一种HJFET 110，其包括：由In y Ga 1-y N（0＆lt; n 1; y＆n 1; 1）构成的沟道层12; 载体供给层13由Al x Ga 1-x N（0＆lt; n 1; x＆n 1; 1）组成，载流子供给层13设置在沟道层12上并且包括至少一个p型层; 以及源极电极15S，漏极电极15D和栅极电极17，其通过p型层面对沟道层12，并且设置在载流子供给层13上。满足以下关系式：5.6×10 11× NA×＆eegr×T [cm-2] <5.6×1013x，其中x表示载流子供应层的Al组成比，t表示p型层的厚度，NA表示杂质浓度，＆eegr; 表示活化比。

30. 发明申请

US20110278586A1 BIPOLAR TRANSISTOR 有权
标题翻译：双极晶体管
公开(公告)号：US20110278586A1
公开(公告)日：2011-11-17
申请号：US13124873
申请日：2009-10-16
申请人： Yuji Ando , Hironobu Miyamoto , Tatsuo Nakayama , Yasuhiro Okamoto , Takashi Inoue , Kazuki Ota
发明人： Yuji Ando , Hironobu Miyamoto , Tatsuo Nakayama , Yasuhiro Okamoto , Takashi Inoue , Kazuki Ota
IPC分类号： H01L29/20
CPC分类号： H01L29/7371 , H01L29/0649 , H01L29/0817 , H01L29/0821 , H01L29/2003 , H01L29/205 , H01L29/475 , H01L29/66318
摘要： A bipolar transistor is provided with an emitter layer, a base layer and a collector layer. The emitter layer is formed above a substrate and is an n-type conductive layer including a first nitride semiconductor. The base layer is formed on the emitter layer and is a p-type conductive including a second nitride semiconductor. The collector layer is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed such that a crystal growth direction to the substrate surface is parallel to a substrate direction of [000-1]. The third nitride semiconductor contains InycAlxcGa1-xc-ycN (0•xc•1, 0•yc•1, 0
摘要翻译：双极晶体管设置有发射极层，基极层和集电极层。发射极层形成在衬底之上，并且是包括第一氮化物半导体的n型导电层。基极层形成在发射极层上，是包含第二氮化物半导体的p型导体。集电极层形成在基极层上并且包括第三氮化物半导体。形成集电体层，基极层和发射极层，使得到基板表面的晶体生长方向平行于[000-1]的基板方向。第三氮化物半导体含有InycAlxcGa1-xc-ycN（0·xc·1,0,0·yc·1,0,0cc·yc·1）。第三氮化物半导体中的表面侧的a轴长度比基板侧的a轴长短。

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