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    • 22. 发明授权
    • Systems and methods for on-the-fly write pre-compensation estimation
    • 用于即时写入预补偿估计的系统和方法
    • US07859780B2
    • 2010-12-28
    • US12199379
    • 2008-08-27
    • George MathewYuan Xing LeeHongwei Song
    • George MathewYuan Xing LeeHongwei Song
    • G11B5/09G11B5/02
    • G11B5/09G11B20/10194
    • Various embodiments of the present invention provide systems and methods for write pre-compensation. For example, various embodiments of the present invention provide systems for on-the-fly estimation of write pre-compensation values. Such systems include a magnetic storage medium, a read/write head assembly disposed in relation to the magnetic storage medium, and an analog to digital converter that receives an analog signal from the read/write head assembly corresponding to a data set stored on the magnetic storage medium and provides a series of digital samples corresponding to the data set. The storage devices further include a read data processing circuit that receives the same series of digital samples and provides a user data output, and a pre-compensation value calculation circuit that receives the series of digital samples and provides an updated write pre-compensation value.
    • 本发明的各种实施例提供了用于写入预补偿的系统和方法。 例如,本发明的各种实施例提供用于写入预补偿值的即时估计的系统。 这样的系统包括磁存储介质,相对于磁存储介质设置的读/写头组件和模数转换器,其从读/写头组件接收对应于存储在磁盘上的数据集的模拟信号 并提供与数据集相对应的一系列数字样本。 存储装置还包括读取数据处理电路,其接收相同系列的数字样本并提供用户数据输出,以及预补偿值计算电路,其接收一系列数字样本并提供更新的写入预补偿值。
    • 23. 发明申请
    • Systems and Methods for Storage Channel Testing
    • 存储通道测试的系统和方法
    • US20100265608A1
    • 2010-10-21
    • US12425757
    • 2009-04-17
    • Yuan Xing LeeGeorge MathewShaohua YangHongwel SongWeijun TanHao Zhong
    • Yuan Xing LeeGeorge MathewShaohua YangHongwel SongWeijun TanHao Zhong
    • G11B27/36
    • G11B20/182G11B2220/2516
    • Various embodiments of the present invention provide systems and methods for validating elements of storage devices. A an example, various embodiments of the present invention provide semiconductor devices that include a write path circuit, a read path circuit and a validation circuit. The write path circuit is operable to receive a data input and to convert the data input into write data suitable for storage to a storage medium. The read path circuit is operable to receive read data and to convert the read data into a data output. The validation circuit is operable to: receive the write data, augment the write data with a first noise sequence to yield a first augmented data series; and augment a derivative of the first augmented data series with a second noise sequence to yield the read data.
    • 本发明的各种实施例提供用于验证存储设备的元件的系统和方法。 作为示例,本发明的各种实施例提供包括写入路径电路,读取路径电路和验证电路的半导体器件。 写入路径电路可操作用于接收数据输入并将数据输入转换成适合于存储的写数据到存储介质。 读路径电路可操作以接收读数据并将读数据转换为数据输出。 验证电路可操作用于:接收写数据,用第一噪声序列增加写数据以产生第一增强数据序列; 并且用第二噪声序列来增加第一增强数据序列的导数以产生读取的数据。
    • 25. 发明申请
    • Systems and Methods for Memory Efficient Signal and Noise Estimation
    • 用于存储器高效信号和噪声估计的系统和方法
    • US20100088357A1
    • 2010-04-08
    • US12247378
    • 2008-10-08
    • George MathewYuan Xing LeeHongwei SongDavid L. ParkerScott M. Dziak
    • George MathewYuan Xing LeeHongwei SongDavid L. ParkerScott M. Dziak
    • G06F7/38G06F7/50G06F7/52
    • H04B17/327H04B17/26
    • Various embodiments of the present invention provide systems and methods for estimating signal and noise powers in a received signal set. For example, one embodiment of the present invention provides a method for determining signal power and noise power. The method uses a storage medium that includes a Na×Nw data pattern. The Na×Nw data pattern includes Na bits repeated Nw times. Both Na and Nw are each greater than one. The methods further include performing an initial read of the Na×Nw data pattern, which is stored to a first register. Nr subsequent reads of the Na×Nw data pattern are each processed by: performing a subsequent read of the Na×Nw data pattern, and performing a difference calculation using the initial read of the Na×Nw data pattern and the subsequent read of the Na×Nw data pattern and resulting in the calculation of a difference vector that is stored to a second register; and performing a difference accumulation calculation to generate an accumulation vector which is stored to a third register. Based at least in part on the stored Na×Nw data pattern and the stored difference vector, an electronics noise power is calculated.
    • 本发明的各种实施例提供了用于估计接收信号组中的信号和噪声功率的系统和方法。 例如,本发明的一个实施例提供了一种用于确定信号功率和噪声功率的方法。 该方法使用包括Na×Nw数据模式的存储介质。 Na×Nw数据模式包括重复N次的Na比特。 Na和Nw都大于1。 所述方法还包括执行存储到第一寄存器的Na×Nw数据模式的初始读取。 N×Nw数据模式的后续读取各自通过以下处理:执行Na×Nw数据模式的后续读取,并且使用Na×Nw数据模式的初始读取和随后的Na读数执行差分计算 ×Nw数据模式,并导致存储到第二寄存器的差矢量的计算; 以及执行差积累计算,以产生存储到第三寄存器的累加向量。 至少部分地基于存储的Na×Nw数据模式和存储的差分矢量,计算电子噪声功率。