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21. 发明申请

US20110227135A1 SCHOTTKY DIODES 有权
标题翻译：肖特基二极管
公开(公告)号：US20110227135A1
公开(公告)日：2011-09-22
申请号：US13150831
申请日：2011-06-01
申请人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L27/07 , H01L29/812 , H01L29/872
CPC分类号： H01L29/808 , H01L29/0619 , H01L29/66143 , H01L29/66901 , H01L29/806 , H01L29/872
摘要： Improved Schottky diodes with reduced leakage current and improved breakdown voltage are provided by building a JFET with its current path of a first conductivity type serially located between a first terminal comprising a Schottky contact and a second terminal. The current path lies (i) between multiple substantially parallel finger regions of a second, opposite, conductivity type substantially laterally outboard of the Schottky contact, and (ii) partly above a buried region of the second conductivity type that underlies a portion of the current path, which regions are electrically coupled to the first terminal and the Schottky contact and which portion is electrically coupled to the second terminal. When reverse bias is applied to the first terminal and Schottky contact, the current path is substantially pinched off in vertical or horizontal directions or both, thereby reducing the leakage current and improving the breakdown voltage of the device.
摘要翻译：通过以串联位于包括肖特基接触和第二端子的第一端子之间的第一导电类型的电流路径构建JFET来提供具有减小的漏电流和改善的击穿电压的改进的肖特基二极管。电流通路是（i）在肖特基接触的基本上横向外侧的第二相对导电类型的多个基本上平行的手指区域之间，以及（ii）部分地位于第二导电类型的掩埋区域之下，路径，哪些区域电耦合到第一端子和肖特基接触，哪个部分电耦合到第二端子。当对第一端子和肖特基触点施加反向偏压时，电流路径在垂直或水平方向或两者上基本上被夹断，从而减小漏电流并提高器件的击穿电压。

22. 发明授权

US09496333B2 Resurf high voltage diode 有权
公开(公告)号：US09496333B2
公开(公告)日：2016-11-15
申请号：US14622068
申请日：2015-02-13
申请人： Xin Lin , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
发明人： Xin Lin , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/66 , H01L29/06 , H01L29/739 , H01L29/861
CPC分类号： H01L29/063 , H01L29/0649 , H01L29/0692 , H01L29/66356 , H01L29/7391 , H01L29/861
摘要： A trench-isolated RESURF diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a buried cathode extension region (104) formed under a RESURF anode extension region (106, 107) such that the cathode extension region (104) extends beyond the cathode contact (131) to be sandwiched between upper and lower regions (103, 106, 107) of opposite conductivity type.

23. 发明授权

US09231083B2 High breakdown voltage LDMOS device 有权
标题翻译：高击穿电压LDMOS器件
公开(公告)号：US09231083B2
公开(公告)日：2016-01-05
申请号：US13537619
申请日：2012-06-29
申请人： Hongning Yang , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Hongning Yang , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L21/336 , H01L29/66 , H01L29/10 , H01L29/06
CPC分类号： H01L29/66689 , H01L21/76229 , H01L21/76264 , H01L29/0653 , H01L29/1083 , H01L29/66484 , H01L29/66772 , H01L29/7824
摘要： A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (LDMOS) device (40) has a semiconductor-on-insulator (SOI) support structure (21) on or over which are formed a substantially symmetrical, laterally internal, first LDMOS region (81) and a substantially asymmetric, laterally edge-proximate, second LDMOS region (83). A deep-trench isolation (DTI) wall (60) substantially laterally terminates the laterally edge-proximate second LDMOS region (83). Electric field enhancement and lower source-drain breakdown voltages (BVDSS) exhibited by the laterally edge-proximate second LDMOS region (83) associated with the DTI wall (60) are avoided by providing a doped SC buried layer region (86) in the SOI support structure (21) proximate the DTI wall (60), underlying a portion of the laterally edge-proximate second LDMOS region (83) and of opposite conductivity type than a drain region (31) of the laterally edge-proximate second LDMOS region (83).
摘要翻译：多区域（81,83）横向扩散金属氧化物半导体（LDMOS）器件（40）具有绝缘体上半导体（SOI）支撑结构（21），其上形成有基本上对称的横向内部的第一LDMOS区域（81）和基本不对称的横向边缘邻近的第二LDMOS区域（83）。深沟槽隔离（DTI）壁（60）基本上横向地终止横向边缘邻近的第二LDMOS区域（83）。通过在SOI中提供掺杂的SC掩埋层区域（86）来避免由与DTI壁（60）相关联的横向边缘邻近的第二LDMOS区域（83）表现出的电场增强和较低的源极 - 漏极击穿电压（BVDSS）靠近DTI壁（60）的支撑结构（21），位于横向边缘邻近的第二LDMOS区域（83）的一部分下方并且具有与横向边缘邻近的第二LDMOS区域的漏极区域（31）相反的导电类型 83）。

24. 发明授权

US09136327B1 Deep trench isolation structures and systems and methods including the same 有权
标题翻译：深沟槽隔离结构及其系统和方法包括相同
公开(公告)号：US09136327B1
公开(公告)日：2015-09-15
申请号：US14464901
申请日：2014-08-21
申请人： Xu Cheng , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Xu Cheng , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L21/336 , H01L29/06 , H01L29/36 , H01L21/762 , H01L21/8234 , H01L27/02
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/823481 , H01L27/0203 , H01L27/0207 , H01L29/36
摘要： Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. The semiconductor device includes a semiconductor body, a device region, and the deep trench isolation structure. The deep trench isolation structure is configured to electrically isolate the device region from other device regions that extend within the semiconductor body. The deep trench isolation structure includes an isolation trench, a dielectric material that extends within the isolation trench, a first semiconducting region, and a second semiconducting region. The methods include methods of manufacturing a semiconductor device that includes the disclosed deep trench isolation structures. The methods also include methods of operating an integrated circuit device that includes a plurality of semiconductor devices that include the disclosed deep trench isolation structures.
摘要翻译：深沟槽隔离结构及其系统和方法在此公开。该系统包括半导体器件。半导体器件包括半导体本体，器件区域和深沟槽隔离结构。深沟槽隔离结构被配置为将器件区域与在半导体本体内延伸的其它器件区域电隔离。深沟槽隔离结构包括隔离沟槽，在隔离沟槽内延伸的介电材料，第一半导体区域和第二半导体区域。该方法包括制造包括所公开的深沟槽隔离结构的半导体器件的方法。所述方法还包括操作集成电路器件的方法，所述集成电路器件包括包括所公开的深沟槽隔离结构的多个半导体器件。

25. 发明授权

US09136323B2 Drain-end drift diminution in semiconductor devices 有权
标题翻译：半导体器件的漏极漂移减少
公开(公告)号：US09136323B2
公开(公告)日：2015-09-15
申请号：US14486104
申请日：2014-09-15
申请人： Hongning Yang , Daniel J. Blomberg , Xu Cheng , Xin Lin , Won Gi Min , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Daniel J. Blomberg , Xu Cheng , Xin Lin , Won Gi Min , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/06 , H01L29/66 , H01L29/78 , H01L29/08 , H01L29/10
CPC分类号： H01L29/063 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： A method of fabricating a transistor includes forming a field isolation region in a substrate. After forming the field isolation region, dopant is implanted in a first region of a substrate for formation of a drift region. A drain region is formed in a second region of the substrate. The first and second regions laterally overlap to define a conduction path for the transistor. The first region does not extend laterally across the second region.
摘要翻译：制造晶体管的方法包括在衬底中形成场隔离区域。在形成场隔离区之后，将掺杂剂注入到用于形成漂移区的衬底的第一区域中。漏极区形成在衬底的第二区域中。第一和第二区域横向重叠以限定晶体管的导电路径。第一区域不横向跨越第二区域延伸。

26. 发明授权

US09099489B2 Bipolar transistor with high breakdown voltage 有权
标题翻译：具有高击穿电压的双极晶体管
公开(公告)号：US09099489B2
公开(公告)日：2015-08-04
申请号：US13545746
申请日：2012-07-10
申请人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L29/02 , H01L21/02 , H01L29/66 , H01L29/732 , H01L29/06 , H01L29/417 , H01L29/08
CPC分类号： H01L29/66272 , H01L29/0607 , H01L29/063 , H01L29/0808 , H01L29/0821 , H01L29/41708 , H01L29/732
摘要： A higher breakdown voltage transistor has separated emitter, base contact, and collector contact. Underlying the emitter and the base contact are, respectively, first and second base portions of a first conductivity type. Underlying and coupled to the collector contact is a collector region of a second, opposite, conductivity type, having a central portion extending laterally toward, underneath, or beyond the base contact and separated therefrom by the second base portion. A floating collector region of the same conductivity type as the collector region underlies and is separated from the emitter by the first base portion. The collector and floating collector regions are separated by a part of the semiconductor (SC) region in which the base is formed. A further part of the SC region in which the base is formed, laterally bounds or encloses the collector region.
摘要翻译：较高的击穿电压晶体管具有分离的发射极，基极接触和集电极接触。分别位于发射极和基极接触面之下的第一和第二基极部分是第一导电类型。底部并且耦合到集电极触点的是第二相对导电类型的集电极区域，其具有横向朝向，在下面或超过基部触点延伸并且由第二基部分离的中心部分。与集电极区域相同的导电类型的浮置集电极区域位于第一基底部分的下方并与发射极分离。集电极和集电极区域由形成有基极的半导体（SC）区域的一部分分开。 SC区域的另一部分，其中形成基底，横向界定或围绕收集器区域。

27. 发明申请

US20150104920A1 SEMICONDUCTOR DEVICE AND RELATED FABRICATION METHODS 有权
标题翻译：半导体器件及相关制造方法
公开(公告)号：US20150104920A1
公开(公告)日：2015-04-16
申请号：US14575204
申请日：2014-12-18
申请人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L29/66 , H01L21/265
CPC分类号： H01L29/6625 , H01L21/265 , H01L29/0649 , H01L29/36 , H01L29/66234 , H01L29/66272 , H01L29/73 , H01L29/732 , H01L29/735
摘要： Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a collector region of semiconductor material having a first conductivity type, a base region of semiconductor material within the collector region, the base region having a second conductivity type opposite the first conductivity type, and a doped region of semiconductor material having the second conductivity type, wherein the doped region is electrically connected to the base region and the collector region resides between the base region and the doped region. In exemplary embodiments, the dopant concentration of the doped region is greater than a dopant concentration of the collector region to deplete the collector region as the electrical potential of the base region exceeds that of the collector region.
摘要翻译：提供半导体器件结构和相关的制造方法。示例性的半导体器件结构包括具有第一导电类型的半导体材料的集电极区域，在集电极区域内的半导体材料的基极区域，具有与第一导电类型相反的第二导电类型的基极区域和半导体材料的掺杂区域具有第二导电类型，其中所述掺杂区域电连接到所述基极区域，并且所述集电极区域位于所述基极区域和所述掺杂区域之间。在示例性实施例中，掺杂区域的掺杂剂浓度大于集电极区域的掺杂剂浓度以消耗集电极区域，因为基极区域的电位超过集电极区域的电位。

28. 发明授权

US08946041B2 Methods for forming high gain tunable bipolar transistors 有权
标题翻译：用于形成高增益可调双极晶体管的方法
公开(公告)号：US08946041B2
公开(公告)日：2015-02-03
申请号：US13534971
申请日：2012-06-27
申请人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L21/331 , H01L29/66 , H01L29/08 , H01L29/10 , H01L29/732 , H01L21/8249 , H01L27/06
CPC分类号： H01L29/66272 , H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/1004 , H01L29/7322
摘要： Embodiments for forming improved bipolar transistors are provided, manufacturable by a CMOS IC process. The improved transistor comprises an emitter having first and second portions of different depths, a base underlying the emitter having a central portion of a first base width underlying the first portion of the emitter, a peripheral portion having a second base width larger than the first base width partly underlying the second portion of the emitter, and a transition zone of a third base width and lateral extent lying laterally between the first and second portions of the base, and a collector underlying the base. The gain of the transistor is larger than a conventional bipolar transistor made using the same CMOS process. By adjusting the lateral extent of the transition zone, the properties of the improved transistor can be tailored to suit different applications without modifying the underlying CMOS IC process.
摘要翻译：提供用于形成改进的双极晶体管的实施例，可通过CMOS IC工艺制造。改进的晶体管包括具有不同深度的第一和第二部分的发射器，发射器下面的基底具有位于发射器的第一部分下方的第一基底宽度的中心部分，具有大于第一基底的第二基底宽度的周边部分部分位于发射体的第二部分下方的宽度，以及位于基底的第一和第二部分之间横向置换的第三基底宽度和横向范围的过渡区，以及位于基底的收集器。晶体管的增益大于使用相同CMOS工艺制造的常规双极晶体管。通过调整过渡区域的横向范围，可以调整改进晶体管的性能以适应不同的应用，而无需修改底层的CMOS IC工艺。

29. 发明申请

US20150004768A1 DRAIN-END DRIFT DIMINUTION IN SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件中的引出端DRIFT分解
公开(公告)号：US20150004768A1
公开(公告)日：2015-01-01
申请号：US14486104
申请日：2014-09-15
申请人： Hongning Yang , Daniel J. Blomberg , Xu Cheng , Xin Lin , Won Gi Min , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Daniel J. Blomberg , Xu Cheng , Xin Lin , Won Gi Min , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/06 , H01L29/66 , H01L29/10
CPC分类号： H01L29/063 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： A method of fabricating a transistor includes forming a field isolation region in a substrate. After forming the field isolation region, dopant is implanted in a first region of a substrate for formation of a drift region. A drain region is formed in a second region of the substrate. The first and second regions laterally overlap to define a conduction path for the transistor. The first region does not extend laterally across the second region.
摘要翻译：制造晶体管的方法包括在衬底中形成场隔离区域。在形成场隔离区之后，将掺杂剂注入到用于形成漂移区的衬底的第一区域中。漏极区形成在衬底的第二区域中。第一和第二区域横向重叠以限定晶体管的导电路径。第一区域不横向跨越第二区域延伸。

30. 发明申请

US20140061858A1 Semiconductor Device with Diagonal Conduction Path 有权
标题翻译：具有对角导电路径的半导体器件
公开(公告)号：US20140061858A1
公开(公告)日：2014-03-06
申请号：US13605214
申请日：2012-09-06
申请人： Xin Lin , Daniel J. Blomberg , Jiangkai Zuo
发明人： Xin Lin , Daniel J. Blomberg , Jiangkai Zuo
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L29/73 , H01L21/2253 , H01L29/6625
摘要： A method of fabricating a bipolar transistor including emitter and base regions having first and second conductivity types, respectively, includes forming an isolation region at a surface of a semiconductor substrate, the isolation region having an edge that defines a boundary of an active area of the emitter region, and implanting dopant of the second conductivity type through a mask opening to form the base region in the semiconductor substrate. The mask opening spans the edge of the isolation region such that an extent to which the dopant passes through the isolation region varies laterally to establish a variable depth contour of the base region.
摘要翻译：包括分别具有第一和第二导电类型的发射极和基极区域的双极晶体管的制造方法包括在半导体衬底的表面形成隔离区域，该隔离区域具有界定边界的有源区域发射极区域和通过掩模开口注入第二导电类型的掺杂剂，以在半导体衬底中形成基极区域。掩模开口跨越隔离区域的边缘，使得掺杂剂通过隔离区域的程度横向变化，以建立基极区域的可变深度轮廓。

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