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21. 发明申请

US20070296650A1 Dual-Scan Circuit for Driving an OLED Display Device 有权
标题翻译：用于驱动OLED显示设备的双扫描电路
公开(公告)号：US20070296650A1
公开(公告)日：2007-12-27
申请号：US11425628
申请日：2006-06-21
申请人： Chin-Tien Chang
发明人： Chin-Tien Chang
IPC分类号： G09G3/30
CPC分类号： G09G3/3216 , G09G2310/0221 , G09G2310/0278
摘要： A luminescent display device is disclosed. The luminescent display device is comprised of an array of pixels, a first driving chip and a second driving chip. The array of pixels is comprised of columns and rows of pixels. The first driving chip is connected a first pixel of the array of pixels, and the second driving chip is connected to a second pixel of the array of pixels. The second pixel is adjacent to the first pixel. The first driving chip is not connected to all pixels in a row of the at least one row of pixels.
摘要翻译：公开了发光显示装置。发光显示装置由像素阵列，第一驱动芯片和第二驱动芯片构成。像素阵列由像素列和行组成。第一驱动芯片连接像素阵列的第一像素，第二驱动芯片连接到像素阵列的第二像素。第二像素与第一像素相邻。第一驱动芯片不连接到至少一行像素的一行中的所有像素。

22. 发明申请

US20070210998A1 Lighting emitting display, pixel circuit and driving method thereof 有权
标题翻译：照明发光显示器，像素电路及其驱动方法
公开(公告)号：US20070210998A1
公开(公告)日：2007-09-13
申请号：US11717104
申请日：2007-03-13
申请人： Yu-Wen Chiou , Chin-Tien Chang , Hong-Ru Guo
发明人： Yu-Wen Chiou , Chin-Tien Chang , Hong-Ru Guo
IPC分类号： G09G3/32
CPC分类号： G09G3/325 , G09G2300/0861 , G09G2310/0251 , G09G2310/0262 , G09G2320/043
摘要： A lighting emitting display, a pixel circuit and a driving method thereof. The pixel circuit includes a driving transistor, a capacitor and a LED. The capacitor receives a first supply voltage and is coupled to a gate of the driving transistor. A cathode of the LED receives a second supply voltage. During a pre-charge period, the gate and the drain of the driving transistor are coupled to an anode of the LED, the source of the driving transistor is coupled to a charging voltage. The source of the driving transistor receives a data signal and the drain and gate of the driving transistor are coupled to each other during a programming period. The source of the driving transistor is coupled to receive the first supply voltage and the drain of the driving transistor is coupled to the anode of the LED during a display period.
摘要翻译：发光显示器，像素电路及其驱动方法。像素电路包括驱动晶体管，电容器和LED。电容器接收第一电源电压并耦合到驱动晶体管的栅极。 LED的阴极接收第二电源电压。在预充电期间，驱动晶体管的栅极和漏极耦合到LED的阳极，驱动晶体管的源极耦合到充电电压。驱动晶体管的源极接收数据信号，并且驱动晶体管的漏极和栅极在编程周期期间彼此耦合。驱动晶体管的源极耦合以接收第一电源电压，并且驱动晶体管的漏极在显示周期期间耦合到LED的阳极。

23. 发明申请

US20070195018A1 Organic light emitting diode display and pixel circuit thereof 有权
标题翻译：有机发光二极管显示及其像素电路
公开(公告)号：US20070195018A1
公开(公告)日：2007-08-23
申请号：US11652536
申请日：2007-01-12
申请人： Yu-Wen Chiou , Chin-Tien Chang , Hong-Ru Guo
发明人： Yu-Wen Chiou , Chin-Tien Chang , Hong-Ru Guo
IPC分类号： G09G3/30
CPC分类号： G09G3/3241 , G09G2300/0819 , G09G2300/0842 , G09G2310/08
摘要： An OLED display and pixel circuit thereof are provided. The pixel circuit includes first and second switches, first and second PMOS transistors, a capacitor and an OLED. The first switch, controlled by a first scan signal, has a first end receiving a data signal and a second end. The second switch, controlled by a second scan signal, has a third end coupled to the second end and a fourth end. The first PMOS transistor has a source coupled to a high voltage, a drain coupled to the fourth end and a gate coupled to the second end. The second PMOS transistor has a gate coupled to the second end and a source coupled to the high voltage. The capacitor is coupled to the gate of the first PMOS transistor and the high voltage. The OLED has a positive end coupled to a drain of the second PMOS transistor.
摘要翻译：提供了OLED显示器及其像素电路。像素电路包括第一和第二开关，第一和第二PMOS晶体管，电容器和OLED。由第一扫描信号控制的第一开关具有接收数据信号的第一端和第二端。由第二扫描信号控制的第二开关具有联接到第二端和第四端的第三端。第一PMOS晶体管具有耦合到高电压的源极，耦合到第四端的漏极和耦合到第二端的栅极。第二PMOS晶体管具有耦合到第二端的栅极和耦合到高电压的源极。电容器耦合到第一PMOS晶体管的栅极和高电压。 OLED具有耦合到第二PMOS晶体管的漏极的正端。

24. 发明授权

US08363037B2 Reset circuit for power-on and power-off 有权
标题翻译：复位电路上电和关机
公开(公告)号：US08363037B2
公开(公告)日：2013-01-29
申请号：US11835268
申请日：2007-08-07
申请人： Ying Lieh Chen , Kai Lan Chuang , Tsung Yu Wu , Chien Ru Chen , Chin Tien Chang , Chuan Che Lee , Wen Teng Fan
发明人： Ying Lieh Chen , Kai Lan Chuang , Tsung Yu Wu , Chien Ru Chen , Chin Tien Chang , Chuan Che Lee , Wen Teng Fan
IPC分类号： G09G5/00
CPC分类号： G06F1/24 , H03K17/22
摘要： A circuit for resetting a display having at least one driver outputting a driving voltage through an output channel to a corresponding data line of a panel comprises a first switch and a second switch. The first switch is actuated by a control pulse to transfer a reset voltage to the data line of the panel. The second switch is actuated by the control pulse to electrically isolate the output channel of the driver from the data line of the panel, wherein the control pulse is asserted during transient periods resulting from power-on and power-off of the display.
摘要翻译：用于将具有至少一个驱动器的显示器复位的电路通过输出通道输出到面板的相应数据线，包括第一开关和第二开关。第一开关由控制脉冲启动，以将复位电压传送到面板的数据线。第二开关由控制脉冲启动，以将驱动器的输出通道与面板的数据线电隔离，其中控制脉冲在由显示器的通电和断电引起的瞬态期间被断言。

25. 发明申请

US20120050083A1 SOURCE DRIVER 有权
标题翻译：源驱动器
公开(公告)号：US20120050083A1
公开(公告)日：2012-03-01
申请号：US12873332
申请日：2010-09-01
申请人： Wei-Kai Tseng , Chin-Tien Chang
发明人： Wei-Kai Tseng , Chin-Tien Chang
IPC分类号： H03M1/66
CPC分类号： G09G3/20 , G09G2310/027
摘要： A source driver includes at least a channel, and the channel includes an N-type digital-to-analog converter (NDAC) and an operational amplifier. The NDAC is utilized for receiving input data and selecting one of a plurality of gamma voltages to generate output data according to the input data. The operational amplifier is coupled to the NDAC, and is utilized for amplifying at least the output data to generate an amplified output data. In addition, the channel does not include any P-type digital-to-analog converter.
摘要翻译：源极驱动器至少包括一个通道，并且该通道包括N型数模转换器（NDAC）和运算放大器。 NDAC用于接收输入数据并根据输入数据选择多个伽马电压之一以产生输出数据。运算放大器耦合到NDAC，并用于至少放大输出数据以产生放大的输出数据。此外，该通道不包括任何P型数模转换器。

26. 发明授权

US08009155B2 Output buffer of a source driver applied in a display 有权
标题翻译：显示屏中应用的源驱动程序的输出缓冲区
公开(公告)号：US08009155B2
公开(公告)日：2011-08-30
申请号：US12061255
申请日：2008-04-02
申请人： Ying-Lieh Chen , Chin-Tien Chang , Hsu-Yu Hsiao
发明人： Ying-Lieh Chen , Chin-Tien Chang , Hsu-Yu Hsiao
IPC分类号： G06F3/038 , G09G5/00
CPC分类号： G09G3/3688 , G09G2310/0291 , G09G2330/021
摘要： An output buffer and a controlling method are disclosed. The output buffer comprises an upper buffer and a lower buffer. In the controlling method, at first, a first voltage (V1) and a second voltage (V2) are applied on the upper buffer, and a third voltage (V3) and a fourth voltage (V4) are applied on the lower buffer, wherein V1>V2, V1>V4, V3>V2, and V3>V4. Then, the upper buffer is operated to output data to a plurality of pixels thereby operating the liquid crystals of the pixels over an upper supply range, wherein the upper supply range is from V1 to V2. Thereafter, the lower buffer is operated to output data to the pixels thereby operating the liquid crystals of the pixels over a lower supply range, wherein the lower supply range is from V3 to V4.
摘要翻译：公开了一种输出缓冲器和控制方法。输出缓冲器包括上缓冲器和下缓冲器。在控制方法中，首先，在上缓冲器上施加第一电压（V1）和第二电压（V2），在下缓冲器上施加第三电压（V3）和第四电压（V4），其中 V1> V2，V1> V4，V3> V2，V3> V4。然后，操作上缓冲器以将数据输出到多个像素，从而在上电源范围上操作像素的液晶，其中上电源范围为V1至V2。此后，操作下缓冲器以向像素输出数据，从而在较低的供给范围上操作像素的液晶，其中较低的供给范围为V3至V4。

27. 发明申请

US20110032240A1 BUFFERING CIRCUIT WITH REDUCED DYNAMIC POWER CONSUMPTION 有权
标题翻译：减少动态电力消耗电路
公开(公告)号：US20110032240A1
公开(公告)日：2011-02-10
申请号：US12536050
申请日：2009-08-05
申请人： Jia-Hui Wang , Chien-Hung Tsai , Ying-Lieh Chen , Chin-Tien Chang
发明人： Jia-Hui Wang , Chien-Hung Tsai , Ying-Lieh Chen , Chin-Tien Chang
IPC分类号： G09G5/00 , H03F3/16 , H03L5/00
CPC分类号： H03F3/3022 , G09G3/2092 , G09G2300/0426 , G09G2330/021 , G09G2360/18 , H03F1/0205
摘要： A buffering circuit with reduced power consumption is provided. The output buffering circuit includes first and second amplifier circuits. The first amplifier circuit includes a first input stage and a first output stage both coupled between a first power voltage and a second power voltage lower than the first power voltage, and an assistant discharging unit configured to provide a discharging current flowing from a first output node to a first intermediate power voltage during a discharging operation of the first amplifier circuit. The second amplifier circuit includes a second input stage and a second output stage both coupled between the first power voltage and the second power voltage, and an assistant charging unit configured to provide a charging current flowing from a second intermediate power voltage to a second output node during a charging operation of the second amplifier circuit. The first and second amplifier circuits can have reduced output voltage ranges and hence reduced total power consumption.
摘要翻译：提供了具有降低功耗的缓冲电路。输出缓冲电路包括第一和第二放大器电路。第一放大器电路包括耦合在第一电源电压和低于第一电源电压的第二电源电压之间的第一输入级和第一输出级，以及辅助放电单元，被配置为提供从第一输出节点在第一放大器电路的放电操作期间到第一中间电源电压。第二放大器电路包括耦合在第一电源电压和第二电源电压之间的第二输入级和第二输出级，以及辅助充电单元，被配置为提供从第二中间电源电压流向第二输出节点的充电电流在第二放大器电路的充电操作期间。第一和第二放大器电路可以具有降低的输出电压范围，从而降低总功耗。

28. 发明授权

US07642800B2 Wafer test system wherein period of high voltage stress test of one chip overlaps period of function test of other chip 有权
标题翻译：晶片测试系统，其中一个芯片的高压应力测试周期与其他芯片的功能测试周期重叠
公开(公告)号：US07642800B2
公开(公告)日：2010-01-05
申请号：US11848954
申请日：2007-08-31
申请人： Tzong-Yau Ku , Chien-Ru Chen , Chin-Tien Chang , Ying-Lieh Chen , Lin-Kai Bu
发明人： Tzong-Yau Ku , Chien-Ru Chen , Chin-Tien Chang , Ying-Lieh Chen , Lin-Kai Bu
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G01R31/2851 , G01R31/2831 , G01R31/2884
摘要： A wafer, a test system thereof, a test method thereof and a test device thereof are provided. The present invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.
摘要翻译：提供晶片，其测试系统，其测试方法和测试装置。本发明利用第一组探针在第一芯片上执行高压应力（HVS）测试，并利用第二组探针在第二芯片上执行功能测试，其中高压应力测试与功能测试的周期重叠，从而大大降低了晶片的测试时间。

29. 发明授权

US07609238B2 Dual-scan circuit for driving an OLED display device 有权
标题翻译：用于驱动OLED显示设备的双重扫描电路
公开(公告)号：US07609238B2
公开(公告)日：2009-10-27
申请号：US11425628
申请日：2006-06-21
申请人： Chin-Tien Chang
发明人： Chin-Tien Chang
IPC分类号： G09G3/32 , G09G3/30 , G09G3/28 , G09G3/36
CPC分类号： G09G3/3216 , G09G2310/0221 , G09G2310/0278
摘要： A luminescent display device is disclosed. The luminescent display device is comprised of an array of pixels, a first driving chip and a second driving chip. The array of pixels is comprised of columns and rows of pixels. The first driving chip is connected a first pixel of the array of pixels, and the second driving chip is connected to a second pixel of the array of pixels. The second pixel is adjacent to the first pixel. The first driving chip is not connected to all pixels in a row of the at least one row of pixels.
摘要翻译：公开了发光显示装置。发光显示装置由像素阵列，第一驱动芯片和第二驱动芯片构成。像素阵列由像素列和行组成。第一驱动芯片连接像素阵列的第一像素，第二驱动芯片连接到像素阵列的第二像素。第二像素与第一像素相邻。第一驱动芯片不连接到至少一行像素的一行中的所有像素。

30. 发明授权

US07474245B1 Digital-to-analog converter 失效
标题翻译：数模转换器
公开(公告)号：US07474245B1
公开(公告)日：2009-01-06
申请号：US11898538
申请日：2007-09-13
申请人： Hui-Min Wang , Chen-Song Yen , Chin-Tien Chang , Chuan-Che Lee
发明人： Hui-Min Wang , Chen-Song Yen , Chin-Tien Chang , Chuan-Che Lee
IPC分类号： H03M1/68
CPC分类号： H03M1/682 , H03M1/765
摘要： A digital-to-analog converter outputting an output analog voltage according to an N-bit digital signal is provided. The digital-to-analog converter includes a first and a second resistor strings, a first and a second select units. The first resistor string is connected between a first and a second power supply voltages to generate a first group of reference voltages. The first select unit selects two reference voltages out of the first group according to M most significant bits of the N-bit digital signal. The second resistor string is connected between the selected reference voltages to generate a second group of reference voltages between the selected reference voltages. The second select unit selects one reference voltage out of the second group as the output analog voltage according to the N-M least significant bits of the N-bit digital signal.
摘要翻译：提供了根据N位数字信号输出输出模拟电压的数模转换器。数模转换器包括第一和第二电阻串，第一和第二选择单元。第一电阻串连接在第一和第二电源电压之间以产生第一组参考电压。第一选择单元根据N位数字信号的M个最高有效位选择第一组中的两个参考电压。第二电阻串连接在所选择的参考电压之间，以在所选参考电压之间产生第二组参考电压。第二选择单元根据N位数字信号的N-M个最低有效位选择第二组中的一个参考电压作为输出模拟电压。

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