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21. 发明申请

US20050020018A1 Method of manufacturing a semiconductor integrated circuit device 有权
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US20050020018A1
公开(公告)日：2005-01-27
申请号：US10917294
申请日：2004-08-13
申请人： Dai Ishikawa , Satoshi Sakai , Atsushi Hiraiwa
发明人： Dai Ishikawa , Satoshi Sakai , Atsushi Hiraiwa
IPC分类号： H01L27/04 , H01L21/28 , H01L21/314 , H01L21/822 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/51 , H01L29/78 , H01L21/4763 , H01L21/336 , H01L21/31 , H01L21/3205 , H01L21/469
CPC分类号： H01L21/28185 , H01L21/0214 , H01L21/02332 , H01L21/28202 , H01L21/3143 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L27/1052 , H01L27/10814 , H01L27/10888 , H01L27/10894 , H01L29/513 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： A method of manufacturing a semiconductor integrated circuit device comprising forming a silicon oxide film as thin as 5 nm or less on the surfaces of p type wells and n type wells by wet oxidizing a substrate, heating the substrate in an atmosphere containing about 5% of an NO gas to introduce nitrogen into the silicon oxide film so as to form a silicon oxynitride film, exposing the substrate to a nitrogen plasma atmosphere to further introduce nitrogen into the silicon oxynitride film in order to form a silicon oxynitride gate insulating film having a first peak concentration near the interface with the substrate and a second peak concentration near the surface thereof. Thereby, the concentration of nitrogen in the gate insulating film is increased without raising the concentration of nitrogen near the interface between the substrate and the gate insulating film to a higher level than required.
摘要翻译：一种制造半导体集成电路器件的方法，包括在p型阱和n型阱的表面上通过湿式氧化衬底形成薄至5nm或更小的氧化硅膜，在含有约5％用于将氮气引入到氧化硅膜中以形成氧氮化硅膜的NO气体，将衬底暴露于氮等离子体气氛中，以进一步将氮气引入氮氧化硅膜中，以形成具有第一个氮氧化物的氮氧化硅栅极绝缘膜与基板的界面附近的峰值浓度和其表面附近的第二峰值浓度。由此，不会使衬底与栅极绝缘膜的界面附近的氮浓度提高到高于所需的水平，所以栅极绝缘膜的氮浓度增加。

22. 发明授权

US5930624A Method of producing semiconductor integrated circuit device having switching MISFET and capacitor element including wiring 失效
标题翻译：具有开关MISFET和包括布线的电容元件的半导体集成电路器件的制造方法
公开(公告)号：US5930624A
公开(公告)日：1999-07-27
申请号：US13605
申请日：1998-01-26
申请人： Jun Murata , Yoshitaka Tadaki , Isamu Asano , Mitsuaki Horiuchi , Jun Sugiura , Hiroko Kaneko , Shinji Shimizu , Atsushi Hiraiwa , Hidetsugu Ogishi , Masakazu Sagawa , Masami Ozawa , Toshihiro Sekiguchi
发明人： Jun Murata , Yoshitaka Tadaki , Isamu Asano , Mitsuaki Horiuchi , Jun Sugiura , Hiroko Kaneko , Shinji Shimizu , Atsushi Hiraiwa , Hidetsugu Ogishi , Masakazu Sagawa , Masami Ozawa , Toshihiro Sekiguchi
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/105 , H01L27/108
CPC分类号： H01L27/105 , H01L27/10808
摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. In a first aspect, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In other aspects, a Y-select signal line overlaps the lower electrode layer of the capacitor element; a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region; the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it, the capacitor dielectric film being a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure; an aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; and a refractory metal, or a refractory metal silicide, is used as the protective layer for an aluminum wiring containing an added element (e.g., Cu) to prevent migration.
摘要翻译：公开了一种具有开关MISFET的半导体集成电路器件和形成在半导体衬底上的电容器元件。在第一方面中，电容器元件连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。在其他方面，Y选择信号线与电容器元件的下电极层重叠; 至少在与电容器元件连接的开关MISFET的半导体区域下方设置的势垒层通过用于沟道阻挡区域的杂质的扩散而形成; 电容器元件的电介质膜与其上的电容器电极层共同扩展，电容器电介质膜是其上具有氧化硅层的氮化硅膜，氧化硅层通过氧化氮化硅的表面层而形成在高压下通过溅射在相同的真空溅射室中形成铝布线层和保护（和/或阻挡层），而不破坏形成层之间的真空; 和难熔金属或难熔金属硅化物用作用于包含添加元素（例如Cu）以防止迁移的铝布线的保护层。

23. 发明授权

US5523058A Ultrasonic irradiation apparatus and processing apparatus based thereon 失效
标题翻译：超声波照射装置及其处理装置
公开(公告)号：US5523058A
公开(公告)日：1996-06-04
申请号：US240733
申请日：1994-05-12
申请人： Shinichiro Umemura , Kenichi Kawabata , Kenko Uchida , Kenji Yasuda , Yasuo Wada , Atsushi Hiraiwa
发明人： Shinichiro Umemura , Kenichi Kawabata , Kenko Uchida , Kenji Yasuda , Yasuo Wada , Atsushi Hiraiwa
IPC分类号： A61B17/22 , A61N7/00 , A61N7/02 , B01F11/02 , A61B8/00 , B06B1/00
CPC分类号： A61N7/02 , A61B17/22004 , A61N2007/006 , A61N2007/0078 , A61N2007/0095
摘要： By providing an ultrasonic irradiation apparatus for generating acoustic cavitation efficiently, it is intended to realize an ultrasonic therapeutic apparatus for generating the action of cavitation on a living body suitable for medical treatment of malignant tumors and medical treatment of thrombi and calculi, an ultrasonic diagnostic apparatus for generating cavitation for emphasizing an ultrasonic echo image such as a blood flow and utilizing the reflection capability of the cavitation, an ultrasonic chemical reaction accelerating apparatus, an ultrasonic cleaning apparatus or an ultrasonic sterilizing apparatus. Irradiation focus/code signals for defining irradiated acoustic fields of a fundamental wave and a second harmonic wave as well as focus positions/acoustic pressure distribution forms of the respective waves are applied from an irradiation unit main control circuit to drive phase generating circuits. Generated drive phases are applied to drive signal generating circuits, generated drive signals are applied to element drive circuits and a group of fundamental frequency elements and a group of second harmonic elements are driven. The drive phases are controlled such that the fundamental wave and second harmonic wave are superimposed on each other in a medium near a focal point, thus generating acoustic caviation locally and efficiently.
摘要翻译： PCT No.PCT / JP93 / 01310 Sec。 371日期：1994年5月12日 102（e）日期1994年5月12日PCT提交1993年9月14日PCT公布。公开号WO94 / 06380 日期为1994年3月31日。通过提供用于有效产生声孔的超声波照射装置，旨在实现用于产生适于恶性肿瘤治疗的生物体上的空化作用的超声波治疗装置和血栓的治疗和结石，用于产生用于强调超声波回波图像如血流并利用空化反射能力的超声波诊断装置，超声波化学反应加速装置，超声波清洗装置或超声波消毒装置。用于定义基波和二次谐波的辐射声场以及各波的聚焦位置/声压分布形式的照射焦点/码信号从照射单元主控制电路施加到驱动相位产生电路。产生的驱动相位被施加到驱动信号发生电路，所产生的驱动信号被施加到元件驱动电路，并且一组基频元件和一组二次谐波元件被驱动。控制驱动相位使得基波和二次谐波在焦点附近的介质中彼此叠加，从而局部且有效地产生声空化。

24. 发明授权

US5426326A Semiconductor device including arrangement for reducing junction degradation 失效
标题翻译：半导体器件包括用于减少结退化的装置
公开(公告)号：US5426326A
公开(公告)日：1995-06-20
申请号：US103206
申请日：1993-08-09
申请人： Kiyonori Ohyu , Kozo Watanabe , Osamu Tsuchiya , Kazuyoshi Oshima , Yoshifumi Kawamoto , Atsushi Hiraiwa , Takashi Nishida
发明人： Kiyonori Ohyu , Kozo Watanabe , Osamu Tsuchiya , Kazuyoshi Oshima , Yoshifumi Kawamoto , Atsushi Hiraiwa , Takashi Nishida
IPC分类号： H01L27/10 , H01L29/08 , H01L29/36 , H01L29/78 , H01L29/165
CPC分类号： H01L29/0847 , H01L29/08 , H01L29/36
摘要： An arrangement is provided to decrease the junction degradation caused by the leakage current at a p-n junction in semiconductor devices. This arrangement can be useful for a variety of devices, and is especially effective for reducing junction degradation at the source or drain region of a MOSFET. To achieve such a reduction, a p-n junction layer is provided at a p-n junction of a semiconductor region and a substrate. Carrier concentration distributions of a p-type layer and an n-type layer of the p-n junction layer are set so that an electric field which tends to be increased by a local electric field enhancement in a depletion layer of the p-n junction due to a precipitate introduced from a semiconductor surface will not exceed 1 MV/cm. When the depth of a depletion layer of the p-type layer or the n-type layer is referred to as Xp or Xn, and the slope of the carrier concentration, Ap or An, the following relation is provided:4.3.times.10.sup.12 (/cm.sup.2).gtoreq.An.multidot.Xn.sup.2 =Ap.multidot.Xp.sup.2Preferably, the p-n junction layer is formed under a contact hole of a source or drain region if the device in question is a MOSFET. As a result of using this arrangement, the leakage current caused by a local Zener effect decreases so that the electric field locally increased by the precipitate will not be greater than 1 MV/cm.
摘要翻译：提供了一种布置，以减少由半导体器件中的p-n结处的漏电流引起的结劣化。这种布置对于各种器件可能是有用的，并且对于降低MOSFET的源极或漏极区域处的结退化特别有效。为了实现这种减少，在半导体区域和衬底的p-n结处提供p-n结层。 pn结层的p型层和n型层的载流子浓度分布被设定为使得由于沉淀引起的在pn结的耗尽层中的局部电场增强倾向于增加的电场从半导体表面引入的电流不超过1MV / cm。当p型层或n型层的耗尽层的深度被称为Xp或Xn以及载流子浓度Ap或An的斜率时，提供以下关系：4.3×10 12（/ cm 2））> / = AnxXn2 = ApxXp2如果所讨论的器件是MOSFET，则优选地，在源极或漏极区域的接触孔下方形成pn结层。作为使用这种布置的结果，由局部齐纳效应引起的漏电流减小，使得由沉淀物局部增加的电场将不会大于1MV / cm。

25. 发明申请

US20110266631A1 SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20110266631A1
公开(公告)日：2011-11-03
申请号：US13179163
申请日：2011-07-08
申请人： Naozumi MORINO , Atsushi HIRAIWA , Kazutoshi OKU , Toshiaki ITO , Motoshige IGARASHI , Takayuki SASAKI , Masao SUGIYAMA , Hiroshi YANAGITA , Shinichi WATARAI
发明人： Naozumi MORINO , Atsushi HIRAIWA , Kazutoshi OKU , Toshiaki ITO , Motoshige IGARASHI , Takayuki SASAKI , Masao SUGIYAMA , Hiroshi YANAGITA , Shinichi WATARAI
IPC分类号： H01L27/092
CPC分类号： H01L21/823892 , H01L27/0629 , H01L27/0928 , H01L2224/05554
摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

26. 发明授权

US07662696B2 Method for fabricating semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07662696B2
公开(公告)日：2010-02-16
申请号：US11690521
申请日：2007-03-23
申请人： Atsushi Hiraiwa , Satoshi Sakai , Dai Ishikawa , Yoshihiro Ikeda
发明人： Atsushi Hiraiwa , Satoshi Sakai , Dai Ishikawa , Yoshihiro Ikeda
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28273 , H01L21/3105 , H01L21/823857 , H01L27/105 , H01L27/11521 , H01L27/11526 , H01L29/513 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： According to the present invention, an oxide film with the film quality almost equivalent to that of the thermal oxide can be formed by the low-temperature treatment. After removing an insulator on the active region of the substrate which constitutes a semiconductor wafer, an insulator made of, for example, silicon oxide is deposited on the main surface of the semiconductor wafer by the low pressure CVD method. This insulator is a film to form a gate insulator of MISFET in a later step. Subsequently, a plasma treatment is performed in an atmosphere containing oxygen (oxygen plasma treatment) to the insulator in the manner as schematically shown by the arrows. By so doing, the film quality of the insulator formed by the CVD method can be improved to the extent almost equivalent to that of the insulator formed of the thermal oxide.
摘要翻译：根据本发明，可以通过低温处理形成膜质量几乎等于热氧化物的氧化膜。在构成半导体晶片的基板的有源区域上去除绝缘体之后，通过低压CVD法在半导体晶片的主表面上沉积由例如氧化硅制成的绝缘体。该绝缘体是在后续步骤中形成MISFET的栅极绝缘体的膜。随后，按照箭头示意性地示出的方式，在含有氧的气氛（氧等离子体处理）中对绝缘体进行等离子体处理。通过这样做，通过CVD方法形成的绝缘体的膜质量可以提高到与由热氧化物形成的绝缘体几乎相同的程度。

27. 发明申请

US20090273037A1 Semiconductor Integrated Circuit Device and Manufacturing Method Thereof 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20090273037A1
公开(公告)日：2009-11-05
申请号：US12486944
申请日：2009-06-18
申请人： Satoshi SAKAI , Atsushi HIRAIWA , Satoshi YAMAMOTO
发明人： Satoshi SAKAI , Atsushi HIRAIWA , Satoshi YAMAMOTO
IPC分类号： H01L27/088
CPC分类号： H01L21/823462 , H01L21/82345 , H01L21/823842 , H01L21/823857 , H01L21/823878
摘要： After silicon oxide film (9) is formed on the surface of a semiconductor substrate (1), the silicon oxide film (9) in a region in which a gate insulation film having a small effective thickness is formed is removed using diluted HF and after that, high dielectric constant insulation film (10) is formed on the semiconductor substrate (1). Consequently, two kinds of gate insulation films, namely, a gate insulation film (12) comprised of stacked film of high dielectric constant insulation film (10) and silicon oxide film (9) and gate insulation film (11) comprised of the high dielectric constant insulation film (10) are formed on the semiconductor substrate (1).
摘要翻译：在半导体基板（1）的表面上形成氧化硅膜（9）之后，使用稀释的HF除去形成有效厚度小的栅极绝缘膜的区域中的氧化硅膜（9）在半导体衬底（1）上形成高介电常数绝缘膜（10）。因此，由高介电常数绝缘膜（10）和氧化硅膜（9）构成的栅极绝缘膜（12）和栅极绝缘膜（12）构成的两种栅极绝缘膜由高介电常数在半导体衬底（1）上形成恒定绝缘膜（10）。

28. 发明申请

US20090179247A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20090179247A1
公开(公告)日：2009-07-16
申请号：US12354254
申请日：2009-01-15
申请人： Masako FUJII , Shigeki Obayashi , Naozumi Morino , Atsushi Hiraiwa , Shinichi Watarai , Takeshi Yoshida , Kazutoshi Oku , Masao Sugiyama , Yoshinori Kondo , Yuichi Egawa , Yoshiyuki Kaneko
发明人： Masako FUJII , Shigeki Obayashi , Naozumi Morino , Atsushi Hiraiwa , Shinichi Watarai , Takeshi Yoshida , Kazutoshi Oku , Masao Sugiyama , Yoshinori Kondo , Yuichi Egawa , Yoshiyuki Kaneko
IPC分类号： H01L27/06 , H01L29/78
CPC分类号： H01L21/823892 , H01L27/092
摘要： A technique which can improve manufacturing yield and product reliability is provided in a semiconductor device having a triple well structure. An inverter circuit which includes an n-channel type field effect transistor formed in a shallow p-type well and a p-channel type field effect transistor formed in a shallow n-type well, and does not contribute to circuit operations is provided in a deep n-type well formed in a p-type substrate; the shallow p-type well is connected to the substrate using a wiring of a first layer; and the gate electrode of the p-channel type field effect transistor and the gate electrode of the n-channel type field effect transistor are connected to the shallow n-type well using a wiring of an uppermost layer.
摘要翻译：在具有三重阱结构的半导体器件中提供了可以提高制造成品率和产品可靠性的技术。形成在浅p型阱中的n沟道型场效应晶体管和形成在浅n型阱中的p沟道型场效应晶体管并且对电路操作无贡献的逆变器电路设置在在p型衬底中形成深n型阱; 使用第一层的布线将浅的p型阱连接到基板; 并且p沟道型场效应晶体管的栅电极和n沟道型场效应晶体管的栅电极使用最上层的布线连接到浅n型阱。

29. 发明申请

US20070190744A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICES 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20070190744A1
公开(公告)日：2007-08-16
申请号：US11690521
申请日：2007-03-23
申请人： Atsushi Hiraiwa , Satoshi Sakai , Dai Ishikawa , Yoshihiro Ikeda
发明人： Atsushi Hiraiwa , Satoshi Sakai , Dai Ishikawa , Yoshihiro Ikeda
IPC分类号： H01L21/76
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28273 , H01L21/3105 , H01L21/823857 , H01L27/105 , H01L27/11521 , H01L27/11526 , H01L29/513 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： According to the present invention, an oxide film with the film quality almost equivalent to that of the thermal oxide can be formed by the low-temperature treatment. After removing an insulator on the active region of the substrate which constitutes a semiconductor wafer, an insulator made of, for example, silicon oxide is deposited on the main surface of the semiconductor wafer by the low pressure CVD method. This insulator is a film to form a gate insulator of MISFET in a later step. Subsequently, a plasma treatment is performed in an atmosphere containing oxygen (oxygen plasma treatment) to the insulator in the manner as schematically shown by the arrows. By so doing, the film quality of the insulator formed by the CVD method can be improved to the extent almost equivalent to that of the insulator formed of the thermal oxide.
摘要翻译：根据本发明，可以通过低温处理形成膜质量几乎等于热氧化物的氧化膜。在构成半导体晶片的基板的有源区域上去除绝缘体之后，通过低压CVD法在半导体晶片的主表面上沉积由例如氧化硅制成的绝缘体。该绝缘体是在后续步骤中形成MISFET的栅极绝缘体的膜。随后，按照箭头示意性地示出的方式，在含有氧的气氛（氧等离子体处理）中对绝缘体进行等离子体处理。通过这样做，通过CVD方法形成的绝缘体的膜质量可以提高到与由热氧化物形成的绝缘体几乎相同的程度。

30. 发明授权

US07186604B2 Semiconductor integrated circuit device and method for fabricating the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US07186604B2
公开(公告)日：2007-03-06
申请号：US10519799
申请日：2002-08-15
申请人： Satoshi Sakai , Satoshi Yamamoto , Atsushi Hiraiwa , Ryoichi Furukawa
发明人： Satoshi Sakai , Satoshi Yamamoto , Atsushi Hiraiwa , Ryoichi Furukawa
IPC分类号： H01L21/8238
CPC分类号： H01L29/513 , H01L21/823857
摘要： After forming a silicon oxide film 9 on the surface of a region A of a semiconductor substrate 1, a high dielectric constant insulating film 10, a silicon film, a silicon oxide film 14 are successively deposited over the semiconductor substrate 1, and they are patterned to leave the silicon oxide film 14 in regions for forming gate electrodes. Then, after fabricating silicon films 13n and 13p by using the patterned silicon oxide film 14 as a mask, when removing the silicon oxide film 14, etching is performed under the condition where the etching selectivity of the silicon oxide film 14 to the high dielectric constant insulating film 10 becomes large, thereby leaving the high dielectric constant insulating film 10 also to portions below the end of the gate electrodes (13n, 13p). Thus, it is possible to ensure the voltage withstanding thereof and improve the characteristics of MISFET.
摘要翻译：在半导体衬底1的区域A的表面上形成氧化硅膜9之后，在半导体衬底1上依次沉积高介电常数绝缘膜10，硅膜，氧化硅膜14，并将其图案化以将氧化硅膜14留在用于形成栅电极的区域中。然后，通过使用图案化氧化硅膜14作为掩模来制造硅膜13 n和13 p之后，当去除氧化硅膜14时，在氧化硅膜14的蚀刻选择性高的条件下进行蚀刻介电常数绝缘膜10变大，从而将高介电常数绝缘膜10也留在栅电极（13n，13p）的端部下方的部分。因此，可以确保其耐受电压并改善MISFET的特性。

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