专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US6100715A Methods for configuring FPGA's having variable grain blocks and logic for providing time-shared access to interconnect resources 有权
标题翻译：用于配置具有可变粒度块的FPGA的方法和用于提供对互连资源的时间共享访问的逻辑
公开(公告)号：US6100715A
公开(公告)日：2000-08-08
申请号：US212330
申请日：1998-12-15
申请人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Herman M. Chang , Bai Nguyen , Giap H. Tran
发明人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Herman M. Chang , Bai Nguyen , Giap H. Tran
IPC分类号： H03K19/173 , H03K19/177 , A03K19/177
CPC分类号： H03K19/17748 , H03K19/1737 , H03K19/17736 , H03K19/1778
摘要： A Variable Grain Architecture (VGA) includes a shared output component (SOC) that may be used for outputting different signals onto a shared longline within an FPGA. Plural VGB's make shared use of the SOC to out respective function signals to the shared longline.
摘要翻译：可变晶体结构（VGA）包括可用于将不同信号输出到FPGA内的共享长线上的共享输出组件（SOC）。多个VGB将共享的SOC用于将相应的功能信号分配给共享的延长线。

22. 发明授权

US6028789A Zero-power CMOS non-volatile memory cell having an avalanche injection element 有权
标题翻译：具有雪崩注入元件的零功率CMOS非易失性存储单元
公开(公告)号：US6028789A
公开(公告)日：2000-02-22
申请号：US334051
申请日：1999-06-15
申请人： Sunil D. Mehta , Brad Sharpe-Geisler , Steven Fong
发明人： Sunil D. Mehta , Brad Sharpe-Geisler , Steven Fong
IPC分类号： G11C16/04 , G11C16/10 , G11C16/26
CPC分类号： G11C16/045 , G11C16/0441 , G11C16/10 , G11C16/26 , G11C2216/10
摘要： A zero-power non-volatile memory cell includes a control element, an avalanche injection element, and a CMOS inverter. A floating-gate electrode is capacitively coupled to the control element, the avalanche injection element, and to the CMOS inverter. The avalanche injection element is arranged, so as to transfer electrical charge onto the floating-gate electrode. The presence of stored data within the memory cell is indicated by reading a supply voltage V.sub.DD at an output terminal of the inverter. Accordingly, data can be read from the non-volatile memory cell without applying electrical power to the cell.
摘要翻译：零功率非易失性存储单元包括控制元件，雪崩注入元件和CMOS反相器。浮栅电极电容耦合到控制元件，雪崩注入元件和CMOS反相器。布置雪崩注入元件，以将电荷转移到浮栅电极上。通过读取逆变器输出端的电源电压VDD来指示存储单元内的存储数据的存在。因此，可以从非易失性存储单元读取数据，而不向单元施加电力。

23. 发明授权

US5999449A Two transistor EEPROM cell using P-well for tunneling across a channel 失效
标题翻译：使用P阱的两个晶体管EEPROM单元用于跨通道的隧道
公开(公告)号：US5999449A
公开(公告)日：1999-12-07
申请号：US239072
申请日：1999-01-27
申请人： Sunil D. Mehta , Xiao-Yu Li
发明人： Sunil D. Mehta , Xiao-Yu Li
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/0441
摘要： A two transistor EEPROM cell is described that is programmed and erased by electron tunneling across a tunneling channel in a P-well. The EEPROM cell has two transistors formed in a semiconductor substrate. The two transistors are a tunneling transistor (NMOS) and a read transistor (NMOS). Electron tunneling occurs to program and erase the EEPROM cell through a tunnel oxide layer by electron tunneling across an entire portion of a tunneling channel upon incurrence of a sufficient voltage potential between a floating gate and the tunnel channel
摘要翻译：描述了通过P阱中的隧道通道的电子隧道编程和擦除的两个晶体管EEPROM单元。 EEPROM单元具有形成在半导体衬底中的两个晶体管。两个晶体管是隧道晶体管（NMOS）和读取晶体管（NMOS）。发生电子隧穿，以在浮动栅极和隧道通道之间发生足够的电压电势时通过隧道氧化物层通过电子隧穿跨越隧道通道的整个部分来编程和擦除EEPROM单元

24. 发明授权

US5982193A Input/output block (IOB) connections to MaxL lines, nor lines and dendrites in FPGA integrated circuits 失效
标题翻译：输入/输出块（IOB）连接到MaxL线路，不包括FPGA集成电路中的线路和树突
公开(公告)号：US5982193A
公开(公告)日：1999-11-09
申请号：US995614
申请日：1997-12-22
申请人： Om P. Agrawal , Bradley A. Sharpe-Geisler , John D. Tobey , Giap H. Tran
发明人： Om P. Agrawal , Bradley A. Sharpe-Geisler , John D. Tobey , Giap H. Tran
IPC分类号： H03K19/177
CPC分类号： H03K19/17744
摘要： A Field Programmable Gate Array (FPGA) device includes a plurality of input/output blocks (IOBs) and variable grain blocks (VGBs). An inter-connect network provides routing of signals between the IOBs and VGBs. The VGBs include a plurality of L-organized CBBs (configurable logic blocks) having function-producing resources. The IOBs are arranged along a top, left, bottom and right side of the plurality of VGBs. An IOB includes a 1) delay for timing input signals, 2) a configurable output latch which may be set or reset responsive to control signals, and 3) transistor for controlling a NOR line. The IOB is programmably configured to the inter-connect network which includes vertical and horizontal inter-connect channels comprising adjacent inter-connect lines. The IOB inputs are connected to adjacent inter-connect lines including 1) direct connect input lines from adjacent super-VGBs, 2) MaxL lines, and 3) dendrite lines from adjacent dendrites. The IOB outputs are connected to 1) MaxL lines, 2) dendrite lines in adjacent dendrites, 3) NOR lines, and 4) direct connect output lines to adjacent super-VGBs. Dendrites for routing signals along the periphery of the plurality of VGBs are positioned between the IOBs and super-VGBs. Dendrites include a plurality of I/O switchboxes and dendrite lines. The I/O switchboxes are coupled to vertical and horizontal inter-connect channels. The inter-connect network includes a direct connect architecture between IOBs and adjacent super-VGBs. Dedicated connections between corner and non-corner IOBs provide direct connect inputs and outputs to and from CBBs in a super-VGB.
摘要翻译：现场可编程门阵列（FPGA）装置包括多个输入/输出块（IOB）和可变粒子块（VGB）。互连网络提供IOB和VGB之间的信号路由。 VGB包括具有功能生成资源的多个L组织CBB（可配置逻辑块）。 IOB沿着多个VGB的顶部，左侧，底部和右侧布置。 IOB包括1）用于定时输入信号的延迟，2）响应于控制信号可以被设置或复位的可配置输出锁存器，以及3）用于控制NOR线路的晶体管。 IOB可编程地配置到包括相邻连接线之间的垂直和水平互连通道的互连网络。 IOB输入连接到相邻的互连线，包括1）直接连接相邻超VGB的输入线，2）MaxL线，以及3）相邻枝晶的枝晶线。 IOB输出连接到1）MaxL线，2）相邻枝晶中的枝晶线，3）NOR线，以及4）将输出线直接连接到相邻的超VGB。沿着多个VGB的周边路由信号的树枝状晶体位于IOB和超级VGB之间。树枝包括多个I / O开关盒和枝晶线。 I / O开关盒耦合到垂直和水平互连通道。互连网络包括IOB和相邻超级VGB之间的直接连接体系结构。转角和非拐角IOB之间的专用连接可在超级VGB中向CBB提供直接连接输入和输出。

25. 发明授权

US5912550A Power converter with 2.5 volt semiconductor process components 有权
标题翻译：电源转换器采用2.5伏半导体工艺组件
公开(公告)号：US5912550A
公开(公告)日：1999-06-15
申请号：US196080
申请日：1998-11-19
申请人： Bradley A. Sharpe-Geisler
发明人： Bradley A. Sharpe-Geisler
IPC分类号： G05F1/575 , G05F3/26 , G05F1/56
CPC分类号： G05F1/575 , G05F3/262
摘要： A power converter provides a voltage reference (Vdd) to a plurality of transistors on an integrated circuit with a limited voltage swing when a load is connected and removed. The power converter includes an opamp (100) having an input (+) receiving a voltage reference (V.sub.DIOD), an input (-) connected to a resistor divider (102, 104) and an output driving the gate of a transistor (110). The transistor (110) has a source to drain path providing a 3.3 volt supply (NV3EXT) to an output node (n2) which supplies Vdd. The output node (n2) is connected back to the resistor divider (102,104) and to the source of a cascode transistor (300). The cascode (300) is connected with cascode (302) to form a current mirror which is interconnected with transistor (304) and capacitor (306) to slow the response at node (n7) to transitions at the output node (n2). Cascode (300) drives a current mirror (314, 316). The operational amplifier (100) functions to control the gate voltage of transistor (110) to maintain the voltage Vdd at a constant value. With significant loading to the output, after the loading is removed, cascode (300) will turn on to cause transistor (316) to limit the voltage swing of Vdd until opamp (100) can return Vdd to a constant value.
摘要翻译：当负载被连接和移除时，功率转换器在集成电路上具有有限的电压摆幅的多个晶体管提供电压基准（Vdd）。功率转换器包括具有接收电压参考（VDIOD）的输入（+）的运算放大器（100），连接到电阻分压器（102,104）的输入（ - ）和驱动晶体管（110）的栅极的输出，。晶体管（110）具有向提供Vdd的输出节点（n2）提供3.3伏电源（NV3EXT）的源极到漏极路径。输出节点（n2）连接回电阻分压器（102,104）并连接到共源共栅晶体管（300）的源极。共源共栅（300）与共源共栅（302）连接以形成与晶体管（304）和电容器（306）互连的电流镜，以将节点（n7）处的响应减慢到输出节点（n2）处的转变。 Cascode（300）驱动电流镜（314,316）。运算放大器（100）用于控制晶体管（110）的栅极电压以将电压Vdd维持在恒定值。随着对输出的显着负载，在去除负载之后，共源共栅（300）将导通，以使晶体管（316）限制Vdd的电压摆幅，直到运算放大器（100）可以将Vdd返回到恒定值。

26. 发明申请

US20020186044A1 Variable grain architecture for FPGA integrated circuits 有权
公开(公告)号：US20020186044A1
公开(公告)日：2002-12-12
申请号：US10090209
申请日：2002-03-04
申请人： Vantis Corporation
发明人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Giap H. Tran
IPC分类号： H03K019/177
CPC分类号： H03K19/1737 , H01L2924/0002 , H03K19/17728 , H03K19/17736 , H03K19/17748 , H03K19/17752 , H03K19/17756 , H03K19/17792 , H03K19/17796 , H01L2924/00
摘要： A Variable Grain Architecture is disclosed wherein Variable Grain Blocks (VGB's) are wedged together in mirror opposition to one another to define super-VGB structures. The super-VGB structures are arranged as a matrix within an FPGA device. Each VGB includes progressive function synthesizing layers for forming more complex function signals by folding together less complex function signals of preceding layers. A function spawning layer containing a set of function spawning lookup tables (LUT's) is provided near the periphery of the corresponding super-VGB structure. In one case, the function spawning layer is L-shaped and includes a symmetrical distribution of Configurable Building Blocks. A signal-acquiring layer interfaces with adjacent interconnect lines to acquire input terms for the LUT's and controls. A decoding layer is interposed between the signal-acquiring layer and the function spawning layer for providing strapping and intercept functions. Each VGB has a common controls section, a wide-gating section and a carry-propagating section. Each super-VGB has a centrally-shared section of longline drivers that may be accessed from any of the constituent VGB's. A diversified spectrum of interconnect lines, including 2xL, 4xL, 8xL and direct connect surround each super-VGB to provide different kinds of interconnect.

27. 发明申请

US20010001075A1 Process for fabricating semiconductor memory device with high data retention including silicon nitride etch stop layer formed at high temperature with low hydrogen ion concentration 审中-公开
标题翻译：用于制造具有高数据保留的半导体存储器件的方法，包括在低氢离子浓度的高温下形成的氮化硅蚀刻停止层
公开(公告)号：US20010001075A1
公开(公告)日：2001-05-10
申请号：US09745626
申请日：2000-12-20
申请人： Vantis Corporation
发明人： Minh Van Ngo , Sunil Mehta
IPC分类号： H01L021/336 , H01L021/31 , H01L021/469 , H01L021/4763
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/66825 , Y10S438/97
摘要： A semiconductor memory device such as a flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes a floating gate with high data retention. A tungsten damascene local interconnect structure includes a silicon nitride etch stop layer which is formed using Plasma Enhanced Chemical Vapor Deposition (PECVD) at a temperature of at least 480null C. such that the etch stop layer has a very low concentration of hydrogen ions. The minimization of hydrogen ions, which constitute mobile positive charge carriers, in the etch stop layer, minimizes recombination of the hydrogen ions with electrons on the floating gate, and thereby maximizes data retention of the device.
摘要翻译：诸如闪存电可擦除可编程只读存储器（闪存EEPROM）的半导体存储器件包括具有高数据保持的浮动栅极。钨镶嵌局部互连结构包括在至少480℃的温度下使用等离子体增强化学气相沉积（PECVD）形成的氮化硅蚀刻停止层，使得蚀刻停止层具有非常低的氢离子浓度。在蚀刻停止层中构成移动正电荷载流子的氢离子的最小化最小化氢离子与浮动栅极上的电子的复合，从而使器件的数据保持最大化。

28. 发明授权

US06163168A Efficient interconnect network for use in FPGA device having variable grain architecture 有权
标题翻译：高效互连网络，用于具有可变粒度架构的FPGA器件
公开(公告)号：US06163168A
公开(公告)日：2000-12-19
申请号：US208203
申请日：1998-12-09
申请人： Bai Nguyen , Om P. Agrawal , Bradley A. Sharpe-Geisler , Jack T. Wong , Herman M. Chang
发明人： Bai Nguyen , Om P. Agrawal , Bradley A. Sharpe-Geisler , Jack T. Wong , Herman M. Chang
IPC分类号： H03K19/177 , H01L25/00
CPC分类号： H03K19/17736 , H03K19/1778 , H03K19/17796
摘要： A logic array device has an array of plural interconnect resources including plural lines and plural switchbox areas, with an array of plural Variable Grain Blocks (VGB's) interspersed within the array of plural interconnect resources. The array of plural interconnect resources does not regularly include lines of single-length or shorter, and the array of plural interconnect resources does not regularly include switchbox areas that are spaced apart from one another by distances of a single-length or shorter. The single-length corresponds to a traverse of a continuous distance covering approximately one VGB.
摘要翻译：逻辑阵列器件具有多个互连资源的阵列，包括多个线路和多个开关盒区域，多个可变格栅块（VGB）的阵列散布在多个互连资源的阵列内。多个互连资源的阵列不规则地包括单个长度或更短的线，并且多个互连资源的阵列不规则地包括通过单个长度或更短的距离彼此间隔开的开关盒区域。单个长度对应于覆盖大约一个VGB的连续距离的横越。

29. 发明授权

US06154051A Tileable and compact layout for super variable grain blocks within FPGA device 有权
标题翻译： FPGA器件内的超可变晶粒块的平铺紧凑布局
公开(公告)号：US06154051A
公开(公告)日：2000-11-28
申请号：US187689
申请日：1998-11-05
申请人： Bai Nguyen , Om P. Agrawal , Bradley A. Sharpe-Geisler , Jack T. Wong , Herman M. Chang , Giap H. Tran
发明人： Bai Nguyen , Om P. Agrawal , Bradley A. Sharpe-Geisler , Jack T. Wong , Herman M. Chang , Giap H. Tran
IPC分类号： H01L27/02 , H03K19/177 , H01L25/00
CPC分类号： H03K19/17736 , H01L27/0207 , H03K19/1778 , H03K19/17796
摘要： A tileable structure is provided for logic array devices. The tileable structure has a mirror-symmetrical arrangement of sets of logic blocks, common control sections for the logic block sets, surrounding interconnect lines, and switching areas at intersections of the interconnect lines.
摘要翻译：为逻辑阵列器件提供了可瓦片结构。可瓦片结构具有逻辑块集合的逻辑对称布置，用于逻辑块集合的公共控制部分，周围互连线以及互连线的交叉处的交换区域。

30. 发明授权

US06150842A Variable grain architecture for FPGA integrated circuits 失效
公开(公告)号：US06150842A
公开(公告)日：2000-11-21
申请号：US472645
申请日：1999-12-27
申请人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Giap H. Tran
发明人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Giap H. Tran
IPC分类号： H03K19/173 , H03K19/177 , H01L25/00
CPC分类号： H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17748 , H03K19/17752 , H03K19/17756 , H03K19/17792 , H03K19/17796 , H01L2924/0002
摘要： A Variable Grain Architecture is disclosed wherein Variable Grain Blocks (VGB's) are wedged together in mirror opposition to one another to define super-VGB structures. The super-VGB structures are arranged as a matrix within an FPGA device. Each VGB includes progressive function synthesizing layers for forming more complex function signals by folding together less complex function signals of preceding layers. A function spawning layer containing a set of function spawning lookup tables (LUT's) is provided near the periphery of the corresponding super-VGB structure. In one case, the function spawning layer is L-shaped and includes a symmetrical distribution of Configurable Building Blocks. A signal-acquiring layer interfaces with adjacent interconnect lines to acquire input terms for the LUT's and controls. A decoding layer is interposed between the signal-acquiring layer and the function spawning layer for providing strapping and intercept functions. Each VGB has a common controls section, a wide-gating section and a carry-propagating section. Each super-VGB has a centrally-shared section of longline drivers that may be accessed from any of the constituent VGB's. A diversified spectrum of interconnect lines, including 2.times.L, 4.times.L, 8.times.L and direct connect surround each super-VGB to provide different kinds of interconnect.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式