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21. 发明授权

US08928344B2 Compliant printed circuit socket diagnostic tool 有权
标题翻译：符合印刷电路插座诊断工具
公开(公告)号：US08928344B2
公开(公告)日：2015-01-06
申请号：US13266907
申请日：2010-05-27
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： G01R31/00 , G01R31/28 , G01R31/02
CPC分类号： G01R31/2889 , G01R31/024 , Y10T29/49004
摘要： Diagnostic tools for testing integrated circuit (IC) devices, and a method of making the same. The first diagnostic tool includes a first compliant printed circuit with a plurality of contact pads configured to form an electrical interconnect at a first interface between proximal ends of contact members in the socket and contact pads on a printed circuit board (PCB). A plurality of printed conductive traces electrically couple to a plurality of the contact pads on the first compliant printed circuit. A plurality of electrical devices are printed on the first compliant printed circuit at a location external to the first interface. The electrical devices are electrically coupled to the conductive traces and programmed to provide one or more of continuity testing at the first interface or functionality of the IC devices. A second diagnostic tool includes a second compliant printed circuit electrically coupled to a surrogate IC device.
摘要翻译：用于测试集成电路（IC）器件的诊断工具及其制作方法。第一诊断工具包括具有多个接触焊盘的第一顺应印刷电路，其被配置为在插座中的接触构件的近端和印刷电路板（PCB）上的接触焊盘之间的第一界面处形成电互连。多个印刷导电迹线电耦合到第一顺应印刷电路上的多个接触焊盘。多个电气设备被印刷在第一接合印刷电路上的位于第一接口外部的位置处。电气设备电耦合到导电迹线并被编程为在IC器件的第一接口或功能性处提供一个或多个连续性测试。第二诊断工具包括电耦合到替代IC器件的第二顺应印刷电路。

22. 发明授权

US08803539B2 Compliant wafer level probe assembly 有权
标题翻译：符合晶圆级探头组件
公开(公告)号：US08803539B2
公开(公告)日：2014-08-12
申请号：US13266522
申请日：2010-05-25
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： G01R1/067
CPC分类号： G01R1/07314
摘要： A probe assembly that acts as a temporary interconnect between terminals on a circuit member and a test station. The probe assembly can include a base layer of a dielectric material printed onto a surface of a fixture. The surface of the fixture can have a plurality of cavities. A plurality of discrete contact members can be formed in the plurality of cavities in the fixture and coupled to the base layer. A plurality of conductive traces can be printed onto an exposed surface of the base layer and electrically coupled with proximal ends of one or more of the discrete contact members. A compliant layer can be deposited over the conductive traces and the proximal ends of the contact members. A protective layer can be deposited on the compliant layer such that when the probe assembly is removed from the fixture the distal ends of the contact members contact terminals on the circuit member and the conductive traces electrically couple the circuit member to a test station. Electrical devices on the probe assembly can communicate with the test station to provide adaptive testing.
摘要翻译：探针组件，用作电路元件端子和测试台之间的临时互连。探针组件可以包括印刷在固定装置的表面上的电介质材料的基层。固定装置的表面可以具有多个空腔。多个离散的接触构件可以形成在固定装置中的多个空腔中并且耦合到基层。多个导电迹线可以印刷到基底层的暴露表面上并与一个或多个离散接触构件的近端电耦合。柔性层可以沉积在导电迹线和接触构件的近端上。保护层可以沉积在柔性层上，使得当探针组件从固定装置移除时，接触构件的远端接触电路构件上的端子，并且导电迹线将电路构件电耦合到测试台。探头组件上的电气设备可以与测试台通信以提供自适应测试。

23. 发明申请

US20140043782A1 COMPLIANT CORE PERIPHERAL LEAD SEMICONDUCTOR SOCKET 有权
标题翻译：合格的核心外围导线半导体插座
公开(公告)号：US20140043782A1
公开(公告)日：2014-02-13
申请号：US14058863
申请日：2013-10-21
申请人： HSIO TECHNOLOGIES, LLC
发明人： James Rathburn
IPC分类号： H01L23/522 , H05K3/40
CPC分类号： H01L23/34 , G01R1/0416 , H01L23/522 , H01L2224/13 , H05K3/325 , H05K3/4007 , H05K2201/0133 , H05K2201/0187 , H05K2201/09036 , H05K2201/09481 , H05K2201/0949 , H05K2201/10378 , H05K2203/162 , Y10T29/49165
摘要： An electrical interconnect between terminals on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a substrate with a first surface having a plurality of openings arranged to correspond to the terminals on the IC device. A compliant material is located in the openings. A plurality of first conductive traces extend along the first surface of the substrate and onto the compliant material. The compliant material provides a biasing force that resists flexure of the first conductive traces into the openings. Vias extending through the substrate are electrically coupled the first conductive traces. A plurality of second conductive traces extend along the second surface of the substrate and are electrically coupled to a vias. The second conductive traces are configured to electrical couple with the contact pads on the PCB.
摘要翻译： IC器件上的端子和印刷电路板（PCB）上的接触焊盘之间的电气互连。电互连包括具有第一表面的基板，该第一表面具有多个开口，其布置成对应于IC器件上的端子。柔性材料位于开口中。多个第一导电迹线沿着衬底的第一表面延伸到柔性材料上。柔性材料提供抵抗第一导电迹线弯曲到开口中的偏压力。延伸穿过衬底的通孔电耦合第一导电迹线。多个第二导电迹线沿着衬底的第二表面延伸并且电耦合到通孔。第二导电迹线被配置为与PCB上的接触焊盘电耦合。

24. 发明申请

US20130203273A1 HIGH SPEED BACKPLANE CONNECTOR 审中-公开
标题翻译：高速背板连接器
公开(公告)号：US20130203273A1
公开(公告)日：2013-08-08
申请号：US13575368
申请日：2011-01-31
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： H01R12/72 , H01R43/20
CPC分类号： H01R12/721 , H01R12/727 , H01R12/737 , H01R13/6587 , H01R43/20 , H01R43/24 , Y10T29/49208
摘要： A backplane connector including a substrate and a backplane connector set attached to the substrate. The backplane connector set includes a plurality of interconnect elements each having a conductive trace, a first contact member, and a second contact members matched to the first contact member. The first and second contact members extend beyond perimeter edges of the substrate. A plurality of conductive tie bars retain the interconnect elements in a fixed relationship prior to attachment to the substrate. Additive printing processes can be used to form the conductive traces.
摘要翻译：背板连接器，包括衬底和附接到衬底的背板连接器组。背板连接器组包括多个互连元件，每个互连元件具有导电迹线，第一接触元件和与第一接触元件匹配的第二接触元件。第一和第二接触构件延伸超过衬底的周边边缘。多个导电连接条在连接到基板之前将互连元件保持固定关系。可以使用添加印刷工艺来形成导电迹线。

25. 发明申请

US20120202364A1 COMPLIANT CONDUCTIVE NANO-PARTICLE ELECTRICAL INTERCONNECT 有权
标题翻译：合适的导电纳米颗粒电气互连
公开(公告)号：US20120202364A1
公开(公告)日：2012-08-09
申请号：US13448914
申请日：2012-04-17
申请人： James RATHBURN
发明人： James RATHBURN
IPC分类号： H01R12/71 , H05K3/32 , H05K3/28 , B82Y30/00
CPC分类号： H01L23/48 , B82Y10/00 , H01R23/722 , H05K1/0231 , H05K1/113 , H05K1/141 , H05K3/32 , H05K3/3436 , H05K3/4038 , H05K3/4069 , H05K7/1069 , H05K7/1092 , H05K2201/049 , Y10T29/4913 , Y10T29/49147
摘要： An electrical interconnect providing an interconnect between contacts on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a substrate with a plurality of through holes extending from a first surface to a second surface. A resilient material is located in the through holes. The resilient material includes an opening extending from the first surface to the second surface. A plurality of discrete, free-flowing conductive nano-particles are located in the openings of the resilient material. The conductive particles are substantially free of non-conductive materials. A plurality of first contact members are located in the through holes adjacent the first surface and a plurality of second contact members are located in the through holes adjacent the second surface. The first and second contact members are electrically coupled to the nano-particles.
摘要翻译：提供IC器件上的触点与印刷电路板（PCB）上的接触焊盘之间的互连的电互连。电互连包括具有从第一表面延伸到第二表面的多个通孔的基底。弹性材料位于通孔中。弹性材料包括从第一表面延伸到第二表面的开口。多个离散的自由流动的导电纳米颗粒位于弹性材料的开口中。导电颗粒基本上不含非导电材料。多个第一接触构件位于邻近第一表面的通孔中，并且多个第二接触构件位于与第二表面相邻的通孔中。第一和第二接触构件电耦合到纳米颗粒。

26. 发明申请

US20120164888A1 METALIZED PAD TO ELECTRICAL CONTACT INTERFACE 有权
标题翻译：金属化焊接到电气接触界面
公开(公告)号：US20120164888A1
公开(公告)日：2012-06-28
申请号：US13410914
申请日：2012-03-02
申请人： JAMES RATHBURN
发明人： JAMES RATHBURN
IPC分类号： H01R31/06 , H05K3/00
CPC分类号： H01R12/57 , H01R12/52 , H01R12/523 , H01R12/716 , H05K1/141 , H05K3/3436 , H05K3/4007 , H05K3/4046 , H05K7/1069 , H05K2201/049 , Y10T29/49124
摘要： A surface mount electrical interconnect to provide an interface between a PCB and contacts on an integrated circuit device. The electrical interconnect includes a substrate with a plurality of recesses arranged along a first surface to correspond to the contacts on the integrated circuit device. Contact members are located in a plurality of the recess. The contact members include contact tips adapted to electrically couple with the contacts on the integrated circuit device. An electrical interface including at least one circuit trace electrically couples the contact member to metalized pads located along a second surface of the substrate at a location offset from a corresponding contact member. A solder ball is attached to a plurality of the metalized pads.
摘要翻译：表面安装电互连，以提供PCB与集成电路器件上的触点之间的接口。电互连包括具有沿着第一表面布置以对应于集成电路器件上的触点的多个凹槽的衬底。接触构件位于多个凹部中。接触构件包括适于与集成电路器件上的触点电耦合的接触尖端。包括至少一个电路迹线的电接口将电接触构件电耦合到沿着衬底的第二表面位于偏离对应接触构件的位置的金属化焊盘。焊球连接到多个金属化焊盘。

27. 发明申请

US20120062270A1 COMPLIANT PRINTED CIRCUIT WAFER PROBE DIAGNOSTIC TOOL 有权
标题翻译：合格打印电路探头检测工具
公开(公告)号：US20120062270A1
公开(公告)日：2012-03-15
申请号：US13318038
申请日：2010-05-27
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： G01R31/26
CPC分类号： G01R31/2889 , G01R31/024 , H01L2224/16225
摘要： Diagnostic tools for testing wafer-level IC devices, and a method of making the same. The first diagnostic tool can include a first compliant printed circuit with a plurality of contact pads configured to form an electrical interconnect at a first interface between distal ends of probe members in the wafer probe and contact pads on a wafer-level IC device. A plurality of printed conductive traces electrically couple to a plurality of the contact pads on the first compliant printed circuit. A plurality of electrical devices are printed on the first compliant printed circuit at a location away from the first interface. The electrical devices are electrically coupled to the conductive traces and are configured to provide one or more of continuity testing or functionality of the wafer-level IC devices. A second diagnostic tool includes a second compliant printed circuit electrically coupled to a dedicated IC testing device. A plurality of electrical devices are printed on the second compliant printed circuit and electrically coupled to the dedicated IC device.
摘要翻译：用于测试晶圆级IC器件的诊断工具及其制作方法。第一诊断工具可以包括具有多个接触焊盘的第一顺应印刷电路，其被配置为在晶片探针中的探针部件的远端和晶片级IC器件上的接触焊盘之间的第一接口处形成电互连。多个印刷导电迹线电耦合到第一顺应印刷电路上的多个接触焊盘。在远离第一接口的位置处，在第一顺应印刷电路上印刷多个电气设备。电气设备电耦合到导电迹线并且被配置为提供晶片级IC器件的连续性测试或功能的一个或多个。第二诊断工具包括电耦合到专用IC测试装置的第二顺应印刷电路。多个电气设备印刷在第二顺应印刷电路上并电耦合到专用IC器件。

28. 发明申请

US20120058653A1 SINGULATED SEMICONDUCTOR DEVICE SEPARABLE ELECTRICAL INTERCONNECT 有权
标题翻译：单相半导体器件可分离电气互连
公开(公告)号：US20120058653A1
公开(公告)日：2012-03-08
申请号：US13319228
申请日：2010-06-28
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： H01R12/71
CPC分类号： G01R3/00 , G01R1/0491 , G01R1/0735 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49169 , Y10T29/49204 , Y10T29/49222
摘要： A socket assembly that forms a solderless electrical interconnection between terminals on a singulated integrated circuit device and another circuit member. The socket housing has an opening adapted to receive the singulated integrated circuit device. The compliant printed circuit is positioned relative to the socket housing to electrically couple with the terminals on a singulated integrated circuit device located in the opening. The compliant printed circuit includes a dielectric base layer printed onto a surface of a fixture, while leaving cavities in the surface of the fixture exposed. A plurality of contact members are formed in the plurality of cavities in the fixture and coupled to the dielectric base layer. The contact members are exposed wherein the compliant printed circuit is removed from the fixture. At least one dielectric layer with recesses corresponding to a target circuit geometry is printed on the dielectric base layer. A conductive material is deposited in at least a portion of the recesses to form conductive traces electrically coupling the contact members to the other circuit member.
摘要翻译：插座组件，其在单个集成电路器件和另一个电路部件之间形成端子之间的无焊接电气互连。插座壳体具有适于容纳单个集成电路装置的开口。顺应印刷电路相对于插座壳体定位，以在位于开口中的单个集成电路装置上与端子电耦合。柔性印刷电路包括印刷在固定装置表面上的电介质基层，同时在固定装置表面露出空腔。多个接触构件形成在固定装置中的多个空腔中，并与电介质基底层耦合。接触构件被暴露，其中柔性印刷电路从固定装置移除。具有对应于目标电路几何形状的凹部的至少一个电介质层被印刷在电介质基底层上。导电材料沉积在凹陷的至少一部分中以形成将接触构件电耦合到另一个电路构件的导电迹线。

29. 发明申请

US20120055701A1 HIGH PERFORMANCE SURFACE MOUNT ELECTRICAL INTERCONNECT 有权
标题翻译：高性能表面安装电气互连
公开(公告)号：US20120055701A1
公开(公告)日：2012-03-08
申请号：US13266486
申请日：2010-05-25
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： H05K1/03 , B23K31/02 , H05K1/16 , H05K1/02 , H05K1/09
CPC分类号： H01R12/7082 , H01R12/57 , Y10T29/4913 , Y10T29/49144 , Y10T29/49165
摘要： An interconnect assembly including a substrate with a plurality of through holes extending from a first surface to a second surface. A plurality of discrete contact member are located in the plurality of through holes. The contact members include proximal ends that are accessible from the second surface, distal ends extending above the first surface, and intermediate portions engaged with an engagement region of the substrate located between the first surface and the recesses. Retention members are coupled with at least a portion of the proximal ends to retain the contact members in the through holes. The retention members can be made from a variety of materials with different levels of conductivity, ranging from highly conductive to non-conductive.
摘要翻译：一种互连组件，包括具有从第一表面延伸到第二表面的多个通孔的基底。多个离散接触构件位于多个通孔中。接触构件包括从第二表面可接近的近端，在第一表面上方延伸的远端，以及与位于第一表面和凹部之间的基底的接合区域接合的中间部分。保持构件与至少一部分近端联接以将接触构件保持在通孔中。保持构件可以由具有不同导电性的各种材料制成，从高导电性到非导电性。

30. 发明申请

US20120043667A1 COMPLIANT PRINTED CIRCUIT SEMICONDUCTOR PACKAGE 有权
标题翻译：合格打印电路半导体封装
公开(公告)号：US20120043667A1
公开(公告)日：2012-02-23
申请号：US13318263
申请日：2010-05-27
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： H01L23/522 , H01L21/50
CPC分类号： H01L24/82 , H01L23/49811 , H01L23/5389 , H01L24/18 , H01L24/19 , H01L24/20 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/20 , H01L2224/73267 , H01L2224/92244 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/12044 , H01L2924/1306 , H01L2924/14 , H01L2924/15153 , H01L2924/15174 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3011 , H01L2924/3025 , H05K1/185 , H01L2924/00
摘要： A package for at least one semiconductor device and a method for making the package. At least one dielectric layer is selectively printed on at least a portion of the semiconductor device creating first recesses aligned with a plurality of the electrical terminals. A conductive material is printed in the first recesses forming contact members on the semiconductor device. At least one dielectric layer is selectively printed on at least a portion of the package to create a plurality of second recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the second recesses to create a circuit geometry. The circuit geometry includes a plurality of exposed terminals electrically coupled to the electric terminals on the semiconductor device.
摘要翻译：用于至少一个半导体器件的封装以及用于制造封装的方法。至少一个电介质层被选择性地印刷在半导体器件的至少一部分上，形成与多个电端子对准的第一凹槽。在形成半导体器件上的接触部件的第一凹部中印刷导电材料。至少一个电介质层被选择性地印刷在封装的至少一部分上以产生对应于目标电路几何形状的多个第二凹部。导电材料印刷在第二凹槽的至少一部分中以产生电路几何形状。电路几何形状包括电耦合到半导体器件上的电端子的多个暴露端子。

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