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21. 发明授权

US07392398B1 Method and apparatus for protection of computer assets from unauthorized access 有权
标题翻译：保护计算机资产免遭未经授权访问的方法和装置
公开(公告)号：US07392398B1
公开(公告)日：2008-06-24
申请号：US09586907
申请日：2000-06-05
申请人： Rajesh G. Shakkarwar
发明人： Rajesh G. Shakkarwar
IPC分类号： G06F21/00 , G06F21/02 , G06F21/04
CPC分类号： G06F21/54 , G06F21/575 , G06F21/577 , G06F21/629 , G06F21/74 , G06F2221/2103 , G06F2221/2105 , G06F2221/2137 , G06F2221/2141 , G06F2221/2151
摘要： A method and apparatus for protection of computer assets from unauthorized access is described. A protection engine is incorporated into microprocessor support circuitry to control access to computer assets, for example, BIOS memory and peripheral devices. The protection engine is capable of monitoring the state of an switch and controlling access to computer assets based, in part, on the state of the switch. The protection engine is capable of authenticating the source of interface control commands using cryptographic techniques. The protection engine provides protection against computer viruses, malicious cookies and java/javascript applets, macros, unauthorized remote access to a computer system, and other forms of unauthorized access.
摘要翻译：描述了一种用于保护计算机资产免于未经授权的访问的方法和装置。保护引擎并入微处理器支持电路中以控制对计算机资产的访问，例如BIOS存储器和外围设备。保护引擎能够监视交换机的状态，并且部分地基于交换机的状态来控制对计算机资产的访问。保护引擎能够使用加密技术来验证接口控制命令的来源。保护引擎提供针对计算机病毒，恶意Cookie和java / javascript小程序，宏，未经授权的远程访问计算机系统以及其他形式的未经授权访问的保护。

22. 发明申请

US20070208962A1 APPARATUS AND METHOD FOR REDUCING POWER CONSUMPTION OF A PROCESSOR BY ESTIMATING ENGINE LOAD 有权
标题翻译：通过估算发动机负荷来降低加工者的功率消耗的装置和方法
公开(公告)号：US20070208962A1
公开(公告)日：2007-09-06
申请号：US11555847
申请日：2006-11-02
申请人： Andrej Zdravkovic
发明人： Andrej Zdravkovic
IPC分类号： G06F1/32
CPC分类号： G06F9/3869 , G06F1/3203 , G06F1/324 , Y02D10/126
摘要： A computer system has a processor and a queue for storing instructions for execution by the processor. The processor is capable of being clocked at a plurality of different clock frequencies. In one embodiment, the clocking frequency is determined by estimating a short or long term load associated with the stored instructions. In another embodiment, the clocking frequency is determined by analyzing a set of the stored instructions.
摘要翻译：计算机系统具有处理器和用于存储由处理器执行的指令的队列。该处理器能够以多个不同的时钟频率进行计时。在一个实施例中，通过估计与存储的指令相关联的短期或长期负载来确定计时频率。在另一个实施例中，通过分析一组存储的指令来确定时钟频率。

23. 发明授权

US07254806B1 Detecting reordered side-effects 有权
标题翻译：检测重新排序的副作用
公开(公告)号：US07254806B1
公开(公告)日：2007-08-07
申请号：US09434394
申请日：1999-11-04
申请人： John S. Yates, Jr. , David L. Reese , Korbin S. Van Dyke , Paul H. Hohensee
发明人： John S. Yates, Jr. , David L. Reese , Korbin S. Van Dyke , Paul H. Hohensee
IPC分类号： G06F9/45 , G06F15/00
CPC分类号： G06F9/45558 , G06F9/45554 , G06F2009/45583
摘要： A computer binary translator translates at least a segment of a binary representation of a program from a first instruction set architecture to a second instruction set architecture. A sequence of side-effects in the translation differs from a sequence of side-effects in the original. The translation distinguishes memory loads that are believed to be directed to well-behaved memory from memory loads that are believed to be directed to non-well-behaved memory device(s). Instruction execution circuitry identifies a memory reference that has a side-effect that has been reordered by translation, the memory reference having been believed at translation time to be directed to well-behaved memory but at execution it is found that the reference cannot be guaranteed to be well-behaved. The instruction execution circuitry identifies whether the difference in side-effect order may have a material effect on the execution of the program. A roll-back program state is established, and execution of the original code resumes.
摘要翻译：计算机二进制翻译器将程序的二进制表示的至少一段从第一指令集架构转换为第二指令集体系结构。翻译中的副作用序列与原始的副作用序列不同。该翻译区分被认为被定向到良好行为的存储器的存储器负载，这些存储器负载相信被定向到不良行为的存储器件。指令执行电路识别具有通过转换重新排序的副作用的存储器引用，已经将翻译时间相信的存储器引用指向良好的存储器，但是在执行时，发现该引用不能被保证表现良好。指令执行电路识别副作用顺序的差异是否可能对程序的执行产生重大影响。建立回滚程序状态，并恢复原始代码的执行。

24. 发明授权

US07239198B1 Single gate oxide differential receiver and method 有权
标题翻译：单栅极氧化物差分接收器及方法
公开(公告)号：US07239198B1
公开(公告)日：2007-07-03
申请号：US09211469
申请日：1998-12-14
申请人： Oleg Drapkin , Grigori Temkine
发明人： Oleg Drapkin , Grigori Temkine
IPC分类号： G06G7/12
CPC分类号： H03K19/018585 , H03K19/00315 , H03K19/018528
摘要： An integrated differential receiver includes a single gate oxide differential receiver and an associated switchable voltage supply circuit. The integrated differential receiver determines the desired receiver supply voltage and selects a supply voltage for the single gate oxide differential receiver. When a lower supply voltage is determined as the desired supply voltage, the integrated differential receiver automatically provides a supply voltage to the single gate oxide differential receiver with a voltage higher than the I/O pad supply voltage and higher than the maximum input signal voltage to increase the speed of operation for the differential receiver. The switchable voltage supply circuit is operatively responsive to a control signal which indicates the desired supply voltage for the I/O pad. In one embodiment, both the single gate oxide differential receiver and the switchable voltage supply circuit are single gate oxide circuits.
摘要翻译：集成差分接收器包括单个栅极氧化物差分接收器和相关联的可切换电压供应电路。集成差分接收器确定所需的接收器电源电压，并选择单栅极氧化物差动接收器的电源电压。当将较低电源电压确定为所需的电源电压时，集成差分接收器自动向单栅极氧化物差动接收器提供电压，其电压高于I / O焊盘电源电压，并高于最大输入信号电压增加差动接收器的运行速度。可切换电压供应电路可操作地响应于指示I / O焊盘所需电源电压的控制信号。在一个实施例中，单栅极氧化物差动接收器和可切换电压供应电路都是单栅极氧化物电路。

25. 发明授权

US07228404B1 Managing instruction side-effects 有权
标题翻译：管理指令副作用
公开(公告)号：US07228404B1
公开(公告)日：2007-06-05
申请号：US09672440
申请日：2000-09-28
申请人： Ronak Patel , Korbin S. Van Dyke , T.R. Ramesh , Shalesh Thusoo , Gurjeet Singh Saund , Sanjay Mansingh , Paul William Campbell
发明人： Ronak Patel , Korbin S. Van Dyke , T.R. Ramesh , Shalesh Thusoo , Gurjeet Singh Saund , Sanjay Mansingh , Paul William Campbell
IPC分类号： G06F9/00
CPC分类号： G06F9/30174 , G06F9/3851 , G06F9/3861
摘要： A computer. When an instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location is recognized, a value is stored representative of an architecturally-visible representation of the side-effect, a format of the representative value being different than an architecturally-visible representation of the side-effect. Execution is resumed without generating the architecturally-visible side-effect. Later, the architecturally-visible representation corresponding to the representative value is written into the architecturally-visible storage location. On a context switch, a context of a first process is written and a context of a second process is loaded to place the second process into execution. At least some instructions maintain results in storage resources outside the context resource set, and instructions are marked to indicate whether or not a context switch may be performed at a boundary of the marked instruction. Instruction execution is monitored for a condition that is a superset of a condition whose occurrence is desired to be detected, and a first exception is raised as a result of recognizing the superset condition. Software filters the superset condition to determine whether the monitored condition has occurred, and if so, the software establishes a second exception to be raised after execution of further instructions of the instruction stream. When it is recognized that an instruction is to affect the execution of a second instruction, the processor is set into single-step mode. After the second instruction is executed, the computer is set out of single-step mode.
摘要翻译：一台电脑。当识别到在建筑上可见的存储位置中要求建筑上可见的副作用的指令时，存储代表该副作用的结构可视表示的值，代表值的格式不同于体系结构副作用的隐形表示。恢复执行，而不产生架构上可见的副作用。之后，对应于代表值的架构可视化表示被写入架构可见的存储位置。在上下文切换中，写入第一进程的上下文并加载第二进程的上下文以使第二进程执行。至少一些指令在上下文资源集合之外保持存储资源的结果，并且标记指令以指示是否可以在标记指令的边界执行上下文切换。监视指示执行是作为期望发生的条件的超集的条件，并且作为识别超集条件的结果而引起第一异常。软件过滤超集条件以确定监视条件是否已经发生，如果是，则软件在执行指令流的进一步指令之后建立第二个异常。当识别到指令影响第二指令的执行时，处理器被设置为单步模式。执行第二条指令后，计算机将处于单步模式。

26. 发明授权

US07137110B1 Profiling ranges of execution of a computer program 有权
标题翻译：分析计算机程序的执行范围
公开(公告)号：US07137110B1
公开(公告)日：2006-11-14
申请号：US09330852
申请日：1999-06-11
申请人： David L. Reese , John S. Yates, Jr. , Paul H. Hohensee
发明人： David L. Reese , John S. Yates, Jr. , Paul H. Hohensee
IPC分类号： G06F9/45
CPC分类号： G06F9/45554 , G06F9/45541 , G06F9/45558 , G06F2009/45583
摘要： Profiling execution of a program. The program is coded in a mode-dependent instruction set. During a profile-quiescent execution interval, the profile circuitry records no profile information. After a triggering event is detected, the profile circuitry commences a profiled execution interval, and records profile information describing every profileable event during that interval. The profiled information includes at least all divergence of execution from sequential execution and processor mode changes not inferable from instruction opcode. The recorded profile information is efficiently tailored to annotate the profiled binary code with sufficient processor mode information to resolve mode-dependency, and indicates contiguous ranges of sequential instructions executed during a profiled interval by low and high boundaries of the contiguous ranges, indicating the high boundary by the address of the last byte. The profile information identifies each distinct physical page of instruction text executed during the interval.
摘要翻译：分析程序的执行。程序以模式相关的指令集编码。在配置文件静态执行间隔期间，配置文件电路不记录配置文件信息。在检测到触发事件之后，简档电路开始分析执行间隔，并且记录在该间隔期间描述每个可描述事件的简档信息。分析信息至少包括从顺序执行执行的所有分歧和处理器模式改变，不能从指令操作码推断出。记录的配置文件信息被有效地定制以用足够的处理器模式信息来注释分布式二进制代码以解决模式依赖性，并且指示在间隔间隔期间通过连续范围的低和高边界执行的连续指令的连续范围，指示高边界通过最后一个字节的地址。简档信息标识在间隔期间执行的指令文本的每个不同物理页。

27. 发明授权

US07111290B1 Profiling program execution to identify frequently-executed portions and to assist binary translation 有权
标题翻译：分析程序执行以识别经常执行的部分并协助二进制翻译
公开(公告)号：US07111290B1
公开(公告)日：2006-09-19
申请号：US09425401
申请日：1999-10-22
申请人： John S. Yates, Jr. , David L. Reese , Paul H. Hohensee
发明人： John S. Yates, Jr. , David L. Reese , Paul H. Hohensee
IPC分类号： G06F9/45
CPC分类号： G06F9/45533
摘要： A method and a computer with circuitry configured for performance of the method are disclosed. During a profiled interval of an execution of a program on a computer, profile information is recorded describing the execution, without the program having been compiled for profiled execution. The program is coded in an instruction set in which an interpretation of an instruction depends on a processor mode not expressed in the binary representation of the instruction. The recorded profile information describes at least all events occurring during the profiled execution interval of the two classes: (1) a divergence of execution from sequential execution; and (2) a processor mode change that is not inferable from the opcode of the instruction that induces the processor mode change taken together with a processor mode before the mode change instruction. The profile information further identifies each distinct physical page of instruction text executed during the execution interval.
摘要翻译：公开了一种配置用于执行该方法的电路的方法和计算机。在计算机上执行程序的轮廓间隔期间，描述描述执行的简档信息，而没有编译用于轮廓执行的程序。程序被编码在指令集中，其中指令的解释取决于在指令的二进制表示中未表达的处理器模式。记录的简档信息至少描述了在两个类的分析执行间隔期间发生的所有事件：（1）执行从顺序执行的分歧; 和（2）在模式改变指令之前，与处理器模式改变一起引导处理器模式改变的处理器模式改变，其不能从引导处理器模式改变的指令的操作码推断。简档信息进一步标识在执行间隔期间执行的指令文本的每个不同物理页。

28. 发明授权

US07061504B1 Method and apparatus for configurable gamma correction in a video graphics circuit 有权
标题翻译：视频图形电路中可配置伽马校正的方法和装置
公开(公告)号：US07061504B1
公开(公告)日：2006-06-13
申请号：US09272069
申请日：1999-03-18
申请人： David I. J. Glen
发明人： David I. J. Glen
IPC分类号： G09G5/02
CPC分类号： G09G3/2011 , G09G2310/027 , G09G2320/0276
摘要： A method and apparatus for gamma correction in a video graphics circuit is accomplished by storing a plurality of gamma correction curves in one or more lookup tables that can be accessed using pixel display information to generate gamma-corrected data. Gamma correction selection information is provided to select which of the gamma correction curves is utilized to perform the gamma correction for a particular set of pixel data.
摘要翻译：通过在一个或多个查找表中存储多个伽马校正曲线来实现视频图形电路中的伽马校正的方法和装置，该曲线校正曲线可以使用像素显示信息进行访问以产生伽马校正数据。提供伽马校正选择信息以选择哪一个伽马校正曲线用于对特定的像素数据集执行伽马校正。

29. 发明授权

US07006117B1 Apparatus for testing digital display driver and method thereof 有权
标题翻译：数字显示驱动器测试装置及其方法
公开(公告)号：US07006117B1
公开(公告)日：2006-02-28
申请号：US09574327
申请日：2000-05-19
申请人： Albert Tung-chu Man , Victor Herbert Flack , Yuri Lee
发明人： Albert Tung-chu Man , Victor Herbert Flack , Yuri Lee
IPC分类号： G09G5/00
CPC分类号： G09G5/006 , G06F3/14 , G09G3/006 , G09G2330/12 , G09G2370/045 , Y10S345/904
摘要： In a specific embodiment of the present invention, a graphics device generates digital output data in response to a known input data. The resulting digital output data has an expected circular redundancy check (CRC) value. The generated digital output data is provided to a digital graphics output port associated with the graphics controller, which is thereby transmitted to a test apparatus over a digital graphics cable. The test apparatus performs an analysis on the received digital graphics data. The analysis results are transmitted back to the graphics device over a serial link of the digital display cable. The graphics device receives the transmitted analysis data, which is subsequently used to determine if the graphics device is operating properly. This determination may be made the graphics device, or by a host system for further analysis.
摘要翻译：在本发明的具体实施例中，图形装置响应已知的输入数据生成数字输出数据。所得到的数字输出数据具有预期的循环冗余校验（CRC）值。生成的数字输出数据被提供给与图形控制器相关联的数字图形输出端口，由此通过数字图形电缆将其传输到测试装置。测试装置对所接收的数字图形数据执行分析。分析结果通过数字显示电缆的串行链路传输回图形设备。图形设备接收传输的分析数据，随后用于确定图形设备是否正常运行。该确定可以被做成图形设备，或由主机系统进行进一步的分析。

30. 发明授权

US06950772B1 Dynamic component to input signal mapping system 有权
标题翻译：动态组件输入信号映射系统
公开(公告)号：US06950772B1
公开(公告)日：2005-09-27
申请号：US09741456
申请日：2000-12-19
申请人： Edward G. Callway
发明人： Edward G. Callway
IPC分类号： G06F3/00 , H03M1/12 , H04N17/02 , H04N17/04
CPC分类号： H04N17/02 , H03M1/123 , H04N17/045
摘要： A dynamic component to input signal mapping system is disclosed that receives different types of input signals applied to a number of components and provides resultant output signals. The system includes input ports receiving the input signals, output ports providing the output signals, and a number of components processing the input signals, each of the components having at least one input and one output. The system includes a test signal source coupled to the components. Additionally, a signal analyzer coupled to an output of components analyzes response signals output from the components in response to test signals. The system is operative to map at least one component to receive at least one input signal based on the analyzed response. The system allows components on a semiconductor chip to be dynamically reconfigured for optimal processing of different types of signals, such as video and audio signals.
摘要翻译：公开了一种输入信号映射系统的动态分量，其接收施加到多个分量的不同类型的输入信号并提供合成的输出信号。该系统包括接收输入信号的输入端口，提供输出信号的输出端口以及处理输入信号的多个组件，每个组件具有至少一个输入和一个输出。该系统包括耦合到组件的测试信号源。另外，耦合到组件的输出的信号分析器分析响应于测试信号从组件输出的响应信号。该系统可操作以基于所分析的响应映射至少一个组件以接收至少一个输入信号。该系统允许动态地重新配置半导体芯片上的组件，以便对不同类型的信号（例如视频和音频信号）进行最佳处理。

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