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11. 发明授权

US06605847B2 Semiconductor device having gate all around type transistor and method of forming the same 有权
公开(公告)号：US06605847B2
公开(公告)日：2003-08-12
申请号：US10039151
申请日：2002-01-03
申请人： Sang-Su Kim , Tae-Hee Choe , Hwa-Sung Rhee , Geum-Jong Bae , Nae-In Lee
发明人： Sang-Su Kim , Tae-Hee Choe , Hwa-Sung Rhee , Geum-Jong Bae , Nae-In Lee
IPC分类号： H01L29786
CPC分类号： H01L29/78696 , H01L29/42384 , H01L29/42392 , H01L29/66772 , H01L29/78654 , Y10S438/933
摘要： A semiconductor device having a transistor of gate all around (GAA) type and a method of fabricating the same are disclosed. A SOI substrate composed of a SOI layer, a buried oxide layer and a lower substrate is prepared. The SOI layer has at least one unit dual layer of a silicon germanium layer and a silicon layer. The SOI layer is patterned to form an active layer pattern to a certain direction. An insulation layer is formed to cover the active layer pattern. An etch stop layer is stacked on the active layer pattern covered with the insulation layer. The etch stop layer is patterned and removed at a gate region crossing the active layer pattern at the channel region. The insulation layer is removed at the gate region. The silicon germanium layer is isotropically etched and selectively removed to form a cavity at the channel region of the active layer pattern. In the state that the silicon germanium layer is selectively removed, a gate insulation layer is formed to cover the exposed surface of the active layer pattern. A gate conductivity layer is stacked on the substrate by a chemical vapor deposition (CVD) to fill the gate region including the cavity. The middle part of the channel region of the active layer pattern can be patterned to be divided by multiple patterns that are formed in a line.

12. 发明授权

US06534787B2 Asymmetrical MOS channel structure with drain extension 有权
标题翻译：具有漏极延伸的非对称MOS沟道结构
公开(公告)号：US06534787B2
公开(公告)日：2003-03-18
申请号：US09768312
申请日：2001-01-23
申请人： Sheng Teng Hsu
发明人： Sheng Teng Hsu
IPC分类号： H01L29786
CPC分类号： H01L29/66659 , H01L21/26586 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/7835 , H01L29/78624
摘要： A method of forming a MOS transistor without a lightly doped drain (LDD) region between the channel region and drain is provided. The channel region and a drain extension are formed from two separate tilted ion implantation processes, after the deposition of the gate electrode. The tilted implantation forms a relatively short channel length, with respect to the length of the gate electrode. The position of the channel is offset, and directly adjoins the source. A second tilted implant process forms a drain extension region under the gate electrode, adjacent the drain. Elimination of LDD areas reduces the number of masking and doping steps required to manufacture a transistor. Further, the drain extension area promotes transistor performance, by eliminating source resistance. At the same time, sufficient doping of the drain extension area insures that the drain resistance through the drain extension remains low. This drain extension acts to more evenly distribute electric fields so that large breakdown voltages are possible. In this manner, larger Id currents and faster switching speeds are obtained. A MOS transistor having a short, offset channel and drain extension formed through dual tilted ion implants is also provided.
摘要翻译：提供了一种形成在沟道区和漏极之间没有轻掺杂漏极（LDD）区的MOS晶体管的方法。在栅电极沉积之后，沟槽区和漏极延伸由两个分开的倾斜离子注入工艺形成。相对于栅电极的长度，倾斜注入形成相对短的沟道长度。通道的位置偏移，并直接与源相邻。第二倾斜注入工艺在栅电极下方形成漏极延伸区域，与漏极相邻。消除LDD面积减少了制造晶体管所需的掩模和掺杂步骤的数量。此外，漏极扩展区域通过消除源极电阻来促进晶体管的性能。同时，漏极扩展区的充分掺杂确保通过漏极延伸的漏极电阻保持较低。这种漏极扩展用于更均匀地分布电场，使得可以实现大的击穿电压。以这种方式，获得更大的Id电流和更快的开关速度。还提供了通过双倾斜离子植入物形成的具有短的偏移沟道和漏极延伸的MOS晶体管。

13. 发明授权

US06355942B1 Active matrix display and forming method thereof 有权
标题翻译：有源矩阵显示及其形成方法
公开(公告)号：US06355942B1
公开(公告)日：2002-03-12
申请号：US09287551
申请日：1999-04-05
申请人： Shunpei Yamazaki , Jun Koyama , Yuji Kawasaki , Toshimitsu Konuma , Satoshi Teramoto , Yoshiharu Hirakata
发明人： Shunpei Yamazaki , Jun Koyama , Yuji Kawasaki , Toshimitsu Konuma , Satoshi Teramoto , Yoshiharu Hirakata
IPC分类号： H01L29786
CPC分类号： G02F1/13454 , G02F1/1339
摘要： An active matrix liquid crystal display having improved reliability. Pixel regions and a peripheral driver circuit are integrally packed on the display. TFTs forming the peripheral driver circuit are located inside a sealing material layer on the side of a liquid crystal material, thus protecting the peripheral driver circuit from external moisture and contaminants. This enhances the long-term reliability of the peripheral driver circuit. Pixel TFTs are arranged in pixel regions. The leads going from the TFTs forming the peripheral driver circuit to the pixel TFTs are shortened. This results in a reduction in the resistance. As a result, the display characteristics are improved.
摘要翻译：一种具有提高可靠性的有源矩阵液晶显示器。像素区域和外围驱动器电路整体地封装在显示器上。形成外围驱动电路的TFT位于液晶材料侧的密封材料层的内部，从而保护外围驱动电路免受外部湿气和污染物的影响。这增强了外围驱动电路的长期可靠性。像素TFT布置在像素区域中。从形成外围驱动电路的TFT到像素TFT的引线缩短。这导致电阻降低。结果，改善了显示特性。

14. 发明授权

US06355941B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06355941B1
公开(公告)日：2002-03-12
申请号：US08371486
申请日：1995-01-11
申请人： Shunpei Yamazaki , Yujiro Nagata
发明人： Shunpei Yamazaki , Yujiro Nagata
IPC分类号： H01L29786
CPC分类号： H01L29/1608 , H01L21/02422 , H01L21/02491 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L29/04 , H01L29/16 , H01L29/161 , H01L29/24 , H01L29/78618 , H01L29/7866 , H01L29/78666 , H01L29/78684 , H01L31/046 , H01L31/0465 , H01L31/202 , Y02E10/50 , Y02P70/521 , Y10S148/077 , Y10S148/093
摘要： A semiconductor device which has a non-single crystal semiconductor layer formed on a substrate and in which the non-single crystal semiconductor layer is composed of a first semiconductor region formed primarily of non-single crystal semiconductor and a second semi-conductor region formed primarily of semi-amorphous semiconductor. The second semi-conductor region has a higher degree of conductivity than the first semiconductor region so that a semi-conductor element may be formed.
摘要翻译：一种半导体器件，其具有在基板上形成的非单晶半导体层，其中非单晶半导体层由主要由非单晶半导体形成的第一半导体区域和主要形成的第二半导体区域构成的半非晶半导体。第二半导体区域具有比第一半导体区域更高的导电性，从而可以形成半导体元件。

15. 发明授权

US06346715B1 Semiconductor device and semiconductor display device 失效
公开(公告)号：US06346715B1
公开(公告)日：2002-02-12
申请号：US09132633
申请日：1998-08-11
申请人： Shunpei Yamazaki , Jun Koyama
发明人： Shunpei Yamazaki , Jun Koyama
IPC分类号： H01L29786
摘要： A semiconductor device including a control circuit for carrying out gamma correction of a supplied signal and a memory for storing data used in the gamma correction. The control circuit and the memory are constituted by TFTs and are a integrally formed on the same insulating substrate. A semiconductor display device including a pixel region in which a plurality of TFTs are arranged in matrix; a driver for switching the plurality of TFTs; a picture signal supply source for supplying a picture signal; a control circuit for carrying out gamma correction of the picture signal; and a memory for storing data used in the gamma correction of the picture signal. The plurality of TFTs, the driver, the control circuit, and the memory are integrally formed on the same insulating substrate.

16. 发明授权

US06303946B1 Thin film transistor substrate and liquid crystal display unit having a low-resistance silicon compound film 失效
标题翻译：薄膜晶体管基板和具有低电阻硅化合物膜的液晶显示单元
公开(公告)号：US06303946B1
公开(公告)日：2001-10-16
申请号：US09118481
申请日：1998-07-17
申请人： Chae Gee Sung
发明人： Chae Gee Sung
IPC分类号： H01L29786
CPC分类号： H01L29/66765 , H01L29/41733 , H01L29/458 , H01L29/78618
摘要： The present invention provides a thin-film transistor substrate comprising: a gate electrode 40 and a gate insulating film 41 formed on a substrate 36; a semiconductor active film 42 oppositely provided on the gate electrode via the gate insulating film; a pair of ohmic contact films 43 and 44 separately provided on the semiconductor active film; a low-resistance silicon compound film 45 ranging from the ohmic contact films to the gate insulating film so as to cover the ohmic contact films and the portions of the semiconductor active film superposing with the ohmic contact films; and a source electrode 46 and a drain electrode 48 provided on the low-resistance silicon compound film.
摘要翻译：本发明提供一种薄膜晶体管基板，包括：形成在基板36上的栅极40和栅极绝缘膜41; 通过栅极绝缘膜在栅电极上相对设置的半导体有源膜42; 分别设置在半导体活性膜上的一对欧姆接触膜43和44; 从欧姆接触膜到栅极绝缘膜的低电阻硅化合物膜45，以覆盖欧姆接触膜和与欧姆接触膜重叠的半导体有源膜的部分; 以及设置在低电阻硅化合物膜上的源电极46和漏电极48。

17. 发明授权

US06236064B1 Electro-optical device 失效
标题翻译：电光装置
公开(公告)号：US06236064B1
公开(公告)日：2001-05-22
申请号：US08470598
申请日：1995-06-06
申请人： Akira Mase , Masaaki Hiroki
发明人： Akira Mase , Masaaki Hiroki
IPC分类号： H01L29786
CPC分类号： H01L27/124 , G02F1/13624 , G02F2001/136245 , H01L27/1214 , H01L29/4908
摘要： A liquid-crystal electro-optical device capable of compensating for the operation of any malfunctioning one of TFTs (thin-film transistors) existing within the device if such a malfunction occurs. Plural complementary TFT configurations are provided per pixel electrode. Each complementary TFT configuration consists of at least one p-channel TFT and at least one n-channel TFT. The input and output terminals of the plural complementary TFT configurations are connected in series. One of the input and output terminals is connected to the pixel electrode, while the other is connected to a first signal line. All the gate electrodes of the p-channel and n-channel TFTs included in said plural complementary TFT configurations are connected to a second signal line.
摘要翻译：如果发生这种故障，则能够补偿设备内存在的任何故障的TFT（薄膜晶体管）的操作的液晶电光器件。每像素电极提供多个互补TFT配置。每个互补TFT配置由至少一个p沟道TFT和至少一个n沟道TFT组成。多个互补TFT结构的输入和输出端子串联连接。输入和输出端之一连接到像素电极，而另一个连接到第一信号线。包括在所述多个互补TFT配置中的p沟道和n沟道TFT的所有栅电极连接到第二信号线。

18. 发明授权

US06818923B2 Thin film transistor array substrate and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列基板及其制造方法
公开(公告)号：US06818923B2
公开(公告)日：2004-11-16
申请号：US10273891
申请日：2002-10-21
申请人： Woong Kwon Kim , Heung Lyul Cho , Seung Hee Nam
发明人： Woong Kwon Kim , Heung Lyul Cho , Seung Hee Nam
IPC分类号： H01L29786
CPC分类号： G02F1/13458 , G02F1/1362 , G02F2001/136236 , H01L27/1255 , H01L27/1288
摘要： A thin film transistor array substrate, and its manufacturing method, that is made using a three-round mask process. Gate patterns, each of which includes a gate line consisting of a transparent metal pattern and a gate metal pattern, a gate electrode, a lower gate pad, a lower data pad, and a pixel electrode are formed using a first mask process. A second mask process forms a gate insulating pattern and a semiconductor pattern. A third mask process forms source and drain patterns, each of which includes a data line, a source electrode, a drain electrode, an upper gate pad and an upper data pad. Additionally, the gate metal pattern on an upper portion of the pixel electrode is removed.
摘要翻译：一种薄膜晶体管阵列基板及其制造方法，采用三面掩模工艺制成。使用第一掩模处理形成栅极图案，每个栅极图案包括由透明金属图案和栅极金属图案构成的栅极线，栅电极，下栅极焊盘，下数据焊盘和像素电极。第二掩模工艺形成栅极绝缘图案和半导体图案。第三掩模处理形成源极和漏极图案，其中每个包括数据线，源电极，漏电极，上栅极焊盘和上数据焊盘。此外，去除像素电极上部的栅极金属图案。

19. 发明授权

US06818922B2 Thin film transistor array and driving circuit structure 有权
标题翻译：薄膜晶体管阵列和驱动电路结构
公开(公告)号：US06818922B2
公开(公告)日：2004-11-16
申请号：US10249342
申请日：2003-04-02
申请人： Hsin-Ming Chen
发明人： Hsin-Ming Chen
IPC分类号： H01L29786
CPC分类号： H01L27/1288 , H01L27/1255
摘要： A thin film transistor array and driving circuit structure fabricated on a substrate. The structure comprises a plurality of scanning lines, a plurality of signaling lines, a plurality of thin film transistors, a plurality of pixel electrodes, a plurality of storage capacitors and a plurality of CMOS transistors. Each thin film transistor includes a polysilicon layer, a source/drain terminal, an N+ doped thin film, a gate and a gate insulation layer. The polysilicon layer is formed on the substrate and the source/drain terminal is formed over the polysilicon layer. The N+ doped thin film is positioned between the polysilicon layer and the source/drain terminal. The gate is formed over the polysilicon layer and the gate insulation layer is positioned between the polysilicon layer and the gate.
摘要翻译：薄膜晶体管阵列和驱动电路结构制造在基板上。该结构包括多个扫描线，多个信令线，多个薄膜晶体管，多个像素电极，多个存储电容器和多个CMOS晶体管。每个薄膜晶体管包括多晶硅层，源极/漏极端子，N +掺杂薄膜，栅极和栅极绝缘层。多晶硅层形成在衬底上，源极/漏极端子形成在多晶硅层上。 N +掺杂的薄膜位于多晶硅层和源极/漏极端子之间。栅极形成在多晶硅层上，栅极绝缘层位于多晶硅层和栅极之间。

20. 发明授权

US06710372B2 Thin film transistor array panel for liquid crystal display 有权
标题翻译：用于液晶显示的薄膜晶体管阵列面板
公开(公告)号：US06710372B2
公开(公告)日：2004-03-23
申请号：US10228211
申请日：2002-08-26
申请人： Dong-Gyu Kim
发明人： Dong-Gyu Kim
IPC分类号： H01L29786
CPC分类号： G02F1/13624 , G02F1/136213 , G02F1/136286 , G02F2001/134345 , H01L27/124 , H01L27/1288
摘要： There are provided two subpixels opposite each other with respect to each data line. A pair of gate lines are provided for each row of pixels. A plurality of subsidiary signal lines are provided between the adjoining columns of the pixels. The data lines and the subsidiary signal lines are alternately arranged between the adjoining columns of the pixels. A storage wire is provided between the adjoining rows of the pixels.
摘要翻译：提供了相对于每个数据线彼此相对的两个子像素。为每行像素提供一对栅极线。在像素的相邻列之间提供多条辅助信号线。数据线和辅助信号线交替地布置在像素的相邻列之间。存储线设置在相邻的像素行之间。

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