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11. 发明授权

US06650001B2 Lateral semiconductor device and vertical semiconductor device 失效
标题翻译：侧面半导体器件和垂直半导体器件
公开(公告)号：US06650001B2
公开(公告)日：2003-11-18
申请号：US10053657
申请日：2002-01-24
申请人： Yoshihiro Yamaguchi , Hideaki Ninomiya , Tomoki Inoue
发明人： Yoshihiro Yamaguchi , Hideaki Ninomiya , Tomoki Inoue
IPC分类号： H01L27082
CPC分类号： H01L29/0696 , H01L29/0834 , H01L29/7394 , H01L29/7397
摘要： A lateral semiconductor device includes an n-type buffer layer (15) selectively formed in the surface of an n-type base layer (14), a p-type drain layer (16) selectively formed in the surface of the n-type buffer layer (15), a p-type base layer (17) formed in the surface of the n-type base layer (14) so as to surround the n-type buffer layer (15), an n+-type source layer (18) selectively formed in the surface of the p-type base layer (17), a source electrode (24) in contact with the p-type base layer (17) and the n+-type source layer (18), a drain electrode (22) in contact with the p-type drain layer (16), and a gate electrode (20) formed via a gate insulating film (19) on the surface of the p-type base layer (17) sandwiched between the n+-type source layer (18) and the n-type base layer (14). The p-type drain layer (16) has an annular structure or horseshoe-shaped structure, or is divided into a plurality of portions. This realizes a high breakdown voltage with a low ON voltage.
摘要翻译：横向半导体器件包括：n型缓冲层（15），其选择性地形成在n型基极层（14）的表面; p型漏极层（16），其选择性地形成在n型缓冲层层（15），形成在n型基底层（14）的表面中以围绕n型缓冲层（15）的p型基底层（17），n +型源选择性地形成在p型基底层（17）的表面中的层（18），与p型基底层（17）和n +型源极层（18）接触的源极（24）），与p型漏极层（16）接触的漏电极（22）和在p型基极层（17）的表面上经由栅极绝缘膜（19）形成的栅电极（20）夹在n +型源极层（18）和n型基极层（14）之间。 p型漏极层（16）具有环状结构或马蹄形结构，或分为多个部分。这实现了具有低导通电压的高击穿电压。

12. 发明授权

US06600211B1 Bipolar transistor constructions 失效
标题翻译：双极晶体管结构
公开(公告)号：US06600211B1
公开(公告)日：2003-07-29
申请号：US10175175
申请日：2002-06-18
申请人： Nathaniel J. Collins
发明人： Nathaniel J. Collins
IPC分类号： H01L27082
CPC分类号： H01L29/66272 , H01L21/8222 , H01L27/082 , H01L29/1004
摘要： The invention includes a bipolar transistor construction having a collector region, emitter region, and base region extending within a semiconductive material substrate. The construction further comprises separate access regions associated with the base region, emitter region and collector region, respectively. An n-type doped connecting region is comprised by the collector region and extends beneath the emitter and base regions. A p-type doped location is comprised by the base region and extends beneath the emitter region and above the n-type doped connecting region. An n-type doped intermediate location is within the emitter region and between the p-type doped location and the emitter access region. The invention also includes methods of forming bipolar transistors.
摘要翻译：本发明包括具有在半导体材料衬底内延伸的集电极区域，发射极区域和基极区域的双极晶体管结构。该结构还包括分别与基极区域，发射极区域和集电极区域相关联的分离的存取区域。 n型掺杂连接区域由集电极区域包围并在发射极和基极区域的下方延伸。 p型掺杂位置由基极区域包括并在发射极区域的下方和n型掺杂连接区域的上方延伸。 n型掺杂的中间位置在发射极区域内和p型掺杂位置和发射极接入区之间。本发明还包括形成双极晶体管的方法。

13. 发明授权

US06563194B1 BJT with surface resistor connection 失效
标题翻译： BJT带表面电阻连接
公开(公告)号：US06563194B1
公开(公告)日：2003-05-13
申请号：US09666848
申请日：2000-09-21
申请人： Kazuhisa Sakamoto
发明人： Kazuhisa Sakamoto
IPC分类号： H01L27082
CPC分类号： H01L27/0658 , H01L29/7304
摘要： A semiconductor device having: a base area of the first conduction type formed on a semiconductor substrate; an emitter area of the second conduction type formed in the base area; and a collector area of the second conduction type formed as joined to the base area. In the collector area, an impurity area of the first conduction type is formed as separated from the base area. A surface resistor is connected to a base electrode connected to the base area. The surface resistor is connected, at other position thereof, to the impurity area.
摘要翻译：一种半导体器件，具有：在半导体衬底上形成的第一导电类型的基极区域; 形成在基部区域中的第二导电类型的发射极区域; 以及形成为接合到基部区域的第二导电类型的集电极区域。在集电极区域中，形成与基极区域分离的第一导电类型的杂质区域。表面电阻器连接到连接到基座区域的基极。表面电阻器的其他位置连接到杂质区域。

14. 发明授权

US06555894B2 Device with patterned wells and method for forming same 失效
标题翻译：具有图案化孔的装置及其形成方法
公开(公告)号：US06555894B2
公开(公告)日：2003-04-29
申请号：US09062964
申请日：1998-04-20
申请人： James D. Beasom
发明人： James D. Beasom
IPC分类号： H01L27082
CPC分类号： H01L29/6659 , H01L21/2253 , H01L21/266 , H01L29/0692 , H01L29/0821 , H01L29/1079 , H01L29/7322
摘要： In a semiconductor substrate having a top surface and a PN junction between a first region of one conductivity type formed by masked diffusion into a semiconductor from the surface and a second region of opposite conductivity type formed into a first portion of the first region from the surface, the improvement comprises one edge of the first region being spaced from the edge of the second region such that the doping concentration of the first region at the surface intersection of the four corners of the junction between the first and second regions is lower than it is at some other location in the region. A semiconductor device comprises: a substrate with a surface; a first region of one conductivity type that is defined by a first perimeter at the surface, extends from the surface to a first depth, and has a doping concentration that decrease with depth and with proximity to the first perimeter; and a second region of opposite conductivity type that is defined by a second perimeter, extends from the surface to a second depth, and has a doping concentration that decreases with depth and with proximity to the second perimeter. The second region overlaps the first region, and the doping concentration of the first region at the surface intersection of the first and second regions is less than the maximum doping concentration at other locations on the surface within the first perimeter where the second region overlaps the first region.
摘要翻译：在半导体衬底中具有顶表面和PN结之间的一个导电类型的第一区域，该第一区域通过从表面被掩蔽扩散到半导体中而形成，第二区域相反导电型形成第一区域的第一部分，改进包括第一区域的一个边缘与第二区域的边缘间隔开，使得第一区域和第二区域之间的结点的四个角的表面交叉处的第一区域的掺杂浓度低于第一区域在该地区的其他地点。半导体器件包括：具有表面的衬底; 由表面的第一周界限定的一种导电类型的第一区域从表面延伸到第一深度，并且具有随深度减小并且接近第一周边的掺杂浓度; 并且由第二周界限定的相反导电类型的第二区域从表面延伸到第二深度，并且具有随着深度和邻近第二周边而减小的掺杂浓度。第二区域与第一区域重叠，并且第一和第二区域的表面交叉处的第一区域的掺杂浓度小于在第一周边内的表面上的其它位置处的最大掺杂浓度，其中第二区域与第一区域重叠地区。

15. 发明授权

US06521972B1 RF power transistor having low parasitic impedance input feed structure 有权
标题翻译： RF功率晶体管具有低寄生阻抗输入馈送结构
公开(公告)号：US06521972B1
公开(公告)日：2003-02-18
申请号：US09675098
申请日：2000-09-28
申请人： Wei-Shu Zhou , Shuo-Yuan Hsiao , Nanlei Larry Wang
发明人： Wei-Shu Zhou , Shuo-Yuan Hsiao , Nanlei Larry Wang
IPC分类号： H01L27082
CPC分类号： H01L23/66 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An RF microwave power transistor has an input/output feed structure which functions as a low impedance microstrip line by providing a ground plane in close proximity to the feed structure on one surface of a semiconductor body. A second ground plane can be provided on an opposing surface of the semiconductor body with vias interconnecting the first and second ground planes. In addition to reducing feed impedance, a larger total transistor size can be provided before “odd mode oscillation” occurs.
摘要翻译： RF微波功率晶体管具有输入/输出馈送结构，其通过在半导体本体的一个表面上靠近馈电结构提供接地平面来起到低阻抗微带线的作用。可以在半导体主体的相对表面上设置第二接地平面，该通孔具有互连第一和第二接地平面的通孔。除了降低馈电阻抗之外，在“奇模振荡”发生之前，可以提供更大的总体晶体管尺寸。

16. 发明授权

US06489665B2 Lateral bipolar transistor 有权
标题翻译：侧面双极晶体管
公开(公告)号：US06489665B2
公开(公告)日：2002-12-03
申请号：US09742706
申请日：2000-12-20
申请人： Kirk D. Prall , Mike P. Violette
发明人： Kirk D. Prall , Mike P. Violette
IPC分类号： H01L27082
CPC分类号： H01L29/6625 , H01L21/8222 , H01L21/8249 , H01L27/0623 , H01L27/082 , H01L29/735
摘要： A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a periphery of the base region to form the concentric lateral bipolar transistor of the invention. A gate overlies the substrate and at least a portion of the base region. At least one electrical contact is formed connecting the base and the gate, although a plurality of contacts may be formed. A further bipolar transistor is formed according to the following method of the invention. A base region is formed in a substrate and a gate region is formed overlying at least a portion of the base region. Emitter and collector terminals are formed on opposed sides of the base region. The gate is used as a mask during first and second ion implants. During the first ion implant the ions bombard the substrate from a first direction to grade a base/emitter junction, and during the second ion implant ions bombard the substrate from a second direction to grade a base/collector junction. Also a lateral bipolar transistor having a decreased base width as a result of implanting ions after fabrication of collector and emitter regions to enlarge the collector and emitter regions, thereby decreasing the base region and increasing gain.
摘要翻译：基本同心的横向双极晶体管及其形成方法。基极区域围绕发射极区域的周边设置，并且集电极区域围绕基极区域的周边设置以形成本发明的同心横向双极晶体管。栅极覆盖衬底和基极区域的至少一部分。形成连接基座和栅极的至少一个电触头，尽管可以形成多个触点。根据本发明的以下方法形成另外的双极晶体管。在基板中形成基极区域，并且形成覆盖基极区域的至少一部分的栅极区域。发射极和集电极端子形成在基极区域的相对侧上。在第一和第二离子注入期间，门用作掩模。在第一离子注入期间，离子从第一方向轰击衬底以分级基极/发射极结，并且在第二离子注入期间，离子从第二方向轰击衬底以对基极/集电极结进行分级。另外，作为在制造集电极和发射极区域之后注入离子的结果，具有减小的基极宽度的横向双极晶体管，以扩大集电极和发射极区域，从而减小基极区域并增加增益。

17. 发明授权

US06414372B2 Bipolar transistor having lightly doped epitaxial collector region constant in dopant impurity and process of fabrication thereof 失效
标题翻译：掺杂杂质中掺杂稀土外延层的双极晶体管的常数和制造方法
公开(公告)号：US06414372B2
公开(公告)日：2002-07-02
申请号：US08807326
申请日：1997-02-27
申请人： Yasushi Kinoshita
发明人： Yasushi Kinoshita
IPC分类号： H01L27082
CPC分类号： H01L29/66287 , H01L29/0821 , H01L29/7322
摘要： A bipolar transistor has a lightly doped n-type single crystal silicon layer epitaxially grown in a recess formed in a heavily doped n-type impurity region after a selective growth of a thick field oxide layer, a base region, an emitter region and a collector contact region are formed in surface portions of the lightly doped n-type single crystal silicon layer, and the single crystal silicon layer is not affected by the heat during the growth of the thick field oxide layer, and has a flat zone constant in dopant concentration regardless of the thickness thereof.
摘要翻译：双极晶体管具有在厚电场氧化物层，基极区域，发射极区域和集电极的选择性生长之后在形成于重掺杂n型杂质区域的凹部中外延生长的轻掺杂n型单晶硅层接触区域形成在轻掺杂n型单晶硅层的表面部分中，并且单晶硅层不受厚场氧化物层生长期间的热的影响，并且在掺杂浓度中具有平坦区域恒定而不管其厚度如何。

18. 发明授权

US06404038B1 Complementary vertical bipolar junction transistors fabricated of silicon-on-sapphire utilizing wide base PNP transistors 有权
标题翻译：由使用宽基极PNP晶体管的蓝宝石蓝宝石构成的互补垂直双极结晶体管
公开(公告)号：US06404038B1
公开(公告)日：2002-06-11
申请号：US09517292
申请日：2000-03-02
申请人： Eric N. Cartagena
发明人： Eric N. Cartagena
IPC分类号： H01L27082
CPC分类号： H01L27/1203 , H01L21/82285 , H01L21/86 , H01L27/0826
摘要： A method for fabricating complementary vertical bipolar junction transistors of silicon-on-sapphire in fewer steps than required for true complimentary vertical bipolar junction transistors is disclosed. Initially a thin layer of silicon is grown on a sapphire substrate. The silicon is improved using double solid phase epitaxy. The silicon is then patterned and implanted with P+-type and N+-type dopants. Subsequently a micrometer scale N-type layer is grown that acts as the intrinsic base for both an PNP transistor and as the collector for an NPN transistor. The extrinsic base for the NPN is then formed and the emitter, collector and ohmic contact regions are next selectively masked and implanted. Conductive metal is then formed between protecting oxide to complete the complementary vertical bipolar junction transistors.
摘要翻译：公开了一种用于制造蓝宝石蓝宝石的互补垂直双极结型晶体管的方法，其步骤比真正的互补垂直双极结晶体管所需的步长更少。最初，在蓝宝石衬底上生长一层薄的硅。使用双相固相外延改善了硅。然后将硅图案化并用P +型和N +型掺杂剂注入。随后，生长微米级N型层，其作为PNP晶体管和NPN晶体管的集电极的本征基极。然后形成NPN的外在基极，接着选择性地掩蔽和植入发射极，集电极和欧姆接触区域。然后在保护氧化物之间形成导电金属，以完成互补的垂直双极结型晶体管。

19. 发明授权

US06242794B1 Self-aligned symmetric intrinsic device 有权
标题翻译：自对准对称固有装置
公开(公告)号：US06242794B1
公开(公告)日：2001-06-05
申请号：US09311149
申请日：1999-05-13
申请人： Paul Enquist
发明人： Paul Enquist
IPC分类号： H01L27082
CPC分类号： H01L29/7722 , H01L29/66242 , H01L29/66318 , H01L29/7371
摘要： A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.
摘要翻译：一种半导体器件及其制造方法。发射极区域与基极区域对称地形成为自对中和自对准。使用前端处理技术，集电极形成为与基极区域和发射极区域对称自对准。可以使用背面处理技术使收集器区域进一步与基部区域自身居中。自对准和自对中结构的对称结构实际上消除了器件中的寄生元件，显着提高器件性能。该器件的可扩展性约为0.1微米。该方法还提供对称设备的商业制造所需的设备特性的可再现性和可重复性。

20. 发明授权

US06806555B2 Semiconductor component and method for fabricating it 有权
标题翻译：半导体元件及其制造方法
公开(公告)号：US06806555B2
公开(公告)日：2004-10-19
申请号：US10144213
申请日：2002-05-13
申请人： Jakob Huber , Wolfgang Klein
发明人： Jakob Huber , Wolfgang Klein
IPC分类号： H01L27082
CPC分类号： H01L29/0821 , H01L21/8224 , H01L27/0825
摘要： A semiconductor component and a method for fabricating it includes a substrate and an epitaxial layer situated thereon and integrating at least a first and a second bipolar component in the layer. The first and second bipolar components have a buried layer and different collector widths. The buried layer of the second component has a larger layer thickness than that of the first component; exactly one epitaxial layer is provided. The different collector widths produced as a result thereof are influenced by the outdiffusion of the dopant of the buried layers by other substances.
摘要翻译：半导体部件及其制造方法包括基板和位于其上的外延层，并且在该层中至少集成第一和第二双极部件。第一和第二双极组件具有掩埋层和不同的集电极宽度。第二部件的掩埋层的厚度大于第一部件的厚度; 正好提供一个外延层。作为其结果产生的不同的集电极宽度受到其它物质对掩埋层的掺杂剂的扩散的影响。

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