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11. 发明申请

US20020136044A1 INTEGRATED CIRCUIT WITH ANALOG OR MULTILEVEL STORAGE CELLS AND USER-SELECTABLE SAMPLING FREQUENCY 有权
标题翻译：具有模拟或多存储电池的集成电路和用户可选择的采样频率
公开(公告)号：US20020136044A1
公开(公告)日：2002-09-26
申请号：US09343117
申请日：1999-06-29
发明人： CARL W. WERNER , ANDREAS M. HAEBERLI , LEON SEA JIUNN WONG , CHENG-YUAN MICHAEL WANG , HOCK C. SO , SAU C. WONG
IPC分类号： G11C007/02 , G11C027/00
CPC分类号： G11C11/5642 , G11C5/145 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C16/12 , G11C16/30 , G11C16/32 , G11C27/005 , G11C27/02 , G11C27/026
摘要： Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells (416) capable of multilevel or analog voltage level storage. The integrated circuit may store or record information in analog or digital form, or both. Information is stored in and retrieved from the integrated circuit using a user-selected sampling frequency. The user's selection of the sampling frequency is stored within the integrated circuit.
摘要翻译：技术用于在诸如集成电路的存储器单元的介质中存储信息，并且还从介质检索信息。集成电路包括能够进行多电平或模拟电压电平存储的非易失性存储单元（416）。集成电路可以以模拟或数字形式或两者存储或记录信息。使用用户选择的采样频率将信息存储在集成电路中并从集成电路检索。用户对采样频率的选择存储在集成电路内。

12. 发明申请

US20020110014A1 Recording system, data recording apparatus, memory apparatus, and data recording method 有权
标题翻译：记录系统，数据记录装置，存储装置和数据记录方法
公开(公告)号：US20020110014A1
公开(公告)日：2002-08-15
申请号：US10118402
申请日：2002-04-08
申请人： SONY CORPORATION
发明人： Shigeo Araki , Kenichi Nakanishi
IPC分类号： G11C027/00
CPC分类号： G06F3/0613 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F12/0607 , G06F2212/2022 , G11C7/16 , G11C7/22 , G11C8/12 , G11C2207/16
摘要： Data 30 is recorded into storages 0 to 3 in parallel. Writing sectors are selected from a plurality of clusters so that the sectors are continuously arranged in each cluster, and the data is simultaneously written into the selected sectors. In the case where the sectors numbered in the original order are written into the storages 0 to 3 in parallel, the data of No. 0 is recorded into the head sector in the cluster of the storage 0, the data of No. 16 is recorded into the head sector in the cluster of the storage 1, the data of No. 32 is recorded into the head sector in the cluster of the storage 2, and the data of No. 48 is recorded into the head sector in the cluster of the storage 3, respectively. Thus, the data is arranged in the original order into the cluster constructed in the same storage. When the data is written into a plurality of storages in parallel, the compatibility of the file format of the written data is held.
摘要翻译：数据30被并行地记录到存储器0到3中。从多个簇中选择写入扇区，使得扇区被连续排列在每个簇中，并且数据被同时写入所选择的扇区。在以原始顺序编号的扇区并行地写入存储器0至3的情况下，将0号的数据记录在存储器0的簇中的头扇区中，记录16号的数据将32号的数据记录在存储器2的簇中的头扇区中，并将48号的数据记录在存储器2的簇中的头扇区中存储3个。因此，数据以原始顺序排列到同一存储器中构建的集群中。当数据被并行写入多个存储器时，保持写入数据的文件格式的兼容性。

13. 发明申请

US20020089867A1 Analog storage semiconductor memory 审中-公开
标题翻译：模拟存储半导体存储器
公开(公告)号：US20020089867A1
公开(公告)日：2002-07-11
申请号：US09874987
申请日：2001-06-07
发明人： Makoto Nagasue
IPC分类号： G11C027/00
CPC分类号： G11C27/005
摘要： An analog storage flash memory by which sufficient write accuracy can be obtained even when the write speed of the memory cell transistor disperses due to manufacturing dispersion or other reasons. A read voltage adjustment circuit outputs the read voltage generated by a read voltage generation circuit as is, or drops and outputs the read voltage. A write voltage adjustment circuit outputs the write voltage generated by a write voltage generation circuit as is, or drops and outputs the write voltage. A write control circuit repeats the write operation at the write voltage Vw until the memory cell transistor turns OFF at the read voltage VrnullnullVr in the first write cycle, and repeats the write operation at the write voltage VwnullnullVw until the memory transistor turns OFF at the read voltage Vr in the second write cycle.
摘要翻译：即使当存储单元晶体管的写入速度由于制造分散或其他原因而分散时，也能够获得足够的写入精度的模拟存储闪存。读取电压调整电路按原样输出由读取电压产生电路产生的读取电压，或者降低并输出读取的电压。写入电压调整电路输出由写入电压产生电路产生的写入电压，或者降低并输出写入电压。写入控制电路以写入电压Vw重复写入操作，直到存储单元晶体管在第一写入周期中以读取电压Vr-DELTAVr变为OFF，并以写入电压Vw-DELTAVw重复写入操作，直到存储晶体管转为在第二写入周期中的读取电压Vr处截止。

14. 发明申请

US20040057269A1 Arrangement of integrated circuits in a memory module 审中-公开
公开(公告)号：US20040057269A1
公开(公告)日：2004-03-25
申请号：US10674240
申请日：2003-09-29
发明人： Jayesh R. Bhakta , Robert S. Pauley JR.
IPC分类号： G11C027/00
CPC分类号： H05K1/181 , H05K1/0266 , H05K2201/09409 , H05K2201/09709 , H05K2201/10689 , Y02P70/611
摘要： Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.

15. 发明申请

US20040057268A1 Data reproduction device 失效
标题翻译：数据再现装置
公开(公告)号：US20040057268A1
公开(公告)日：2004-03-25
申请号：US10628687
申请日：2003-07-28
申请人： FUJITSU LIMITED
发明人： Toshikazu Kanaoka , Masakazu Taguchi
IPC分类号： G11C027/00
CPC分类号： G11B7/005 , G11B5/012 , G11B5/09 , G11B20/10009 , G11B20/10037 , G11B20/10046 , G11B20/10222 , G11B20/10425 , G11B27/3027 , H03L7/00
摘要： A data reproduction device for sampling a signal reproduced from a recording medium based on a synchronization clock signal synchronized with the reproduced signal includes: an analog-to-digital conversion part converting the reproduced signal into a first digital signal based on a first clock signal; an interpolation part interpolating the first digital signal so that the first digital signal is equalized with a second digital signal sampled based on a second clock signal having a frequency n times the frequency of the first clock signal; an optimum phase detection part receiving the output of the interpolation part and detecting the phase error between the optimum point of the reproduced signal and the synchronization clock signal; a phase correction part correcting the phase of the reproduced signal based on the phase error; and an information data start detection part detecting the start of information data based on the phase error.
摘要翻译：根据与再现信号同步的同步时钟信号，对从记录介质再现的信号进行采样的数据再现装置包括：模数转换部分，基于第一时钟信号将再现信号转换为第一数字信号; 内插部分内插第一数字信号，使得第一数字信号与基于具有n倍于第一时钟信号频率的频率的第二时钟信号采样的第二数字信号相等; 接收内插部分的输出并检测再生信号的最佳点与同步时钟信号之间的相位误差的最佳相位检测部分; 相位校正部，基于相位误差校正再现信号的相位; 以及信息数据开始检测部，其基于相位误差来检测信息数据的开始。

16. 发明申请

US20040057267A1 Semiconductor memory device, and method of controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20040057267A1
公开(公告)日：2004-03-25
申请号：US10623544
申请日：2003-07-22
申请人： FUJITSU LIMITED
发明人： Shinya Fujioka
IPC分类号： G11C027/00
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.
摘要翻译：内部电压发生器激活时，产生内部电压供给内部电路。操作内部电压发生器消耗预定量的功率。响应来自外部的控制信号，入口电路使内部电压发生器失活。内部电压发生器未激活时，不产生内部电压，从而降低功耗。因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器记忆细胞。

17. 发明申请

US20040057266A1 Semiconductor memory device, electronic card and electronic device 有权
标题翻译：半导体存储器件，电子卡和电子器件
公开(公告)号：US20040057266A1
公开(公告)日：2004-03-25
申请号：US10620849
申请日：2003-07-16
申请人： Kabushiki Kaisha Toshiba
发明人： Hideo Mukai
IPC分类号： G11C027/00
CPC分类号： H01L27/112 , G11C5/063 , G11C7/18 , G11C16/0483 , G11C2207/005 , H01L27/115
摘要： A semiconductor memory device comprises a cell array including bit lines arranged at a uniform pitch; and a plurality of bit line selection transistors connected to respective bit line ends for selectively connecting the bit line to a sense amp. The bit line selection transistors are translationally arrayed in a direction perpendicular to the bit line at an average array pitch greater than eight times the pitch of the bit lines.
摘要翻译：一种半导体存储器件，包括一个单元阵列，包括以均匀间距排列的位线; 以及连接到各个位线端的多个位线选择晶体管，用于选择性地将位线连接到读出放大器。位线选择晶体管以垂直于位线的方向平移排列，平均排列间距大于位线的间距的八倍。

18. 发明申请

US20030043619A1 Single ended row select for a MRAM device 有权
公开(公告)号：US20030043619A1
公开(公告)日：2003-03-06
申请号：US09941646
申请日：2001-08-30
发明人： Tom W. Voshell , Mirmajid Seyyedy
IPC分类号： G11C027/00
CPC分类号： G11C11/16
摘要： A method and apparatus for selecting a rowline in a MRAM device. A rowline select circuit is provided on a first side of each rowline and connects the rowline to ground when a memory cell in the rowline is being written to and to a voltage source when a memory cell in the rowline is being read. A rowline stack select circuit is provided on the second side of each rowline and is connected to one rowline on each plane of memory. When a memory cell is being accessed, the rowline containing that memory cell as well as each other rowline connected to the same rowline stack select circuit are connected to a current source.

19. 发明申请

US20030002312A1 Pore structure for programmable device 有权
标题翻译：可编程器件的孔结构
公开(公告)号：US20030002312A1
公开(公告)日：2003-01-02
申请号：US09896616
申请日：2001-06-30
发明人： Tyler A. Lowrey
IPC分类号： G11C027/00 , H01L021/31
CPC分类号： H01L27/2463 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1691
摘要： In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, the quantity of programmable material is minimized, and the programmable material that is reprogrammed from an amorphous to a crystalline state, and vice versa, is localized on a contact. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact formed on a substrate. A spacer is formed within the opening and a programmable material is formed within the opening such that the spacer reduces the programmable material on the contact. A conductor is formed on the programmable material and the contact transmits to a signal line.
摘要翻译：在一方面，提供一种设置和重新编程可编程设备的状态的设备。在一个方面，可编程材料的量被最小化，并且从无定形重新编程为结晶状态的可编程材料（反之亦然）被定位在触点上。在一方面，提供一种方法，使得通过暴露形成在基底上的接触的电介质形成开口。间隔件形成在开口内，并且可编程材料形成在开口内，使得间隔件减少了接触件上的可编程材料。导体形成在可编程材料上，触点传输到信号线。

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