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1. 发明申请

US20040057264A1 Multibit non-volatile memory and method 有权
标题翻译：多位非易失性存储器和方法
公开(公告)号：US20040057264A1
公开(公告)日：2004-03-25
申请号：US10603426
申请日：2003-06-24
发明人： Jan Van Houdt , Luc Haspeslagh
IPC分类号： G11C027/00
CPC分类号： H01L27/11502 , G11C16/0458 , H01L21/2815 , H01L21/28273 , H01L29/7887 , H01L29/7923
摘要： A memory is described having a semiconductor substrate of a first conductivity type, a first and a second junction region of a second conductivity type, whereby said first and said second junction region are part of respectively a first and a second bitline. A select gate is provided which is part of a wordline running perpendicular to said first and said second bitline. Read, write and erase functions for each cell make use of only two polysilicon layers which simplifies manufacture and each memory cell has at least two locations for storing a charge representing at least one bit.
摘要翻译：描述了具有第一导电类型的半导体衬底，第二导电类型的第一和第二结区的存储器，由此所述第一和第二结区分别是第一和第二位线的一部分。提供选择门，其是垂直于所述第一和所述第二位线的字线的一部分。每个单元的读，写和擦除功能仅使用两个多晶硅层，这简化了制造，每个存储单元具有至少两个用于存储表示至少一个位的电荷的位置。

2. 发明申请

US20040264227A1 Semicondutor integrated circuit and electronic system 失效
标题翻译：半导体集成电路和电子系统
公开(公告)号：US20040264227A1
公开(公告)日：2004-12-30
申请号：US10823581
申请日：2004-04-14
申请人： Renesas Technology Corp.
发明人： Hirotsugu Kojima , Teruo Kitamura
IPC分类号： G11C027/00
CPC分类号： G11C29/12015 , G11C7/1006 , G11C16/0433 , G11C16/0441 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2216/10
摘要： The invention provides a semiconductor integrated circuit for communication control and a wireless communication system using the same realizing reduction in the size of a chip and the size of a module by enabling trimming data to be written into a nonvolatile memory without increasing the number of external terminals. A rewritable nonvolatile memory is provided in a semiconductor integrated circuit, characteristics of circuits including an electronic part are measured and trimming data for correcting variations in the characteristics is stored in the nonvolatile memory. A pin and an interface circuit such as a test pin and a JTAG interface circuit which are originally provided for the semiconductor integrated circuit also serve as an input pin and an interface circuit for sending and storing the trimming data to the nonvolatile memory.
摘要翻译：本发明提供了一种用于通信控制的半导体集成电路和使用该半导体集成电路的无线通信系统，其通过使修整数据能够被写入非易失性存储器而不增加外部端子的数量而实现芯片尺寸的减小和模块的尺寸。在半导体集成电路中提供可重写的非易失性存储器，测量包括电子部件的电路的特性，并且将用于校正特性变化的修整数据存储在非易失性存储器中。最初为半导体集成电路提供的针脚和接口电路如测试针和JTAG接口电路也用作输入引脚和用于向微处理器发送和存储修整数据的接口电路。

3. 发明申请

US20040057265A1 Method of controlling an electronic non-volatile memory and associated device 有权
标题翻译：控制电子非易失性存储器及相关装置的方法
公开(公告)号：US20040057265A1
公开(公告)日：2004-03-25
申请号：US10616413
申请日：2003-07-09
申请人： STMicroelectronics SA , Laboratoire Materiaux et Microelectronique de Provence (L2MP)
发明人： Jean-Michel Mirabel , Rachid Bouchakour , Pierre Canet , Romain Laffont , Juliano Razafindramora
IPC分类号： G11C027/00
CPC分类号： G11C16/14
摘要： A memory cell in an EEPROM includes a floating gate transistor that includes a first conducting terminal and a control gate. A method of controlling the memory cell includes setting a state of the memory cell by simultaneously applying voltage pulses of opposite polarities respectively to the first conducting terminal and to the control gate. The voltage pulses including a first portion having a first slope and a second portion having a second slope, wherein the second slope is based upon the polarities of the voltage pulses. The method allows the amplitude of the voltage pulses to be reduced.
摘要翻译： EEPROM中的存储单元包括具有第一导电端子和控制栅极的浮栅晶体管。控制存储单元的方法包括：通过同时向第一导电端子和控制栅极施加相反极性的电压脉冲来设定存储单元的状态。电压脉冲包括具有第一斜率的第一部分和具有第二斜率的第二部分，其中第二斜率基于电压脉冲的极性。该方法允许降低电压脉冲的幅度。

4. 发明申请

US20040145933A1 Semiconductor memory test apparatus and method for address generation for defect analysis 有权
标题翻译：用于缺陷分析的地址产生的半导体存储器测试装置和方法
公开(公告)号：US20040145933A1
公开(公告)日：2004-07-29
申请号：US10477782
申请日：2003-11-12
发明人： Tomoyuki Yamane
IPC分类号： G11C027/00
CPC分类号： G11C29/56004 , G11C29/26 , G11C29/56 , G11C2029/5606
摘要： There is disclosed a semiconductor memory test apparatus capable of easily generating an address to be input into a failure analysis memory for testing during interleave operation of a memory device having a burst function between banks. Each of the registers corresponding to DUT banks holds a line address of the corresponding bank. When a start row address of one of the banks is input to the DUT, a line address of the same bank as the start row address is read out from the register corresponding to the bank and output to a failure analysis memory together with the start row address. Furthermore, during burst operation of the bank, it is possible to output the line address to the failure analysis memory together the same row address as the memory device generated by calculating the start row address for each clock cycle.
摘要翻译：公开了一种半导体存储器测试装置，其能够容易地产生要输入到故障分析存储器中的地址，以便在具有银行之间的突发功能的存储器件的交错操作期间进行测试。对应于DUT库的每个寄存器保存相应存储体的行地址。当一个存储体的起始行地址被输入到DUT时，从对应于存储体的寄存器中读出与起始行地址相同的存储体的行地址，并与起始行一起输出到故障分析存储器地址。此外，在存储体的脉冲串操作期间，可以将故障分析存储器的行地址输出到与通过计算每个时钟周期的起始行地址生成的存储器件相同的行地址。

5. 发明申请

US20040114409A1 Fast analog sampler with great memory depth 有权
标题翻译：快速模拟采样器，具有很好的记忆深度
公开(公告)号：US20040114409A1
公开(公告)日：2004-06-17
申请号：US10475222
申请日：2003-10-20
发明人： Dominique Breton , Eric Delagnes
IPC分类号： G11C027/00
CPC分类号： G11C27/024 , G11C27/02 , G11C27/04
摘要： An analog sampler (1) for recording analog data carried by a bus (5) comprises an array (10) of recording cells (2) arranged in rows (13) and columns (12). Each cell (2) has an analog input (3) coupled to the bus (5) by means of a switch (21a) having a controlling digital input (23). The device is characterized in that it comprises a delay line (9) associated with each column (12), coupled to the shift register. Successive outputs (11) of the line (9) are coupled to each of the digital inputs (11-1) of the cells (2) of the column (12) such that at any moment there is no more than one switch of a single recording switch. The signal is thus not disrupted by noise.
摘要翻译：用于记录由总线（5）承载的模拟数据的模拟采样器（1）包括排列成行（13）和列（12）的记录单元（2）的阵列（10）。每个单元（2）具有通过具有控制数字输入（23）的开关（21a）耦合到总线（5）的模拟输入（3）。该装置的特征在于它包括与每个列（12）相关联的延迟线（9），耦合到移位寄存器。线（9）的连续输出（11）耦合到列（12）的单元（2）的每个数字输入（11-1），使得在任何时刻不存在一个以上的开关单记录开关。因此，信号不会被噪声中断。

6. 发明申请

US20040037103A1 Split word line ternary CAM architecture 失效
标题翻译：分割字线三元CAM架构
公开(公告)号：US20040037103A1
公开(公告)日：2004-02-26
申请号：US10226339
申请日：2002-08-23
发明人： Daniel R. Loughmiller
IPC分类号： G11C027/00
CPC分类号： G11C15/04
摘要： A content addressable memory (CAM) cell is disclosed having a split word line scheme and having binary and ternary storage capability. The cell comprises a pair of storage devices, a comparing circuit, a pair of memory access devices having gates controlled by respective word lines, a pair of bit lines for writing to and reading from the storage devices, or pair of search lines. Furthermore, the dynamic CAM cell utilizes a folded bit line architecture with a single sense amplifier sensing inputs from the pair of bit lines.
摘要翻译：公开了一种具有分割字线方案并具有二进制和三进制存储能力的内容可寻址存储器（CAM）单元。该单元包括一对存储装置，比较电路，具有由相应字线控制的门的一对存储器存取装置，用于对存储装置进行写入和读取的一对位线或一对搜索线。此外，动态CAM单元利用具有感测来自该对位线的输入的单个读出放大器的折叠位线架构。

7. 发明申请

US20020196647A1 Resistive cross point array of short-tolerant memory cells 有权
标题翻译：电阻式交叉点阵列的短耐受记忆细胞
公开(公告)号：US20020196647A1
公开(公告)日：2002-12-26
申请号：US09887314
申请日：2001-06-22
发明人： Janice H. Nickel
IPC分类号： G11C027/00
CPC分类号： H01L27/222 , G11C11/16 , G11C13/0004 , G11C13/0014 , G11C13/0016 , G11C17/16 , G11C17/165 , H01L43/12
摘要： A data storage device includes a resistive cross point array of memory cells. Each memory cell includes a memory element and electrically conductive hard mask material on the memory element. The data storage device may be a Magnetic Random Access Memory (nullMRAMnull) device.
摘要翻译：数据存储装置包括存储单元的电阻交叉点阵列。每个存储单元包括存储元件和存储元件上的导电硬掩模材料。数据存储装置可以是磁随机存取存储器（“MRAM”）装置。

8. 发明申请

US20040252536A1 Cache cell with masking 有权
标题翻译：具有掩蔽的缓存单元
公开(公告)号：US20040252536A1
公开(公告)日：2004-12-16
申请号：US10862057
申请日：2004-06-04
申请人： STMicroelectronics S.A.
发明人： Richard Ferrant
IPC分类号： G11C027/00
CPC分类号： G11C15/04
摘要： A CAM cell with masking made in the form of an integrated circuit, including a first storage cell including a first transistor, first and second inverters in anti-parallel, and a second transistor; a comparison cell, including third and fourth transistors controlling a fifth transistor, connected in series with a sixth inhibiting transistor to a result line; and a second storage cell, including a seventh transistor in series with two inverters in anti-parallel and an eighth transistor, the second storage cell controlling the inhibiting transistor. The first, second, seventh, and eighth transistors may be N-channel transistors, and the third, fourth, fifth, and sixth transistors may be P-channel transistors.
摘要翻译：具有以集成电路形式形成的掩蔽的CAM单元，包括：第一存储单元，包括第一晶体管，反并联的第一和第二反相器以及第二晶体管; 比较单元，包括控制第五晶体管的第三和第四晶体管，与第六抑制晶体管串联连接到结果行; 以及第二存储单元，其包括与反并联的两个反相器串联的第七晶体管和第八晶体管，所述第二存储单元控制所述抑制晶体管。第一，第二，第七和第八晶体管可以是N沟道晶体管，并且第三，第四，第五和第六晶体管可以是P沟道晶体管。

9. 发明申请

US20040008533A1 Associative memory 失效
标题翻译：关联记忆
公开(公告)号：US20040008533A1
公开(公告)日：2004-01-15
申请号：US10615910
申请日：2003-07-10
申请人： FUJITSU LIMITED
发明人： Miki Yanagawa
IPC分类号： G11C027/00
CPC分类号： G11C15/04 , G11C15/00
摘要： A memory cell matrix with a plurality of associative memory cells and match lines are respectively divided into two in the direction of the match line. A first memory cell matrix is provided with a match line pre-charge circuit that pre-charges the match line in the first memory cell matrix, and a match line sense amplifier that detects the potential of the match line. A second memory cell matrix is provided with a match line pre-charge circuit that pre-charges the match line in the second memory cell matrix, a match line sense amplifier that detects the potential of the match line in the second memory cell matrix, and a second match line control circuit. The second match line control circuit operates the match line pre-charge circuit in the second memory cell matrix, to pre-charge the match line, only when the data comparison result in the first memory cell matrix indicates agreement.
摘要翻译：具有多个关联存储器单元和匹配线的存储单元矩阵分别在匹配线的方向上分成两个。第一存储单元矩阵设置有预充电第一存储单元矩阵中的匹配线的匹配线预充电电路和检测匹配线的电位的匹配线读出放大器。第二存储单元矩阵设置有预充电第二存储单元矩阵中的匹配线的匹配线预充电电路，检测第二存储单元矩阵中匹配线的电位的匹配线读出放大器，以及第二匹配线控制电路。第二匹配线控制电路在第二存储单元矩阵中操作匹配线预充电电路，以仅在第一存储单元矩阵中的数据比较结果指示一致时对该匹配线进行预充电。

10. 发明申请

US20030161171A1 Adjustable charge pump circuit 有权
标题翻译：可调电荷泵电路
公开(公告)号：US20030161171A1
公开(公告)日：2003-08-28
申请号：US10382333
申请日：2003-03-04
申请人： INVOX TECHNOLOGY, a California Corporation
发明人： Andreas M. Haeberli , Sau C. Wong , Hock C. So , Carl W. Werner , Cheng-Yuan Michael Wang , Leon Sea Jiunn Wong
IPC分类号： G11C027/00
CPC分类号： G11C11/5642 , G11C5/145 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C16/12 , G11C16/30 , G11C16/32 , G11C27/005 , G11C27/02 , G11C27/026
摘要： An integrated circuit detects the voltage level of the supply voltage to the integrated circuit. Circuity on the integrated circuit including the charge pump circuity adjusts to operate more effectively or efficiently at the voltage level of the supply voltage.
摘要翻译：集成电路检测到集成电路的电源电压的电平。包括电荷泵电路在内的集成电路的电流调整为在电源电压的电压电平下更有效或更有效地工作。

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