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11. 发明申请

US20090135038A1 Sigma Delta Modulator Summing Input, Reference Voltage, And Feedback 有权
标题翻译： Sigma Delta调制器求和输入，参考电压和反馈
公开(公告)号：US20090135038A1
公开(公告)日：2009-05-28
申请号：US11946060
申请日：2007-11-28
申请人： ABHIJIT KUMAR DAS
发明人： ABHIJIT KUMAR DAS
IPC分类号： H03M3/04 , H03M1/12
CPC分类号： H03M3/42 , H03M3/43 , H03M3/438
摘要： A multibit sigma delta modulator for conveting an analog input signal (Vin) into a multibit digital output signal is disclosed. In one embodiment, the multibit sigma modulator includes a first analog filter for filtering the analog input error signal, a quantizer including multiple single bit noise shaped modulators for quantizing the filtered analog input error signal outputted by the first analog filter for generating a multibit digital output signal, and a first feedback arrangement with at least one digital-to-analog converter (DAC) coupled to the quantizer for supplying to the first analog filter at least one quantizer feedback signal based on the multibit digital output signal.
摘要翻译：公开了一种用于将模拟输入信号（Vin）转换为多位数字输出信号的多位Σ-Δ调制器。在一个实施例中，多位Σ调制器包括用于对模拟输入误差信号进行滤波的第一模拟滤波器，包含多个单比特噪声整形调制器的量化器，用于量化由第一模拟滤波器输出的滤波的模拟输入误差信号，用于产生多位数字输出信号以及与至少一个耦合到量化器的数模转换器（DAC）的第一反馈装置，用于向第一模拟滤波器提供基于多位数字输出信号的至少一个量化器反馈信号。

12. 发明授权

US06271782B1 Delta-sigma A/D converter 有权
标题翻译： Delta-sigma A / D转换器
公开(公告)号：US06271782B1
公开(公告)日：2001-08-07
申请号：US09541221
申请日：2000-04-03
申请人： Jesper Steensgaard-Madsen
发明人： Jesper Steensgaard-Madsen
IPC分类号： H03M300
CPC分类号： H03M3/416 , H03M1/167 , H03M3/42 , H03M3/424 , H03M3/46
摘要： A delta-sigma modulator comprising a first quantizer providing a first digital signal d0(k) representing the input signal g(t); a loop filter with input signal paths; a loop quantizer providing a corrective digital signal d1(k) representing the loop filter's output signal y(t); an array of feedback DACs D/A converting the sum d(k)=df(k)=d0(k)+d1(k) of the first and the corrective digital signals and injecting feedback signals into the loop filter. The loop filter's input node is applied the difference of the input signal g(t) and the global analog feedback signal a3(t). The global feedback signal a3(t) is delayed several clock cycles with respect to the digital output signal d(k). The delay is used to carry out mismatch-shaping and deglitching algorithms in the feedback DACs. The feedback DACs' different delays and gain coefficients are designed such that the modulator is stable. The filter's input signal paths and the compensating DAC are designed such that the gain from the input signal g(t) to the loop quantizer is small, ideally zero. Thus, the loop quantizer's resolving range can be a fraction of the first quantizer's resolving range, whereby the output signal's d(k) resolution can be much higher than the individual resolutions of d0(k) and d1(k). The delta-sigma modulator is well suited for the implementation of high-resolution wide-bandwidth A/D converters. Important applications include digital communication systems.
摘要翻译：一种Δ-Σ调制器，包括：第一量化器，提供表示输入信号g（t）的第一数字信号d0（k）; 具有输入信号路径的环路滤波器; 提供表示环路滤波器的输出信号y（t）的校正数字信号d1（k）的环路量化器; 将第一和校正数字信号的和d（k）= df（k）= d0（k）+ d1（k）转换为反馈DAC的阵列D / A并将反馈信号注入到环路滤波器中。环路滤波器输入节点应用输入信号g（t）和全局模拟反馈信号a3（t）的差值。全局反馈信号a3（t）相对于数字输出信号d（k）被延迟几个时钟周期。该延迟用于在反馈DAC中执行失配整形和去角化算法。反馈DAC的不同延迟和增益系数被设计成使得调制器稳定。滤波器的输入信号路径和补偿DAC被设计成使得从输入信号g（t）到环路量化器的增益小，理想地为零。因此，环路量化器的分辨率范围可以是第一量化器的分辨率范围的一小部分，由此输出信号的d（k）分辨率可以远高于d0（k）和d1（k）的各个分辨率.Δ-Σ 调制器非常适合实现高分辨率宽带宽A / D转换器。重要的应用包括数字通信系统。

13. 发明申请

US20180343013A1 SIGMA DELTA MODULATOR, INTEGRATED CIRCUIT AND METHOD THEREFOR 审中-公开
公开(公告)号：US20180343013A1
公开(公告)日：2018-11-29
申请号：US15926442
申请日：2018-03-20
申请人： NXP B.V.
发明人： Lucien Johannes BREEMS , Muhammed BOLATKALE , Chenming ZHANG
IPC分类号： H03M3/00
CPC分类号： H03M3/322 , H03M3/37 , H03M3/42 , H03M3/464 , H03M3/496
摘要： A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal, a first summing junction configured to subtract a feedback analog signal from the input analog signal, a loop filter configured to filter an output signal from the first summing junction: an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC includes multiple per-bit parallel loops, each loop configured to provide a per-bit current summation of the filtered analog output signal such that an output of the multiple per-bit parallel loops is a multi-bit quantization digital output signal.

14. 发明授权

US09590654B2 Signal modulation circuit 有权
标题翻译：信号调制电路
公开(公告)号：US09590654B2
公开(公告)日：2017-03-07
申请号：US14594329
申请日：2015-01-12
申请人： Onkyo Corporation
发明人： Yoshinori Nakanishi , Tsuyoshi Kawaguchi , Mamoru Sekiya
IPC分类号： H03M3/00
CPC分类号： H03M3/324 , H03M3/348 , H03M3/358 , H03M3/42
摘要： Provided is a circuit which can correct an output state in real time and reduce influences of distortion/noise components generated by a delay device. A signal modulation circuit includes a subtractor, an integrator, a phase inverting circuit, a DFF for while inserting a zero level at timing synchronous with the clock signal, delaying and quantizing the signal, a ternary signal generating circuit for generating a ternary signal for selectively driving a load connected to a single power supply into ternary conductive states including a positive current on-state, a negative current on-state, and an off-state, a driver circuit for generating a driving signal for driving a load, and a feedback circuit for feeding back the driving signal from the driver circuit to the input signal.
摘要翻译：提供了可以实时校正输出状态并减少由延迟装置产生的失真/噪声分量的影响的电路。信号调制电路包括减法器，积分器，相位反相电路，用于在与时钟信号同步的定时插入零电平的DFF，对信号进行延迟和量化;三态信号发生电路，用于选择性地产生三态信号将连接到单个电源的负载驱动为包括正电流导通状态，负电流导通状态和截止状态的三态导通状态，用于产生用于驱动负载的驱动信号的驱动电路和反馈用于将驱动信号从驱动电路反馈到输入信号的电路。

15. 发明授权

US09442141B2 Analogue-to-digital converter 有权
标题翻译：模数转换器
公开(公告)号：US09442141B2
公开(公告)日：2016-09-13
申请号：US14150164
申请日：2014-01-08
申请人： QUALCOMM TECHNOLOGIES INTERNATIONAL, LTD.
发明人： Gerald Miaille , Michael John Story , Dimitrios Mavridis
IPC分类号： G01R23/02 , G01R23/00 , H03M3/00
CPC分类号： G01R23/00 , H03M3/42 , H03M3/44 , H03M3/454 , H03M3/466 , H03M3/47
摘要： An analogue-to-digital converter for converting an analogue input signal into a digital output signal, the analogue-to-digital converter including two conversion paths, each configured to receive a version of the analogue input signal and convert it into a digital bit stream, a first feedback loop configured to provide feed-back, to both paths, that is indicative of a difference between the digital bit streams output by the two paths, and a second feedback loop configured to feed-back, to both paths, that is indicative of an average of the digital bit streams output by the two paths.
摘要翻译：一种用于将模拟输入信号转换为数字输出信号的模拟 - 数字转换器，所述模数转换器包括两个转换路径，每个转换路径被配置为接收模拟输入信号的版本并将其转换成数字位流第一反馈回路，其被配置为向两个路径提供表示由两个路径输出的数字位流之间的差异的反馈回路，以及被配置为反馈到两个路径的第二反馈回路，指示由两条路径输出的数字比特流的平均值。

16. 发明授权

US09419642B1 Ultra low power dual quantizer architecture for oversampling delta-sigma modulator 有权
标题翻译：用于过采样Δ-Σ调制器的超低功耗双量化器架构
公开(公告)号：US09419642B1
公开(公告)日：2016-08-16
申请号：US14736419
申请日：2015-06-11
申请人： ANALOG DEVICES, INC.
发明人： Khiem Quang Nguyen
IPC分类号： H03M3/00
CPC分类号： H03M3/344 , H03M3/338 , H03M3/368 , H03M3/42 , H03M3/424 , H03M3/464
摘要： Power consumption of analog-to-digital converters (ADCs) is one important requirement for automotive and consumer devices. One flavor of an ADC is a dual quantizer architecture for oversampling delta-sigma modulators. The dual quantizer delta-sigma modulator has a first quantizer for digitizing the output of the loop filter and a second quantizer for digitizing the input of the quantizer. However, the quantization noise of the second quantizer is a highly correlated signal and significantly degrades the spectrum of the delta-sigma modulator. To address this issue, an improvement to the dual quantizer architecture is made to cancel the quantization noise of the second quantizer that is digitizing the input. Furthermore, the improvement allows the second quantizer to run at a much slower sampling rate than the first quantizer. Advantageously, the improvement provides reduction in power consumption and the overall area of modulator.
摘要翻译：模数转换器（ADC）的功耗是汽车和消费类设备的一个重要要求。 ADC的一种风格是用于过采样delta-sigma调制器的双量化器架构。双量化器Δ-Σ调制器具有用于数字化环路滤波器的输出的第一量化器和用于数字化量化器的输入的第二量化器。然而，第二量化器的量化噪声是高度相关的信号，并显着降低了Δ-Σ调制器的频谱。为了解决这个问题，对双量化器架构进行了改进以消除正在对输入进行数字化的第二量化器的量化噪声。此外，改进允许第二量化器以比第一量化器慢得多的采样速率运行。有利地，该改进提供功率消耗的降低和调制器的总面积。

17. 发明授权

US09350373B1 Analog-to-digital converter and long-term-evolution advanced device and method for analog-to-digital conversion 有权
标题翻译：模数转换器和长期演进用于模数转换的高级器件和方法
公开(公告)号：US09350373B1
公开(公告)日：2016-05-24
申请号：US14741841
申请日：2015-06-17
申请人： MediaTek Inc.
发明人： Tsung-Kai Kao
IPC分类号： H03M3/00 , H03M1/08 , H03M1/12
CPC分类号： H03M1/0854 , H03M1/12 , H03M3/352 , H03M3/42 , H03M3/45 , H03M3/458
摘要： An analog-to-digital conversion that converts an input signal to an output signal by using multiple analog-to-digital converting circuits. A first analog-to-digital converting circuit generates a first signal based on the input signal and further outputs a feature signal of a first quantization error of the first analog-to-digital converting circuit. A second analog-to-digital converting circuit generates a second signal based on the input signal and the feature signal. The output combiner combines the first signal and the second signal to generate the output signal and thereby to reduce a quantization error factor in the output signal that is due to the first quantization error.
摘要翻译：通过使用多个模数转换电路将输入信号转换为输出信号的模数转换。第一模数转换电路基于输入信号产生第一信号，并且还输出第一模数转换电路的第一量化误差的特征信号。第二模拟 - 数字转换电路基于输入信号和特征信号产生第二信号。输出组合器组合第一信号和第二信号以产生输出信号，从而减少由于第一量化误差而导致的输出信号中的量化误差因子。

18. 发明授权

US09143158B2 Sigma-delta modulator 有权
标题翻译： Sigma-delta调制器
公开(公告)号：US09143158B2
公开(公告)日：2015-09-22
申请号：US14268409
申请日：2014-05-02
申请人： NXP B.V.
发明人： Lucien Johannes Breems
IPC分类号： H03M3/00
CPC分类号： H03M3/39 , H03M3/412 , H03M3/42 , H03M3/454
摘要： A sigma-delta modulator (300) comprising a first filter stage (304); a second filter stage (306) in series with the first filter stage (304); a first feedback path (311) between the output of the second filter stage (306) and the input to the second filter stage (306), the first feedback (311) comprising a first gain stage (308, 308′) such that the first feedback path (311) is configured to provide a first gain value; and a second feedback path (313) between the output of the second filter stage (306) and the input to the first filter stage (304), the second feedback path (313) comprising a second gain stage (309; 310′) such that the second feedback path (313) is configured to provide a second gain value. The first gain value is different to the second gain value.
摘要翻译：包括第一滤波器级（304）的Σ-Δ调制器（300）与所述第一过滤器级（304）串联的第二过滤器级（306）; 在第二滤波器级（306）的输出与第二滤波级（306）的输入端之间的第一反馈路径（311），第一反馈（311）包括第一增益级（308,308'），使得第一反馈路径（311）被配置为提供第一增益值; 以及在第二滤波器级（306）的输出与第一滤波级（304）的输入之间的第二反馈路径（313），第二反馈路径（313）包括第二增益级（309; 310'），第二反馈路径（313）被配置为提供第二增益值。第一增益值与第二增益值不同。

19. 发明申请

US20150207519A1 SIGNAL MODULATION CIRCUIT 有权
标题翻译：信号调制电路
公开(公告)号：US20150207519A1
公开(公告)日：2015-07-23
申请号：US14594329
申请日：2015-01-12
申请人： Onkyo Corporation
发明人： Yoshinori NAKANISHI , Tsuyoshi KAWAGUCHI , Mamoru SEKIYA
IPC分类号： H03M3/00
CPC分类号： H03M3/324 , H03M3/348 , H03M3/358 , H03M3/42
摘要： Provided is a circuit which can correct an output state in real time and reduce influences of distortion/noise components generated by a delay device. A signal modulation circuit includes a subtractor, an integrator, a phase inverting circuit, a DFF for while inserting a zero level at timing synchronous with the clock signal, delaying and quantizing the signal, a ternary signal generating circuit for generating a ternary signal for selectively driving a load connected to a single power supply into ternary conductive states including a positive current on-state, a negative current on-state, and an off-state, a driver circuit for generating a driving signal for driving a load, and a feedback circuit for feeding back the driving signal from the driver circuit to the input signal.
摘要翻译：提供了可以实时校正输出状态并减少由延迟装置产生的失真/噪声分量的影响的电路。信号调制电路包括减法器，积分器，相位反相电路，用于在与时钟信号同步的定时插入零电平的DFF，对信号进行延迟和量化;三态信号发生电路，用于选择性地产生三态信号将连接到单个电源的负载驱动为包括正电流导通状态，负电流导通状态和截止状态的三态导通状态，用于产生用于驱动负载的驱动信号的驱动电路和反馈用于将驱动信号从驱动电路反馈到输入信号的电路。

20. 发明授权

US4772871A Delta sigma modulator circuit for an analog-to-digital converter 失效
标题翻译：用于模数转换器的ΔΣ调制器电路
公开(公告)号：US4772871A
公开(公告)日：1988-09-20
申请号：US46783
申请日：1987-05-07
申请人： Takao Suzuki , Yasuo Shoji , Yuichi Shiraki
发明人： Takao Suzuki , Yasuo Shoji , Yuichi Shiraki
IPC分类号： H03M3/04 , H03M3/02 , H03M1/00
CPC分类号： H03M3/42
摘要： In a delta-sigma modulator for an A/D converter for modulating an analog input signal to produce a modulated signal of a digital form, a first integrator produces a first integral signal indicative of an integral of the difference between the analog input signal and feedback signal, a first delay element delays the first integral signal by one sampling period, a second integrator produces a second integral signal indicative of an integral of the difference between the output of the first delay element and the feedback signal, a first quantizer produces a two-level signal "1" or "0" depending on whether or not the second integral signal is greater than a predetermined reference, and a second quantizer produces a two-level signal "1" or "0" depending on whether or not the first integral signal is greater than a predetermined reference. An output digital signal is produced in accordance with the outputs of the first and the second quantizers. The feedback signal is also produced in accordance with the outputs of the first and the second quantizers.
摘要翻译：在用于调制模拟输入信号以产生数字形式的调制信号的A / D转换器的Δ-Σ调制器中，第一积分器产生指示模拟输入信号和反馈之间的差的积分的第一积分信号信号，第一延迟元件将第一积分信号延迟一个采样周期，第二积分器产生指示第一延迟元件的输出与反馈信号之间的差的积分的第二积分信号，第一量化器产生二 - 根据第二积分信号是否大于预定参考值，第二量化器根据第一和第二信号“1”或“0”是否产生两级信号“1”或“0” 积分信号大于预定参考值。根据第一和第二量化器的输出产生输出数字信号。还根据第一和第二量化器的输出产生反馈信号。

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