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1. 发明申请

US20170288693A1 CONTINUOUS TIME DELTA-SIGMA MODULATOR WITH A TIME INTERLEAVED QUANTIZATION FUNCTION 审中-公开
公开(公告)号：US20170288693A1
公开(公告)日：2017-10-05
申请号：US15465305
申请日：2017-03-21
申请人： STMicroelectronics International N.V.
发明人： Ashish Sharma Kumar , Rajeev Jain , Chandrajit Debnath
IPC分类号： H03M3/00 , H03M1/00
CPC分类号： H03M3/464 , H03M1/001 , H03M3/42 , H03M3/466 , H03M3/468 , H03M3/494
摘要： A wide band continuous time delta-sigma modulator implements a time interleaved quantization processing operation. The modulator may provide for an inherent finite impulse response filtering in the feedback loop. Additionally, further finite impulse response filtering in each time interleaved feedback path may be provided.

2. 发明授权

US09503120B1 Signal dependent subtractive dithering 有权
标题翻译：信号依赖减法抖动
公开(公告)号：US09503120B1
公开(公告)日：2016-11-22
申请号：US15056315
申请日：2016-02-29
申请人： Analog Devices Global
发明人： Zhichao Tan , Khiem Quang Nguyen
IPC分类号： H03M3/00
CPC分类号： H03M3/328 , H03M3/30 , H03M3/42 , H03M3/424
摘要： A sigma-delta modulator circuit selectively removes a dither signal previously added to an input of a quantizer circuit from the quantizer circuit output when addition of the dither signal causes a digital state change in the quantizer circuit output. Various examples for enabling the selective removal of the dither signal are described. In one embodiment, a second quantizer circuit provides a non-dithered output signal for comparison, by a digital comparator, with the dithered output signal. In another embodiment, a single quantizer circuit provides the dithered and non-dithered output signals in turn, for comparison. A subtraction circuit may remove the dither signal as appropriate. Embodiments enable retention of the improved limit cycle tone reduction achievable via dithering while reducing the need for circuits with increased signal headroom, and associated design complexity and power dissipation.
摘要翻译：当加入抖动信号导致量化器电路输出中的数字状态改变时，Σ-Δ调制器电路从量化器电路输出中选择性地去除先前添加到量化器电路的输入的抖动信号。描述了能够选择性地去除抖动信号的各种示例。在一个实施例中，第二量化器电路提供非抖动输出信号，用于通过数字比较器与抖动输出信号进行比较。在另一个实施例中，单个量化器电路依次提供抖动和不抖动的输出信号，用于比较。减法电路可以适当地去除抖动信号。实施例使得能够保持通过抖动可实现的改进的限制循环音调降低，同时减少对具有增加的信号净空的电路的需要，以及相关的设计复杂性和功率耗散。

3. 发明申请

US20140333462A1 Sigma-Delta Modulator 有权
标题翻译： Σ-Δ调制器
公开(公告)号：US20140333462A1
公开(公告)日：2014-11-13
申请号：US14268409
申请日：2014-05-02
申请人： NXP B.V.
发明人： Lucien Johannes Breems
IPC分类号： H03M3/00
CPC分类号： H03M3/39 , H03M3/412 , H03M3/42 , H03M3/454
摘要： A sigma-delta modulator (300) comprising a first filter stage (304); a second filter stage (306) in series with the first filter stage (304); a first feedback path (311) between the output of the second filter stage (306) and the input to the second filter stage (306), the first feedback (311) comprising a first gain stage (308, 308′) such that the first feedback path (311) is configured to provide a first gain value; and a second feedback path (313) between the output of the second filter stage (306) and the input to the first filter stage (304), the second feedback path (313) comprising a second gain stage (309; 310′) such that the second feedback path (313) is configured to provide a second gain value. The first gain value is different to the second gain value.
摘要翻译：包括第一滤波器级（304）的Σ-Δ调制器（300）与所述第一过滤器级（304）串联的第二过滤器级（306）; 在第二滤波器级（306）的输出与第二滤波级（306）的输入端之间的第一反馈路径（311），第一反馈（311）包括第一增益级（308,308'），使得第一反馈路径（311）被配置为提供第一增益值; 以及在第二滤波器级（306）的输出与第一滤波级（304）的输入之间的第二反馈路径（313），第二反馈路径（313）包括第二增益级（309; 310'），第二反馈路径（313）被配置为提供第二增益值。第一增益值与第二增益值不同。

4. 发明申请

US20020180629A1 Delta-sigma modulator 有权
标题翻译： Delta-Σ调制器
公开(公告)号：US20020180629A1
公开(公告)日：2002-12-05
申请号：US10101263
申请日：2002-03-18
申请人： ARCHIC TECH. CORP.
发明人： Shen-Iuan Liu , Chien-Hung Kuo , Tzu-Chien Hsueh , Hsiang-Hui Chang
IPC分类号： H03M003/00
CPC分类号： H03M1/066 , H03M3/42 , H03M3/464
摘要： The present invention provides a delta-sigma modulator for converting an external analog signal to a digital output signal. The delta-sigma modulator comprises a first filter circuit, a second filter circuit, a one-bit quantization, a multi-bit quantization, a digital-to-analog converter, and a digital filter. The first filter circuit outputs a first analog signal according to the external analog signal and an one-bit output signal. The second filter circuit outputs a third analog signal according to the first analog signal and a second analog signal. The one-bit quantization converts the third analog signal into the one-bit output signal. The multi-bit quantization converts the third analog signal into a multi-bit output signal. The digital-to-analog converter comprises a plurality of capacitors, and determines the number of capacitors to be charged according to the multi-bit output signal, then selects the capacitors to be charged in a predetermined turn and charges the capacitors. When the digital-to-analog converter receives the alternate multi-bit output signal, the digital-to-analog converter selects the capacitors in a turn reversing to the predetermined turn and charges the selected capacitors, which number corresponds to the multi-bit output signal, to generate the second analog signal. The digital filter converts the one-bit output signal and the multi-bit output signal to the digital output signal.
摘要翻译：本发明提供一种用于将外部模拟信号转换成数字输出信号的Δ-Σ调制器。 Δ-Σ调制器包括第一滤波器电路，第二滤波器电路，一比特量化，多比特量化，数模转换器和数字滤波器。第一滤波器电路根据外部模拟信号和一位输出信号输出第一模拟信号。第二滤波器电路根据第一模拟信号和第二模拟信号输出第三模拟信号。一比特量化将第三模拟信号转换为一位输出信号。多位量化将第三模拟信号转换为多位输出信号。数模转换器包括多个电容器，并且根据多位输出信号确定要充电的电容器的数量，然后以预定的匝数选择要充电的电容器并对电容器充电。当数模转换器接收到替代的多位输出信号时，数模转换器以反向预定的转弯的方式选择电容器，并对所选择的电容器充电，该数字对应于多位输出信号，以产生第二模拟信号。数字滤波器将一位输出信号和多位输出信号转换为数字输出信号。

5. 发明授权

US09735801B1 Sigma-delta modulator with averaged-signal feedback 有权
公开(公告)号：US09735801B1
公开(公告)日：2017-08-15
申请号：US15403683
申请日：2017-01-11
申请人： Takashi Miki
发明人： Takashi Miki
IPC分类号： H03M3/00
CPC分类号： H03M3/42 , H03M3/452 , H03M3/454
摘要： A sigma-delta modulator includes a plurality of quantizers, an input path, a feedback path, a loop filter, a pre-filter, and a connection path. The plurality of quantizers are configured to produce a plurality of quantized signals. The input path is configured to lead an input signal to the plurality of quantizers. The feedback path is configured to feed back a feedback signal into the input path, and the feedback signal is produced by averaging the plurality of quantized signals. The loop filter is put on the input path before the plurality of quantizers, and the loop filter is configured to receive the input signal and the feedback signal. The pre-filter is configured to output a signal to a corresponding quantizer which is one of the plurality of quantizers.

6. 发明申请

US20170214412A1 SIGMA-DELTA MODULATOR WITH AVERAGED-SIGNAL FEEDBACK 审中-公开
公开(公告)号：US20170214412A1
公开(公告)日：2017-07-27
申请号：US15403683
申请日：2017-01-11
申请人： Takashi MIKI
发明人： Takashi MIKI
IPC分类号： H03M3/00
CPC分类号： H03M3/42 , H03M3/452 , H03M3/454
摘要： A sigma-delta modulator includes a plurality of quantizers, an input path, a feedback path, a loop filter, a pre-filter, and a connection path. The plurality of quantizers are configured to produce a plurality of quantized signals. The input path is configured to lead an input signal to the plurality of quantizers. The feedback path is configured to feed back a feedback signal into the input path, and the feedback signal is produced by averaging the plurality of quantized signals. The loop filter is put on the input path before the plurality of quantizers, and the loop filter is configured to receive the input signal and the feedback signal. The pre-filter is configured to output a signal to a corresponding quantizer which is one of the plurality of quantizers.

7. 发明授权

US09712184B2 Sigma-delta modulator 有权
公开(公告)号：US09712184B2
公开(公告)日：2017-07-18
申请号：US15197398
申请日：2016-06-29
申请人： NXP B.V.
发明人： Lucien Johannes Breems , Muhammed Bolatkale
IPC分类号： H03M3/00
CPC分类号： H03M3/422 , H03M3/376 , H03M3/42 , H03M3/452 , H03M3/454 , H03M3/464 , H03M3/50
摘要： A sigma-delta modulator comprising a plurality of filter stages in series with each other, wherein at least one of the plurality of filter stages is configured to provide a filter-output-signal; and a plurality of gain stages, each gain stage configured to provide a gain-output-signal. The sigma-delta modulator also includes a filter-output-switching-element configured to selectively couple the filter-output-signal to an input terminal of one of the plurality of gain stages; and a plurality of filter-input-switching-elements. Each of the plurality of filter-input-switching-elements is associated with one of the plurality of filter stages, wherein the plurality of filter-input-switching-elements are configured to selectively couple one of the gain-stage-output-signals to an input terminal of its associated one of the plurality of filter stages.

8. 发明申请

US20170019124A1 SIGMA-DELTA MODULATOR 有权
标题翻译： SIGMA-DELTA调制器
公开(公告)号：US20170019124A1
公开(公告)日：2017-01-19
申请号：US15197398
申请日：2016-06-29
申请人： NXP B.V.
发明人： Lucien Johannes BREEMS , Muhammed BOLATKALE
IPC分类号： H03M3/00
CPC分类号： H03M3/422 , H03M3/376 , H03M3/42 , H03M3/452 , H03M3/454 , H03M3/464 , H03M3/50
摘要： A sigma-delta modulator comprising a plurality of filter stages in series with each other, wherein at least one of the plurality of filter stages is configured to provide a filter-output-signal; and a plurality of gain stages, each gain stage configured to provide a gain-output-signal. The sigma-delta modulator also includes a filter-output-switching-element configured to selectively couple the filter-output-signal to an input terminal of one of the plurality of gain stages; and a plurality of filter-input-switching-elements. Each of the plurality of filter-input-switching-elements is associated with one of the plurality of filter stages, wherein the plurality of filter-input-switching-elements are configured to selectively couple one of the gain-stage-output-signals to an input terminal of its associated one of the plurality of filter stages.
摘要翻译：一种Σ-Δ调制器，包括彼此串联的多个滤波器级，其中所述多个滤波器级中的至少一个被配置为提供滤波器输出信号; 以及多个增益级，每个增益级被配置为提供增益输出信号。 Σ-Δ调制器还包括滤波器输出开关元件，其被配置为选择性地将滤波器输出信号耦合到多个增益级之一的输入端; 和多个滤波器输入开关元件。多个滤波器输入开关元件中的每一个与多个滤波器级中的一个相关联，其中多个滤波器输入开关元件被配置为选择性地将增益级输出信号之一耦合到其相关联的一个滤波器级的输入端。

9. 发明申请

US20110304491A1 DIGITAL FEEDFORWARD SIGMA-DELTA MODULATOR IN ANALOG-TO-DIGITAL CONVERTER AND MODULATION METHOD THEREOF 有权
标题翻译：模拟数字转换器中的数字前馈SIGMA-DELTA调制器及其调制方法
公开(公告)号：US20110304491A1
公开(公告)日：2011-12-15
申请号：US12814533
申请日：2010-06-14
申请人： Yeong-Shin Jang , Sang-Gug Lee , Seung-Tak Ryu
发明人： Yeong-Shin Jang , Sang-Gug Lee , Seung-Tak Ryu
IPC分类号： H03M3/00
CPC分类号： H03M3/42 , H03M3/452
摘要： A digital feedforward sigma-delta modulator in an analog-to-digital converter and its modulation method are disclosed. The modulator changes a feedforward path from an analog domain to a digital domain and processes it. The modulator integrates an analog input by using a plurality of integrators, weights them, quantizes them by using a plurality of quantizers in a digital domain to output digital signals, and then adds up the thusly outputted digital signals by using a digital adder. In case of a continuous time digital feedforward sigma-delta modulator (SDM), a digital signal outputted from the digital adder is weighted and then immediately inputted to the digital adder in the digital domain so as to be subtracted, allowing for digital feedforwarding. Because the feedforward signal is processed in the digital domain, the area occupied by an analog circuit and power consumption can be reduced. Also, because signals are added up in the digital domain, a digital output signal can be immediately used when an excess loop delay needs to be corrected. Thus, because there is no need to convert the digital output signal into an analog signal by using a DAC, the DAC can be omitted.
摘要翻译：公开了一种模拟数字转换器中的数字前馈Σ-Δ调制器及其调制方法。调制器改变从模拟域到数字域的前馈路径并处理它。调制器通过使用多个积分器对模拟输入进行积分，对它们进行加权，通过使用数字域中的多个量化器量化它们以输出数字信号，然后通过使用数字加法器将所输出的数字信号相加。在连续时间数字前馈Σ-Δ调制器（SDM）的情况下，从数字加法器输出的数字信号被加权，然后在数字域中立即输入到数字加法器，以便减去数字前馈。由于前馈信号在数字域中被处理，所以可以减少由模拟电路占用的面积和功耗。另外，由于信号在数字域中相加，所以当需要纠正多余的环路延迟时，可以立即使用数字输出信号。因此，由于不需要通过使用DAC将数字输出信号转换为模拟信号，所以可以省略DAC。

10. 发明申请

US20090309774A1 DELTA-SIGMA MODULATOR 有权
标题翻译： DELTA-SIGMA调制器
公开(公告)号：US20090309774A1
公开(公告)日：2009-12-17
申请号：US12483709
申请日：2009-06-12
申请人： Koichi Hamashita
发明人： Koichi Hamashita
IPC分类号： H03M3/00
CPC分类号： H03M3/42
摘要： An object is to provide a stable delta-sigma modulator having good microlevel signal reproducibility and capable of outputting a 1-bit PDM signal with a low oversampling ratio of about 64 times at a high duty ratio of 90% or more. The delta-sigma modulator has a higher-order loop filter; a first 1-bit quantizer for making a decision as to the output of the higher-order loop filter; a first feedback component for feeding the first output signal back to the input stage of the higher-order loop filter; a second 1.5-bit quantizer for making a decision as to the output absolute value of an internal stage to be monitored; a second dynamic feedback component for feeding a second output signal back to the input stage of the higher-order loop filter; and an operational unit for producing a 1-bit PDM signal Y by performing operation on the first output signal and second output signal.
摘要翻译：目的是提供一种稳定的Δ-Σ调制器，其具有良好的微信号再现性，并且能够在90％以上的高占空比下以大约64倍的低过采样比率输出1位PDM信号。 Δ-Σ调制器具有较高阶环路滤波器; 用于决定高阶环路滤波器的输出的第一个1位量化器; 用于将第一输出信号反馈到高阶环路滤波器的输入级的第一反馈分量; 第二个1.5位量化器，用于决定要监视的内部级的输出绝对值; 用于将第二输出信号馈送回到高阶环路滤波器的输入级的第二动态反馈分量; 以及用于通过对第一输出信号和第二输出信号执行操作来产生1位PDM信号Y的操作单元。

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