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11. 发明申请

US20050024250A1 Space efficient low power cyclic A/D converter 有权
公开(公告)号：US20050024250A1
公开(公告)日：2005-02-03
申请号：US10631450
申请日：2003-07-30
申请人： Ahmad Atriss , Steven Allen
发明人： Ahmad Atriss , Steven Allen
IPC分类号： H03M1/06 , H03M1/34 , H03M1/40 , H04B20060101
CPC分类号： H03M1/0695 , H03M1/40
摘要： Methods and apparatus are provided for an analog converter. The apparatus comprises a first redundant signed digit (RSD) stage and a configurable block. The configurable block converts to a sample/hold circuit to sample a single ended analog signal. The sampled signal is then scaled, converted to a differential signal and provided to the first RSD stage. The first RSD stage outputs a bit value corresponding to the magnitude of the digital signal. In a next half clock cycle the first RSD stage calculates a residue that is provided to the configurable block. The configurable block is converted to a second redundant signed digit stage and generates a bit value corresponding to the magnitude of the residue provided by the first RSD stage. The first and second RSD stages cycle back and forth generating logic value each half clock cycle until the desired bit resolution is achieved. The configurable block is then converted back to a sample/hold circuit to start another conversion process.

12. 发明授权

US06667706B2 Analog to digital converter 失效
标题翻译：模数转换器
公开(公告)号：US06667706B2
公开(公告)日：2003-12-23
申请号：US10201590
申请日：2002-07-22
申请人： Jayadeva Jones
发明人： Jayadeva Jones
IPC分类号： H03M112
CPC分类号： H03M1/445 , H03M1/368 , H03M1/40
摘要： The invention relates to an analog to digital converter computing all the bits in parallel or sequentially, without using decoding logic having an analog input and a digital output, wherein given the analog signal x, each bit can be computed by applying a formula containing a non linear periodic function which may be sine shaped or pulse shaped.
摘要翻译：本发明涉及一种模数转换器，其并行或顺序地计算所有比特，而不使用具有模拟输入和数字输出的解码逻辑，其中给定模拟信号x，每个比特可以通过应用包含非可以是正弦形或脉冲形的线性周期函数。

13. 发明授权

US5537115A Analog-to-digital converter 失效
标题翻译：模数转换器
公开(公告)号：US5537115A
公开(公告)日：1996-07-16
申请号：US250398
申请日：1994-05-27
申请人： Yasuo Nagazumi
发明人： Yasuo Nagazumi
IPC分类号： H03M1/40 , H03M1/12
CPC分类号： H03M1/40
摘要： Analog memories such as CCD, which are advantageous in less power consumption and higher integration density, are used to configure a system for highly accurately executing analog/digital processing. An analog to digital converter according to the invention has at least one first analog memory having an input port for receiving input signal packets and a partial output drive port for driving the i-th output signal packet; at least one second analog memory having a function to integrate input signal packets applied thereto; and at least one signal packet routing mechanism for selectively routing output signal packets from the first analog memory according to an input digital signal bit. The extremely simple configuration of the present invention may be effectively utilized for realizing an ultra-parallel analog processor as well as applied to other fields such as video processing by combining a function of an input means for optical signals, which has been a main application of the CCD.
摘要翻译：使用诸如CCD的模拟存储器，其在较少的功率消耗和较高的集成密度方面是有利的，以配置用于高精度地执行模拟/数字处理的系统。根据本发明的模数转换器具有至少一个具有用于接收输入信号分组的输入端口和用于驱动第i输出信号分组的部分输出驱动端口的第一模拟存储器; 至少一个第二模拟存储器，具有整合施加到其上的输入信号分组的功能; 以及至少一个信号分组路由机制，用于根据输入的数字信号位选择性地路由来自第一模拟存储器的输出信号分组。本发明的非常简单的结构可以有效地用于实现超并行模拟处理器，并且通过组合用于光信号的输入装置的功能应用于诸如视频处理的其他领域，这已经是主要应用 CCD。

14. 发明授权

US5264849A Optical A/D conversion using asymmetrical-neural-networks 失效
标题翻译：使用非对称神经网络的光学A / D转换
公开(公告)号：US5264849A
公开(公告)日：1993-11-23
申请号：US917330
申请日：1992-07-23
申请人： Hiroshi Kondoh , Shiro Satoh
发明人： Hiroshi Kondoh , Shiro Satoh
IPC分类号： G02F7/00 , H03M1/40 , H03M1/22
CPC分类号： G02F7/00 , H03M1/40
摘要： An analog signal having a value A is converted into an n-bit digital signal. An optical calculation part performs a part of a calculation shown below for an A/D conversion as below.U.sub.i =[{{.SIGMA.(W.sub.ij .times.X.sub.j)+h.sub.i }.times.V}+A].times.Si . . . (1)The calculation of the equation (1) is performed fori=0, 1, . . . , n-1 respectively;the W.sub.ij is 0 if i.gtoreq.j.gtoreq.0, or -(2**j) if j>i.gtoreq.0; hi is -(2**i), or -{(2**i)-.epsilon.}(.vertline..epsilon..vertline..ltoreq.1);V and S.sub.i respectively have any desired positive values and the said .SIGMA. represents a summation of each expression following thereto for j=0, 1, . . . , n-1. The thresholding compares the result U.sub.i of the calculation of each equation (1) to a threshold value, and then 1 or 0 is selected. The result of the selection is then assigned to X.sub.i. The calculation of the equation (1) is then performed repeatedly until X.sub.i converge on solutions. The solution of each X.sub.i is then provided as digital values of the n-bit digital signal.
摘要翻译：具有值A的模拟信号被转换成n位数字信号。光学计算部分执行如下所示的用于A / D转换的计算的一部分，如下。 Ui = [{{SIGMA（WijxXj）+ hi} xV} + A] xSi。。（1）对于i = 0,1，...进行等式（1）的计算。。。，n-1; 如果i> / = j> / = 0，则Wij为0，或者如果j> i> / = 0则为 - （2 ** j）嗨是 - （2 ** i），或 - （（2 ** i） - ε）（|ε| | = 1）; V和Si分别具有任何期望的正值，并且所述SIGMA表示对于j = 0,1，之后的每个表达式的和。。。，n-1。阈值将每个等式（1）的计算结果Ui与阈值进行比较，然后选择1或0。然后将选择的结果分配给Xi。然后重复执行等式（1）的计算，直到Xi收敛于解。然后，将每个Xi的解决方案提供为n位数字信号的数字值。

15. 发明授权

US5202687A Analog to digital converter 失效
标题翻译：模拟到数字转换器
公开(公告)号：US5202687A
公开(公告)日：1993-04-13
申请号：US714246
申请日：1991-06-12
申请人： Robert J. Distinti
发明人： Robert J. Distinti
IPC分类号： H03M1/02 , H03M1/38 , H03M1/40 , H03M1/44 , H03M1/72
CPC分类号： H03M1/38 , H03M1/02 , H03M1/40 , H03M1/44 , H03M1/445 , H03M1/72
摘要： An Operational Analog to Digital (SYMAD) Convertor cell for converting an analog signal into a discrete binary code. An analog signal is processed by sample and hold circuitry and then compared to a reference voltage by a comparator. The comparator output is the converted digital output. This output is coupled back to the control input of an analog switch which selects either the reference voltage or a predetermined potential, typically zero volts, to couple to an inverting input of an operational amplifier. The analog signal input is also coupled to the non-inverting input of the operational amplifier. The operational amplifier is configured as a differential amplifier with a gain of two. If the digital output of the comparator is a logic 1, then the operational amplifier output is two times the difference between the analog signal and the reference voltage. If the digital output of the comparator is a logic 0, then the output of the operational amplifier is two times the analog signal. As many SYMAD cells as necessary may be provided to obtain a desired resolution.
摘要翻译：操作模数（SYMAD）转换单元，用于将模拟信号转换为离散二进制码。模拟信号由采样和保持电路处理，然后通过比较器与参考电压进行比较。比较器输出是转换的数字输出。该输出耦合回模拟开关的控制输入，模拟开关选择参考电压或预定电位（通常为零伏特）耦合到运算放大器的反相输入端。模拟信号输入也耦合到运算放大器的非反相输入端。运算放大器配置为增益为2的差分放大器。如果比较器的数字输出为逻辑1，则运算放大器输出是模拟信号与参考电压之差的两倍。如果比较器的数字输出为逻辑0，则运算放大器的输出为模拟信号的两倍。可以提供必要的许多SYMAD电池以获得期望的分辨率。

16. 发明授权

US4782323A Technique for maintaining a common centroid in switched element analog-to-digital converters 失效
标题翻译：用于在开关元件模数转换器中保持共同质心的技术
公开(公告)号：US4782323A
公开(公告)日：1988-11-01
申请号：US175635
申请日：1988-04-04
申请人： Charles H. Lucas
发明人： Charles H. Lucas
IPC分类号： H03M1/00 , H03M1/66
CPC分类号： H03M1/74 , H03M1/40 , H03M1/46
摘要： A switched capacitor circuit for use in a digital-to-analog converter, an analog-to-digital converter, or other digitally controlled circuit is disclosed. The switched capacitor circuit includes first and second arrays (30, 40) of switched capacitors of substantially identical value, each capacitor having a switched terminal. The switched capacitor circuit further includes a decoding circuit (20) responsive to a digital input having a decimal value N for providing control signals for each of the capacitor arrays. Logic circuitry (33, 43, GC(I)) responsive to the control signals is included for sequentially switching the switched terminals of L and M capacitors respectively of the first and second switched capacitor arrays in a predetermined sequence so as to maintain the geometrical centroid of the switched capacitors at a substantially constant location, where the sum of L and M is equal to N.
摘要翻译：公开了一种用于数模转换器，模数转换器或其它数字控制电路的开关电容器电路。开关电容器电路包括具有基本相同值的开关电容器的第一和第二阵列（30,40），每个电容器具有开关端子。开关电容器电路还包括解码电路（20），其响应于具有小数值N的数字输入，用于为每个电容器阵列提供控制信号。包括响应于控制信号的逻辑电路（33,43，GC（I）），用于按预定顺序依次切换第一和第二开关电容器阵列的L和M电容器的开关端子，以便保持几何重心的开关电容器在基本上恒定的位置，其中L和M的总和等于N.

17. 发明授权

US4454500A Analog data acquisition device 失效
标题翻译：模拟数据采集装置
公开(公告)号：US4454500A
公开(公告)日：1984-06-12
申请号：US348666
申请日：1982-02-16
申请人： Kazuo Kato , Nobuaki Miyakawa , Makoto Aihara , Kiyoshi Matsubara
发明人： Kazuo Kato , Nobuaki Miyakawa , Makoto Aihara , Kiyoshi Matsubara
IPC分类号： H03M1/38 , G01R19/00 , H03K5/24 , H03M1/00 , H03K13/02
CPC分类号： H03K5/24 , G01R19/0038 , H03M1/40 , H03M1/46
摘要： An analog data acquisition device fetches a plurality of analog data by a multiplexer in time-division, compares the analog data fetched with a reference value applied from a digital-to-analog converter by a two-input comparator, and produces the result of comparison to a data bus. The result of comparison is also applied to a successive approximation register where the analong-to-digital conversion is effected by successively changing the digital data to the digital-to-analog converter, and the digital data converted is read out onto the data bus.The digital data applied to the digital-to-analog converter is either the output from the successive approximation register or the output from the reference register loaded through the data bus, in accordance with the contents of the control register loaded through the data bus. Thus, in which mode the device operates, in the comparing mode or in the analog-to-digital conversion mode, is selected by the control register.
摘要翻译：模拟数据采集装置通过多路复用器分时获取多个模拟数据，将获取的模拟数据与通过双输入比较器从数模转换器施加的参考值进行比较，并产生比较结果到数据总线。比较结果也适用于逐次逼近寄存器，其中通过将数字数据连续地改变为数模转换器来进行分析数字转换，并将数字数据转换到数据总线上。根据通过数据总线加载的控制寄存器的内容，应用于数模转换器的数字数据是来自逐次逼近寄存器的输出或通过数据总线加载的参考寄存器的输出。因此，设备在哪种模式下工作，在比较模式或模数转换模式下，由控制寄存器选择。

18. 发明授权

US4410880A Digital-to-analog converter and analog-to-digital converter with controllable bi-polar and uni-polar capability 失效
标题翻译：数模转换器和具有可控双极性和单极性能力的模数转换器
公开(公告)号：US4410880A
公开(公告)日：1983-10-18
申请号：US247448
申请日：1981-03-25
申请人： Roy A. Zaborowski
发明人： Roy A. Zaborowski
IPC分类号： H03M1/00 , H03K13/02
CPC分类号： H03M1/1205 , H03M1/40 , H03M1/46 , H03M1/785
摘要： The digital-to-analog converter comprises an R-2R ladder network with bit controlled current steering switches connecting the legs of the ladder network to first and second current buses. First and second current-to-voltage converters are connected to the current buses respectively, the second current-to-voltage converter being connected through a switch to the input of the first current-to-voltage converter. A uni-polar/bi-polar control signal renders the switch conductive or non-conductive in accordance with the data format desired. The digital-to-analog converter is also utilized in a successive approximation analog-to-digital converter.
摘要翻译：数模转换器包括R-2R梯形网络，其具有将梯形网络的腿连接到第一和第二当前总线的位控制的电流转向开关。第一和第二电流 - 电压转换器分别连接到电流总线，第二电流 - 电压转换器通过开关连接到第一电流 - 电压转换器的输入。单极/双极控制信号根据所需的数据格式使开关导通或不导通。数模转换器也用于逐次逼近模数转换器。

19. 发明授权

US4358752A Analog-to-digital converter 失效
标题翻译：模数转换器
公开(公告)号：US4358752A
公开(公告)日：1982-11-09
申请号：US208385
申请日：1980-11-19
申请人： Haruo Tamada , Osamu Kudo
发明人： Haruo Tamada , Osamu Kudo
IPC分类号： G01R19/165 , G01R19/25 , G01R19/257 , H03F3/34 , H03K5/08 , H03K5/24 , H03M1/00 , H03M1/34 , H03M1/38 , H03K13/02
CPC分类号： H03K5/2418 , H03M1/40 , H03M1/46 , H03M1/74
摘要： A differential amplifier, which is associated with a digital-to-analog converter and a register and serves as an element of an analog-to-digital converter, having the offset input voltage characteristic determined by selecting, for example, the ratio of the emitter areas of a first pair of transistors so that no offset characteristic is required for the digital-to-analog converter associated with the differential amplifier. The offset input voltage can also be determined by selecting the ratio of the emitter areas of a second pair of transistors each one of the second pair of transistors connected to a different one of the first transistors and each one of the second pair of transistors having a current source of the same magnitude. The offset characteristic can also be determined by selecting unequal magnitudes of the current sources connected to the second pair of transistors when the ratio of the second pair of transistor emitter areas are equal. The offset characteristic can also be selected by selecting both the second pair of transistors emitter areas ratios and the second transistor current source magnitudes as not equal or by selecting any combination of the above current magnitudes or emitter area ratios.
摘要翻译：差分放大器，其与数模转换器和寄存器相关联，并且用作模数转换器的元件，其具有通过选择例如发射极的比例确定的偏移输入电压特性第一对晶体管的区域，使得与差分放大器相关联的数模转换器不需要偏移特性。偏移输入电压也可以通过选择第二对晶体管中的每一个晶体管的发射极面积与第一晶体管中的不同一个晶体管连接的第二对晶体管的发射极面积的比例来确定，并且第二对晶体管中的每一个晶体管具有电流源的幅度相同。当第二对晶体管发射极区域的比率相等时，也可以通过选择连接到第二对晶体管的电流源的不等量来确定偏移特性。还可以通过选择第二对晶体管发射极面积比和第二晶体管电流源幅度不相等或通过选择上述电流幅度或发射极面积比的任何组合来选择偏移特性。

20. 发明授权

US4282515A Analog to digital encoding system with an encoder structure incorporating instrumentation amplifier, sample and hold, offset correction and gain correction functions 失效
标题翻译：具有编码器结构的模数和数字编码系统，包括仪表放大器，采样和保持，偏移校正和增益校正功能
公开(公告)号：US4282515A
公开(公告)日：1981-08-04
申请号：US59422
申请日：1979-07-20
申请人： Raymond B. Patterson, III
发明人： Raymond B. Patterson, III
IPC分类号： H03M1/00 , H03K13/02
CPC分类号： H03M1/40 , H03M1/46 , H03M1/74
摘要： A new encoder for an analog to digital converter of the successive approximation type incorporates instrumentation amplifier and signal sample and hold functions within the encoder proper, thereby substantially simplifying the converter circuitry. An input analog current signal is applied to a sample and hold capacitor within the encoder through the encoder comparator at a time when the weighted reference signal to the comparator is set to zero. The capacitor stored analog voltage is subsequently applied to the encoder summing node and the encoding sequence ensues. The encoder may be provided with offset and gain correction circuitry, conventionally found exterior to the encoder. In one embodiment of the invention, offset correction is effected using the signal sample and hold capacitor.
摘要翻译：用于逐次逼近型的模数转换器的新编码器将仪表放大器和信号采样和保持功能集成在编码器内，从而大大简化了转换器电路。当比较器的加权参考信号设置为零时，通过编码器比较器将输入模拟电流信号施加到编码器内的采样和保持电容。电容器存储的模拟电压随后被施加到编码器求和节点，随后编码序列。编码器可以设置有通常在编码器外部发现的偏移和增益校正电路。在本发明的一个实施例中，使用信号采样和保持电容实现偏移校正。

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