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11. 发明申请

US20130093524A1 DIGITALLY CONTROLLED OSCILLATOR DEVICE AND HIGH FREQUENCY SIGNAL PROCESSING DEVICE 有权
标题翻译：数字控制振荡器装置和高频信号处理装置
公开(公告)号：US20130093524A1
公开(公告)日：2013-04-18
申请号：US13651410
申请日：2012-10-13
申请人： Renesas Mobile Corporation
发明人： Takahiro NAKAMURA
IPC分类号： H03L7/02
CPC分类号： H03L7/02 , H03B5/1206 , H03B5/1265 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03L7/099 , H03L2207/50
摘要： The present invention provides a digitally controlled oscillator device capable of reducing noise away from an oscillation frequency, and a high frequency signal processing device. Fractional capacitances are realized using a plurality of unitary capacitor units, for example. In one unitary capacitor unit, one ends of two types of capacitive elements are respectively coupled to oscillation output nodes. On the other hand, in the unitary capacitor units other than the one unitary capacitor unit, one ends of two types of capacitive elements are respectively coupled to a fixed voltage. The other ends of one capacitive elements in all the unitary capacitor units are coupled in common, and the other ends of other capacitive elements are also coupled in common. Turning on and off of respective switches in all the unitary capacitor units are controlled in common.
摘要翻译：本发明提供一种能够降低远离振荡频率的噪声的数字控制振荡器装置和高频信号处理装置。例如，使用多个单体电容器单元实现分数电容。在一个单体电容器单元中，两种类型的电容元件的一端分别耦合到振荡输出节点。另一方面，除了一个单一电容器单元之外的单电容器单元中，两种类型的电容元件的一端分别耦合到固定电压。所有单体电容器单元中的一个电容元件的另一端共同耦合，并且其它电容元件的另一端也共同耦合。所有单体电容器单元中的各个开关的导通和关断被共同控制。

12. 发明授权

US08364098B2 PLL calibration 有权
标题翻译： PLL校准
公开(公告)号：US08364098B2
公开(公告)日：2013-01-29
申请号：US12771900
申请日：2010-04-30
申请人： Timothy John Ridgers
发明人： Timothy John Ridgers
IPC分类号： H04B1/04 , H03C3/06 , H03C3/09
CPC分类号： H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0991
摘要： A method for applying a modulation signal to a phase locked loop comprises filtering the modulation signal to provide a low frequency component and a high frequency for application to respectively the feedback and feedforward paths of a phase locked loop. The high frequency component is scaled by a gain factor before being applied to the feedforward path. The low frequency component is also scaled by a gain factor and applied to the feedforward path. The energy in a common low frequency range of the modulation signal and of the loop error signal is estimated, and the gain factors are modified dependent on the measured energy.
摘要翻译：将调制信号施加到锁相环的方法包括对调制信号进行滤波以提供低频分量和高频，以分别应用于锁相环的反馈和前馈路径。在施加到前馈路径之前，高频分量被增益因子缩放。低频分量也被增益因子缩放并应用于前馈路径。估计调制信号和环路误差信号的共同低频范围内的能量，并根据测得的能量修改增益因子。

13. 发明申请

US20120212296A1 SIGNAL GENERATING CIRCUIT AND SIGNAL GENERATING METHOD 有权
标题翻译：信号发生电路和信号发生方法
公开(公告)号：US20120212296A1
公开(公告)日：2012-08-23
申请号：US13029130
申请日：2011-02-17
申请人： Hsin-Hung Chen , Hsiang-Hui Chang
发明人： Hsin-Hung Chen , Hsiang-Hui Chang
IPC分类号： H03L7/24 , H03L7/099
CPC分类号： H03C3/0925 , H03C3/0941 , H03C3/0958
摘要： A signal generating circuit includes: an operating circuit arranged to generate a first control signal according to a reference clock signal and a feedback oscillating signal; a controllable oscillator arranged to generate an output oscillating signal according to the first control signal and a second control signal; a feedback circuit arranged to generate the feedback oscillating signal according to the output oscillating signal and a third control signal; a control circuit arranged to generate the second control signal and the third control signal according to an input signal; and a calibrating circuit arranged to calibrate the control circuit to adjust the second control signal by detecting a phase difference between the reference clock signal and the feedback oscillating signal.
摘要翻译：信号发生电路包括：操作电路，被配置为根据参考时钟信号和反馈振荡信号产生第一控制信号; 可控振荡器，被配置为根据第一控制信号和第二控制信号产生输出振荡信号; 反馈电路，被配置为根据输出振荡信号和第三控制信号产生反馈振荡信号; 控制电路，被配置为根据输入信号产生第二控制信号和第三控制信号; 以及校准电路，其布置成通过检测参考时钟信号和反馈振荡信号之间的相位差校准控制电路来调整第二控制信号。

14. 发明申请

US20120163506A1 GFSK MODULATOR AND A METHOD FOR REDUCING RESIDUAL FREQUENCY MODULATION AND A DIGITAL ENHANCED CORDLESS TELECOMMUNICATION TRANSMITTER INCLUDING THE GFSK MODULATOR 有权
标题翻译： GFSK调制器和减少残留频率调制的方法和包括GFSK调制器的数字增强型无线电信发射机
公开(公告)号：US20120163506A1
公开(公告)日：2012-06-28
申请号：US12981518
申请日：2010-12-30
申请人： Yiming Huang , Ronghui Kong , Caogang Yu
发明人： Yiming Huang , Ronghui Kong , Caogang Yu
IPC分类号： H04L27/14
CPC分类号： H03C3/04 , H03C3/0933 , H03C3/0941 , H03C3/0958 , H03C2200/0079
摘要： A GFSK modulator comprises: a first compensation module, configured to receive a GFSK pulse signal, apply a first amplitude compensation and a first delay compensation to the GFSK pulse signal, so as to generate a first compensated control signal; a second compensation module, configured to receive the GFSK pulse signal, apply a second amplitude compensation and a second delay compensation to the GFSK pulse signal, so as to generate a second compensated control signal; a closed-loop PLL module including a closed-loop PLL, configured to receive and use the first and the second compensated control signals to generate a modulated signal.
摘要翻译： GFSK调制器包括：第一补偿模块，被配置为接收GFSK脉冲信号，对GFSK脉冲信号施加第一幅度补偿和第一延迟补偿，以产生第一补偿控制信号; 第二补偿模块，被配置为接收所述GFSK脉冲信号，对所述GFSK脉冲信号施加第二幅度补偿和第二延迟补偿，以产生第二补偿控制信号; 包括闭环PLL的闭环PLL模块，被配置为接收和使用第一和第二补偿控制信号以产生调制信号。

15. 发明申请

US20120161892A1 Enhanced polar modulator for transmitter 有权
标题翻译：用于发射机的增强极化调制器
公开(公告)号：US20120161892A1
公开(公告)日：2012-06-28
申请号：US13412519
申请日：2012-03-05
申请人： Sofoklis Plevridis , Theodoros Georgantas , Konstantinos D. Vavelidis
发明人： Sofoklis Plevridis , Theodoros Georgantas , Konstantinos D. Vavelidis
IPC分类号： H04L27/32
CPC分类号： H03C5/00 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/0958
摘要： Enhanced polar modulator for transmitter. Within a phase locked loop (PLL), two point modulation topology is employed in which phase information passes through a limiter (e.g., a ±90° or ±π/2), the phase information dynamic range is divided by a factor (e.g., by 2), and a maximum frequency deviation is also divided by a factor (e.g., by 2). Then, a double balanced up-converter mixer/modulator performs gain adjustment (e.g., magnitude and/or amplitude adjustment) and phase changes of 0° and +180° or 0 and +π (e.g., negative gains values may be employed). Phase adjustment in such an architecture is split and provided to both the PLL and to the mixer/modulator of such a polar modulator within a transmitter module such as may be implemented within a communication device (e.g., which may be a wireless communication device). This architecture that includes a PLL with a double balanced up-converter mixer/modulator suppresses even harmonics.
摘要翻译：用于发射机的增强极化调制器。在锁相环（PLL）中，使用两点调制拓扑，其中相位信息通过限幅器（例如±90°或±＆pgr / / 2），相位信息动态范围除以因子（例如，2），并且最大频率偏差也除以因子（例如，2）。然后，双平衡升压转换器混频器/调制器执行增益调整（例如，幅度和/或幅度调整）以及0°和+ 180°或0°和+＆pgr的相位变化。（例如，可以采用负增益值）。这种架构中的相位调整被分离并提供给发射机模块内的PLL和这种极性调制器的混频器/调制器，例如可以在通信设备（例如，其可以是无线通信设备）内实现。这种包括具有双平衡上变频混频器/调制器的PLL的架构抑制了偶次谐波。

16. 发明申请

US20120013375A1 FREQUENCY SYNTHESIZER DEVICE AND MODULATION FREQUENCY DISPLACEMENT ADJUSTMENT METHOD 有权
标题翻译：频率合成器件和调制频率调整方法
公开(公告)号：US20120013375A1
公开(公告)日：2012-01-19
申请号：US13179666
申请日：2011-07-11
申请人： Takashi KURAMOCHI
发明人： Takashi KURAMOCHI
IPC分类号： H03L7/08
CPC分类号： H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/0958
摘要： A frequency synthesizer device that includes two modulation paths and suitably adjusts the amplitude of a control voltage that is outputted from a digital-to-analog converter (DAC) to a voltage-controlled oscillator. The frequency synthesizer device is provided with a voltage-controlled oscillator, a programmable frequency divider, a frequency phase comparator, a DAC, a switch and a modulation frequency displacement correction circuit. The voltage-controlled oscillator oscillates at an oscillation frequency depending on an input voltage. The programmable frequency divider frequency-divides a signal from the voltage-controlled oscillator. The frequency phase comparator outputs a phase difference between the frequency-divided signal and a reference clock. The DAC outputs an adjustment voltage. The switch connects the voltage-controlled oscillator to a reference voltage power source at a time of correction of the adjustment voltage. The modulation frequency displacement correction circuit specifies adjustment data that corresponds to the adjustment voltage corresponding to the target frequency displacement.
摘要翻译：一种频率合成器装置，其包括两个调制路径，并且适当地调节从数模转换器（DAC）输出到压控振荡器的控制电压的幅度。频率合成器装置设有压控振荡器，可编程分频器，频率相位比较器，DAC，开关和调制频率位移校正电路。压控振荡器根据输入电压以振荡频率振荡。可编程分频器对来自压控振荡器的信号进行分频。频率相位比较器输出分频信号和参考时钟之间的相位差。 DAC输出调整电压。在校正调整电压时，开关将压控振荡器连接到参考电压电源。调制频率位移校正电路指定与对应于目标频率位移的调整电压对应的调整数据。

17. 发明授权

US07884676B1 PLL/FLL circuit with gain control 有权
标题翻译：带增益控制的PLL / FLL电路
公开(公告)号：US07884676B1
公开(公告)日：2011-02-08
申请号：US12534663
申请日：2009-08-03
申请人： Kenji Miyanaga
发明人： Kenji Miyanaga
IPC分类号： H03L7/00
CPC分类号： H03L7/093 , H03C3/0941 , H03C3/095 , H03C3/0966
摘要： An FLL circuit having a capability of configuring a desired loop bandwidth in a short period of time is provided. An FDC 17 generates a feedback of an output signal of a VCO 15. An error detector 11 detects an error of the output signal of the VCO 15. A voltage retainer 13 retains an output of a control voltage of the VCO 15. A reference signal generator 16 generates a reference signal. An adder 14 adds the reference signal to a control voltage outputted by the voltage retainer 13. A Kv calculator 18 calculates a gain Kv of the VCO 15 based on a degree of transition of an output frequency of the VCO 15. A loop bandwidth controller 19 adjusts, based on the gain Kv of the VCO 15, a gain of a loop filter 12 to an optimum value, and configures a desired loop bandwidth.
摘要翻译：提供了具有在短时间内配置期望的环路带宽的能力的FLL电路。 FDC17产生VCO15的输出信号的反馈。误差检测器11检测VCO15的输出信号的误差。电压保持器13保持VCO15的控制电压的输出。参考信号发生器16产生参考信号。加法器14将参考信号与由电压保持器13输出的控制电压相加.Kv计算器18基于VCO15的输出频率的转变程度来计算VCO 15的增益Kv。环路带宽控制器19 基于VCO15的增益Kv将环路滤波器12的增益调整到最佳值，并且配置期望的环路带宽。

18. 发明授权

US07746187B2 Self-calibrating modulator apparatuses and methods 有权
标题翻译：自校准调制装置及方法
公开(公告)号：US07746187B2
公开(公告)日：2010-06-29
申请号：US12131417
申请日：2008-06-02
申请人： Wayne S. Lee , Akira Kato , Toru Matsuura
发明人： Wayne S. Lee , Akira Kato , Toru Matsuura
IPC分类号： H03C3/00
CPC分类号： H03C3/0941 , H03C3/08 , H03C3/095 , H03C3/0975 , H03C3/0991 , H03C5/00
摘要： A self-calibrating modulator apparatus includes a modulator having a controlled oscillator and an oscillator gain calibration circuit. The oscillator gain calibration circuit includes an oscillator gain coefficient calculator configured to calculate a plurality of frequency dependent oscillator gain coefficients from results of measurements taken at the output of the controlled oscillator in response to a test pattern signal representing a plurality of different reference frequencies. The plurality of frequency dependent gain coefficients determined from the calibration process are stored in a look up table (LUT), where they are made available after the calibration process ends to scale a modulation signal applied to the modulator. By scaling the modulation signal prior to it being applied to the control input of the controlled oscillator, the nonlinear response of the controlled oscillator is countered and the modulation accuracy of the modulator is thereby improved.
摘要翻译：自校准调制器装置包括具有受控振荡器和振荡器增益校准电路的调制器。振荡器增益校准电路包括振荡器增益系数计算器，其被配置为响应于表示多个不同参考频率的测试模式信号，从受控振荡器的输出处获得的测量结果计算多个频率相关振荡器增益系数。从校准过程确定的多个与频率相关的增益系数被存储在查找表（LUT）中，在校准过程结束之后它们可用以缩放施加到调制器的调制信号。通过在将调制信号应用于受控振荡器的控制输入之前缩放调制信号，可以对受控振荡器的非线性响应进行调整，从而提高调制器的调制精度。

19. 发明授权

US07714666B2 Phase locked loop frequency synthesizer and method for modulating the same 有权
标题翻译：锁相环频率合成器及其调制方法
公开(公告)号：US07714666B2
公开(公告)日：2010-05-11
申请号：US11745611
申请日：2007-05-08
申请人： Ling-Wei Ke , Tai Yuan Yu , Hsin-Hung Chen
发明人： Ling-Wei Ke , Tai Yuan Yu , Hsin-Hung Chen
IPC分类号： H03L7/00
CPC分类号： H03L7/1976 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095
摘要： A phase locked loop frequency synthesizer including a phase locked loop, a frequency regenerator and a modulation processor, resistant to distortion induced by the frequency regenerator and conforming to transmission specifications. The phase locked loop comprises a detector generating a phase detection signal based on phase difference between a reference signal and a feedback signal, a loop filter, a voltage control oscillator generating a first output modulation signal and a frequency dividing unit varying a division factor based on a processed input modulation signal and dividing the frequency of the first output modulation signal by a division factor to generate the feedback signal. The frequency regenerator generates a second output modulation signal with a frequency range not overlapping an output frequency range of the voltage control oscillator. The modulation processor generates the processed input modulation signal to adjust the division factor of the frequency dividing unit and compensating for distortion induced by the frequency regenerator.
摘要翻译：一种锁相环频率合成器，包括锁相环，频率再生器和调制处理器，能够抵抗由频率再生器引起的失真并符合传输规范。锁相环包括检测器，其基于参考信号和反馈信号之间的相位差产生相位检测信号，环路滤波器，产生第一输出调制信号的电压控制振荡器和基于经处理的输入调制信号，并将第一输出调制信号的频率除以分频因子以产生反馈信号。频率再生器产生频率范围不与压控振荡器的输出频率范围重叠的第二输出调制信号。调制处理器产生经处理的输入调制信号，以调整分频单元的分频因子并补偿由频率再生器引起的失真。

20. 发明申请

US20100090731A1 SELF-CALIBRATION METHOD FOR A FREQUENCY SYNTHESIZER USING TWO POINT FSK MODULATION 有权
标题翻译：使用两点FSK调制的频率合成器的自校准方法
公开(公告)号：US20100090731A1
公开(公告)日：2010-04-15
申请号：US12573253
申请日：2009-10-05
申请人： Arnaud Casagrande
发明人： Arnaud Casagrande
IPC分类号： H03L7/07
CPC分类号： H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/0958 , H03C3/0991
摘要： The frequency synthesizer (1) for implementing the self-calibration method includes a first phase lock loop and a high frequency access, which includes a digital-analogue converter (20) that is calibrated by the method, connected to a second input of a voltage-controlled oscillator. The first phase lock loop includes a reference oscillator (2), a phase comparator (3), a first charge pump (4), a first loop filter (5), the voltage controlled oscillator (10) connected by a first input in the first loop, a multimode divider counter (9) controlled by a modulator (11) and connected to the phase comparator. For the calibration operation, the frequency synthesizer includes a second charge pump (14) connected to the phase comparator (3), and a second loop filter (15) in the high frequency access. When the second charge pump is switched on, it forms a second phase lock loop with the second filter connected to the voltage-controlled oscillator. To calibrate the converter gain, a voltage comparator (21) compares an output voltage of the digital-analogue converter (20) with a voltage stored in the second loop filter, after disconnecting the second charge pump of the second phase lock loop, which was previously locked onto a determined output frequency.
摘要翻译：用于实现自校准方法的频率合成器（1）包括第一锁相环和高频接入，其包括通过该方法校准的数模转换器（20），连接到电压的第二输入端控制振荡器。第一锁相环包括参考振荡器（2），相位比较器（3），第一电荷泵（4），第一环路滤波器（5），压控振荡器（10）第一环路，由调制器（11）控制并连接到相位比较器的多模式分频器计数器（9）。对于校准操作，频率合成器包括连接到相位比较器（3）的第二电荷泵（14）和在高频访问中的第二环路滤波器（15）。当第二电荷泵接通时，它形成第二个锁相环，第二个滤波器连接到压控振荡器。为了校准转换器增益，在断开第二个锁相环的第二电荷泵之后，电压比较器（21）将数模转换器（20）的输出电压与存储在第二环路滤波器中的电压进行比较，先前锁定到确定的输出频率。

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