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11. 发明授权

US09171751B2 Method and system for fabricating floating guard rings in GaN materials 有权
标题翻译：在GaN材料中制造浮动保护环的方法和系统
公开(公告)号：US09171751B2
公开(公告)日：2015-10-27
申请号：US14264998
申请日：2014-04-29
申请人： AVOGY, INC.
发明人： Donald R. Disney , Andrew P. Edwards , Hui Nie , Richard J. Brown , Isik C. Kizilyalli , David P. Bour , Linda Romano , Thomas R. Prunty
IPC分类号： H01L29/06 , H01L21/761 , H01L21/266 , H01L21/265 , H01L29/20 , H01L29/40 , H01L29/66 , H01L29/808 , H01L29/872
CPC分类号： H01L21/761 , H01L21/2654 , H01L21/266 , H01L21/765 , H01L29/0619 , H01L29/0642 , H01L29/0692 , H01L29/2003 , H01L29/402 , H01L29/66136 , H01L29/66212 , H01L29/6631 , H01L29/66909 , H01L29/8083 , H01L29/872
摘要： A method for fabricating an edge termination structure includes providing a substrate having a first surface and a second surface and a first conductivity type, forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate, and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The method also includes implanting ions into a first region of the second GaN epitaxial layer to electrically isolate a second region of the second GaN epitaxial layer from a third region of the second GaN epitaxial layer. The method further includes forming an active device coupled to the second region of the second GaN epitaxial layer and forming the edge termination structure coupled to the third region of the second GaN epitaxial layer.
摘要翻译：一种用于制造边缘终端结构的方法包括提供具有第一表面和第二表面和第一导电类型的衬底，形成耦合到衬底的第一表面的第一导电类型的第一GaN外延层，并形成第二与第一导电类型相反的第二导电类型的GaN外延层。第二GaN外延层耦合到第一GaN外延层。该方法还包括将离子注入第二GaN外延层的第一区域以将第二GaN外延层的第二区域与第二GaN外延层的第三区域电隔离。该方法还包括形成耦合到第二GaN外延层的第二区域并形成耦合到第二GaN外延层的第三区域的边缘端接结构的有源器件。

12. 发明申请

US20150263178A1 JFET AND METHOD OF MANUFACTURING THEREOF 有权
标题翻译： JFET及其制造方法
公开(公告)号：US20150263178A1
公开(公告)日：2015-09-17
申请号：US14207733
申请日：2014-03-13
申请人： Infineon Technologies AG
发明人： Jens Peter Konrath , Hans-Joachim Schulze , Ralf Siemieniec , Cedric Ouvrard
IPC分类号： H01L29/808 , H01L21/311 , H01L21/266 , H01L29/66
CPC分类号： H01L29/8083 , H01L21/266 , H01L29/1066 , H01L29/1608 , H01L29/36 , H01L29/407 , H01L29/66909
摘要： A JFET has a semiconductor body with a first surface and second surface substantially parallel to the first surface. A source metallization and gate metallization are arranged on the first surface. A drain metallization is arranged on the second surface. In a sectional plane substantially perpendicular to the first surface, the semiconductor body includes: a first semiconductor region in ohmic contact with the source and drain metallizations, at least two second semiconductor regions in ohmic contact with the gate metallization, spaced apart from one another, and forming respective first pn-junctions with the first semiconductor region, and at least one body region forming a second pn-junction with the first semiconductor region. The at least one body region is in ohmic contact with the source metallization. At least a portion of the at least one body region is, in a projection onto the first surface, arranged between the two second semiconductor regions.
摘要翻译： JFET具有半导体本体，其具有基本上平行于第一表面的第一表面和第二表面。源金属化和栅极金属化被布置在第一表面上。漏极金属化被布置在第二表面上。在基本上垂直于第一表面的截面中，半导体本体包括：与源极和漏极金属化欧姆接触的第一半导体区域，与栅极金属化欧姆接触的至少两个第二半导体区域彼此间隔开，以及与所述第一半导体区域形成相应的第一pn结，以及形成与所述第一半导体区域的第二pn结的至少一个体区。至少一个体区与源金属化欧姆接触。所述至少一个体区的至少一部分在所述第一表面上的突起中布置在所述两个第二半导体区之间。

13. 发明申请

US20150214385A1 Semiconductor Device and Method of Manufacturing the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150214385A1
公开(公告)日：2015-07-30
申请号：US14469799
申请日：2014-08-27
申请人： Renesas Electronics Corporation
发明人： Koichi ARAI
IPC分类号： H01L29/808 , H01L29/16 , H01L21/04 , H01L29/66
CPC分类号： H01L29/66068 , H01L21/046 , H01L21/8213 , H01L21/8232 , H01L27/098 , H01L29/1058 , H01L29/1066 , H01L29/1608 , H01L29/66909 , H01L29/8083
摘要： An on-resistance of a junction FET is reduced. In a semiconductor device in an embodiment, a gate region of the junction field effect transistor includes a low concentration gate region and a high concentration gate region whose impurity concentration is higher than an impurity concentration of the low concentration gate region, and the high concentration gate region is included in the low concentration gate region.
摘要翻译：结FET的导通电阻降低。在本实施方式的半导体装置中，结场效应晶体管的栅极区域包括低浓度栅极区域和杂质浓度高于低浓度栅极区域的杂质浓度的高浓度栅极区域，高浓度栅极区域包括在低浓度栅极区域中。

14. 发明申请

US20150137143A1 Junction Field Effect Transistor Cell with Lateral Channel Region 有权
标题翻译：具有侧向通道区域的结场效应晶体管电池
公开(公告)号：US20150137143A1
公开(公告)日：2015-05-21
申请号：US14083023
申请日：2013-11-18
申请人： Infineon Technologies AG
发明人： Jens Peter Konrath , Hans-Joachim Schulze
IPC分类号： H01L29/808 , H01L29/10 , H01L29/423 , H01L21/265 , H01L21/266 , H01L29/16 , H01L29/66
CPC分类号： H01L29/8083 , H01L21/0465 , H01L21/26546 , H01L21/266 , H01L29/1058 , H01L29/1066 , H01L29/1608 , H01L29/2003 , H01L29/66909
摘要： A junction field effect transistor cell of a semiconductor device includes a top gate region, a lateral channel region and a buried gate region arranged along a vertical direction. The lateral channel region includes first zones of a first conductivity type and second zones of a second conductivity type which alternate along a lateral direction perpendicular to the vertical direction. A pinch-off voltage of the junction field effect transistor cell does not depend, or only to a low degree depends, on a vertical extension of the lateral channel region.
摘要翻译：半导体器件的结型场效应晶体管单元包括沿着垂直方向布置的顶栅区域，横向沟道区域和掩埋栅极区域。横向通道区域包括第一导电类型的第一区域和沿垂直于垂直方向的横向方向交替的第二导电类型的第二区域。结型场效应晶体管单元的夹断电压不依赖于或仅在很小程度上取决于横向沟道区域的垂直延伸。

15. 发明申请

US20150137142A1 Junction Field Effect Transistor Cell with Lateral Channel Region 有权
标题翻译：具有侧向通道区域的结场效应晶体管电池
公开(公告)号：US20150137142A1
公开(公告)日：2015-05-21
申请号：US14082815
申请日：2013-11-18
申请人： Infineon Technologies AG
发明人： Jens Peter Konrath , Hans-Joachim Schulze
IPC分类号： H01L29/808 , H01L29/66
CPC分类号： H01L29/808 , H01L29/1058 , H01L29/1066 , H01L29/1608 , H01L29/2003 , H01L29/41766 , H01L29/66068 , H01L29/66909 , H01L29/66924 , H01L29/8083
摘要： A semiconductor device includes a junction field effect transistor cell with a top gate region, a lateral channel region and a buried gate region. The lateral channel region is arranged between the top gate region and the buried gate region along a vertical direction with respect to a first surface of a semiconductor body. The lateral channel region comprises at least two first zones of a first conductivity type and at least one second zone of a second conductivity type, wherein the first and second zones alternate along the vertical direction. The embodiments provide well-defined channel widths and facilitate the adjustment of pinch-off voltages as well as the manufacture of normally-off junction field effect transistor cells.
摘要翻译：半导体器件包括具有顶栅区的结型场效应晶体管单元，横向沟道区和掩埋栅区。横向沟道区域相对于半导体主体的第一表面沿着垂直方向布置在顶部栅极区域和掩埋栅极区域之间。横向通道区域包括至少两个第一导电类型的第一区域和第二导电类型的至少一个第二区域，其中第一区域和第二区域沿垂直方向交替。这些实施例提供了明确定义的沟道宽度并且有助于夹断电压的调节以及常闭结场效应晶体管单元的制造。

16. 发明申请

US20150060887A1 NORMALLY-OFF POWER JFET AND MANUFACTURING METHOD THEREOF 有权
标题翻译：正常关断电源及其制造方法
公开(公告)号：US20150060887A1
公开(公告)日：2015-03-05
申请号：US14536625
申请日：2014-11-09
申请人： Renesas Electronics Corporation
发明人： Koichi Arai , Yasuaki Kagotoshi , Nobuo Machida , Natsuki Yokoyama , Haruka Shimizu
IPC分类号： H01L29/808 , H01L29/66 , H01L29/16
CPC分类号： H01L29/36 , H01L29/045 , H01L29/1066 , H01L29/1608 , H01L29/42316 , H01L29/66909 , H01L29/8083
摘要： In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.
摘要翻译：通常，在诸如基于SiC的正常关断JFET的半导体有源元件中，其中杂质扩散速度显着低于硅中的杂质扩散速度，通过离子注入形成在源区中形成的沟槽的侧壁中形成栅极区。然而，为了确保JFET的性能，需要高精度地控制栅极区域之间的面积。此外，存在这样的问题，由于通过在源极区域中形成栅极区域而形成重掺杂的PN结，所以不能避免结电流的增加。本发明提供一种常闭功率JFET及其制造方法，根据多次外延法形成栅极区域，该方法重复包括外延生长，离子注入和激活退火多次的工艺。

17. 发明授权

US08969912B2 Method and system for a GaN vertical JFET utilizing a regrown channel 有权
标题翻译：利用再生长通道的GaN垂直JFET的方法和系统
公开(公告)号：US08969912B2
公开(公告)日：2015-03-03
申请号：US13198659
申请日：2011-08-04
申请人： Isik C. Kizilyalli , Hui Nie , Andrew P. Edwards , Linda Romano , David P. Bour , Richard J. Brown , Thomas R. Prunty
发明人： Isik C. Kizilyalli , Hui Nie , Andrew P. Edwards , Linda Romano , David P. Bour , Richard J. Brown , Thomas R. Prunty
IPC分类号： H01L29/74 , H01L31/0328 , H01L29/80 , H01L29/76 , H01L21/8238 , H01L21/336 , H01L29/66 , H01L21/8252 , H01L27/06 , H01L29/808 , H01L29/10 , H01L29/20
CPC分类号： H01L29/66909 , H01L21/8252 , H01L27/0605 , H01L29/1066 , H01L29/2003 , H01L29/66446 , H01L29/66924 , H01L29/8083
摘要： A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, a gate region at least partially surrounding the channel region, having a first surface coupled to the drift region and a second surface on a side of the gate region opposing the first surface, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction, and the channel region extends along at least a portion of the second surface of the gate region.
摘要翻译：垂直III族氮化物场效应晶体管包括：包含第一III族氮化物材料的漏极，与漏极电耦合的漏极接触点，以及包括耦合到漏极的第二III族氮化物材料的漂移区域。场效应晶体管还包括沟道区，该沟道区包括耦合到漏极并沿着垂直方向邻近漏极设置的第三III族氮化物材料，至少部分围绕沟道区的栅极区，具有耦合到漂移的第一表面区域和与栅极区域相对的栅极区域的一侧上的第二表面，以及电连接到栅极区域的栅极接触。场效应晶体管还包括耦合到沟道区的源极和电耦合到源极的源极接触。沟道区域沿着垂直方向设置在漏极和源极之间，使得在垂直III族氮化物场效应晶体管的操作期间的电流沿着垂直方向，并且沟道区域沿着第二表面的至少一部分延伸的门区域。

18. 发明申请

US20150041829A1 ELECTRONIC CIRCUIT DEVICE 有权
标题翻译：电子电路设备
公开(公告)号：US20150041829A1
公开(公告)日：2015-02-12
申请号：US14495303
申请日：2014-09-24
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Haruka SHIMIZU , Natsuki YOKOYAMA
IPC分类号： H01L27/06 , H01L29/16 , H01L29/808
CPC分类号： H01L27/0629 , H01L21/8213 , H01L24/05 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L29/1608 , H01L29/66909 , H01L29/8083 , H01L29/868 , H01L2224/02166 , H01L2224/04042 , H01L2224/05556 , H01L2224/05624 , H01L2224/0603 , H01L2224/29101 , H01L2224/32245 , H01L2224/48091 , H01L2224/48137 , H01L2224/48195 , H01L2224/48247 , H01L2224/49111 , H01L2224/73265 , H01L2924/00014 , H01L2924/10253 , H01L2924/10272 , H01L2924/12031 , H01L2924/12032 , H01L2924/12036 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/15788 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2924/014 , H01L2924/00012
摘要： A normally-off type silicon carbide junction FET has a problem that the gate thereof is not easy to use due to inferiority in the characteristics of it. This problem occurs because in order to achieve normally-off, the gate voltage should be off at 0V and at the same time, the ON-state gate voltage should be suppressed to about 2.5V to prevent the passage of an electric current through a pn junction between gate and source. Accordingly, a range from the threshold voltage to the ON-state gate voltage is only from about 1 V to 2V and it is difficult to control the gate voltage. Provided in the present invention is an electronic circuit device obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the junction FET.
摘要翻译：常闭型碳化硅结FET由于其特性的劣化而具有栅极不易使用的问题。出现此问题的原因是为了实现常关，栅极电压应在0V关断，同时将导通状态栅极电压抑制在约2.5V，以防止电流通过pn 门和源之间的连接。因此，从阈值电压到导通状态栅极电压的范围仅为约1V至2V，并且难以控制栅极电压。在本发明中提供的是通过将常闭型碳化硅结FET的栅极耦合到具有等于或稍小于结FET的栅极电容的电容的元件而获得的电子电路器件。

19. 发明授权

US08941117B2 Monolithically integrated vertical JFET and Schottky diode 有权
标题翻译：单片集成垂直JFET和肖特基二极管
公开(公告)号：US08941117B2
公开(公告)日：2015-01-27
申请号：US13935345
申请日：2013-07-03
申请人： Avogy, Inc.
发明人： Isik C. Kizilyalli , Hui Nie , Andrew P. Edwards , Linda Romano , David P. Bour , Richard J. Brown , Thomas R. Prunty
IPC分类号： H01L31/0256 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L29/66 , H01L29/808 , H01L29/872 , H01L29/20 , H01L27/06 , H01L27/07 , H01L27/098
CPC分类号： H01L29/66909 , H01L21/823487 , H01L27/0605 , H01L27/0611 , H01L27/0629 , H01L27/0727 , H01L27/098 , H01L29/2003 , H01L29/66143 , H01L29/8083 , H01L29/872
摘要： An integrated device including a vertical III-nitride FET and a Schottky diode includes a drain comprising a first III-nitride material, a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, and a channel region comprising a third III-nitride material coupled to the drift region. The integrated device also includes a gate region at least partially surrounding the channel region, a source coupled to the channel region, and a Schottky contact coupled to the drift region. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride FET and the Schottky diode is along the vertical direction.
摘要翻译：包括垂直III族氮化物FET和肖特基二极管的集成器件包括：包括第一III族氮化物材料的漏极，包括耦合到漏极并沿垂直方向邻近漏极设置的第二III族氮化物材料的漂移区，以及包括耦合到所述漂移区的第三III族氮化物材料的沟道区。集成器件还包括至少部分地围绕沟道区的栅极区域，耦合到沟道区的源极和耦合到漂移区域的肖特基接触。沟道区域沿着垂直方向设置在漏极和源极之间，使得垂直III族氮化物FET和肖特基二极管的工作期间的电流沿垂直方向。

20. 发明授权

US08829574B2 Method and system for a GaN vertical JFET with self-aligned source and gate 有权
标题翻译：具有自对准源极和栅极的GaN垂直JFET的方法和系统
公开(公告)号：US08829574B2
公开(公告)日：2014-09-09
申请号：US13334514
申请日：2011-12-22
申请人： Donald R. Disney , Isik C. Kizilyalli , Hui Nie , Linda Romano , Richard J. Brown , Madhan Raj
发明人： Donald R. Disney , Isik C. Kizilyalli , Hui Nie , Linda Romano , Richard J. Brown , Madhan Raj
IPC分类号： H01L29/808 , H01L21/335 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66924 , H01L21/027 , H01L21/283 , H01L21/308 , H01L29/1095 , H01L29/2003 , H01L29/402 , H01L29/66446 , H01L29/66893 , H01L29/66909 , H01L29/66916 , H01L29/7832 , H01L29/808 , H01L29/8083 , H01L29/8086
摘要： A semiconductor device includes a III-nitride substrate, a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa, and a second III-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a III-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure.
摘要翻译：半导体器件包括III族氮化物衬底，耦合到III族氮化物衬底并具有台面的第一III族氮化物外延层和耦合到台面的顶表面的第二III族氮化物外延层。半导体器件还包括耦合到台面的侧表面的III族氮化物栅极结构，以及被配置为在第二III族氮化物外延层和III族氮化物栅极结构之间提供电绝缘的间隔物。

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