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11. 发明申请

US20160224510A1 VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS USING GRAPHICS PROCESSING INSTRUCTIONS 审中-公开
标题翻译：使用图形处理指令配置可变长度矢量图的矢量处理器
公开(公告)号：US20160224510A1
公开(公告)日：2016-08-04
申请号：US14718432
申请日：2015-05-21
申请人： Optimum Semiconductor Technologies, Inc.
发明人： Mayan Moudgill , Gary J. Nacer , C. John Glossner , Arthur Joseph Hoane , Vitaly Kalashnikov , Sitij Agrawal
IPC分类号： G06F15/80 , G06F9/30
CPC分类号： G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F9/461 , G06F9/462 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
摘要： A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more graphics processing instructions. The computer processor may be implemented as a monolithic integrated circuit.
摘要翻译：公开了一种计算机处理器。计算机处理器可以包括向量单元，其包括向量寄存器文件，其包括至少一个寄存器以保存不同数量的元件。计算机处理器还可以包括处理逻辑，其被配置为使用一个或多个图形处理指令对向量寄存器堆中的变化数量的元件进行操作。计算机处理器可以被实现为单片集成电路。

12. 发明授权

US09372694B2 Reducing data backup and recovery periods in processors 有权
标题翻译：减少处理器中的数据备份和恢复周期
公开(公告)号：US09372694B2
公开(公告)日：2016-06-21
申请号：US13796063
申请日：2013-03-12
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Seiichi Yoneda
IPC分类号： G06F7/38 , G06F7/00 , G06F9/30 , G06F1/32 , G11C5/00 , G06F11/14
CPC分类号： G06F9/30145 , G06F1/32 , G06F1/3287 , G06F9/30083 , G06F9/30141 , G06F11/14 , G11C5/00 , Y02D10/171 , Y02D50/20
摘要： A low-power processor that does not easily malfunction is provided. Alternatively, a low-power processor having high processing speed is provided. Alternatively, a method for driving the processor is provided. In power gating, the processor performs part of data backup in parallel with arithmetic processing and performs part of data recovery in parallel with arithmetic processing. Such a driving method prevents a sharp increase in power consumption in a data backup period and a data recovery period and generation of instantaneous voltage drops and inhibits increases of the data backup period and the data recovery period.
摘要翻译：提供了一个不容易发生故障的低功耗处理器。或者，提供具有高处理速度的低功率处理器。或者，提供用于驱动处理器的方法。在电源门控中，处理器与算术处理并行执行部分数据备份，并与算术处理并行执行部分数据恢复。这种驱动方法防止数据备份期间和数据恢复期间的功率消耗急剧增加，并且产生瞬时电压下降并且阻止数据备份周期和数据恢复期间的增加。

13. 发明申请

US20160172011A1 CMOS TRANSISTOR BIAS TEMPERATURE INSTABILITY BASED CHIP IDENTIFIER 有权
标题翻译： CMOS晶体管偏置温度不稳定性芯片识别器
公开(公告)号：US20160172011A1
公开(公告)日：2016-06-16
申请号：US14568966
申请日：2014-12-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Dimitris P. IOANNOU , Chandrasekharan KOTHANDARAMAN
IPC分类号： G11C7/00
CPC分类号： G11C7/04 , G06F9/30141 , G11C7/24 , G11C11/412 , G11C16/10 , H01L29/42368 , H01L29/7815
摘要： Methods and devices for providing unclonable chip identification are provided. An integrated circuit device includes: a first transistor having a first gate oxide thickness; a second transistor having a second gate oxide thickness different than the first gate oxide thickness; and a reading circuit connected to the first transistor and the second transistor, wherein the reading circuit reads a difference in threshold voltage between the first transistor and the second transistor.
摘要翻译：提供了提供不可克隆芯片识别的方法和设备。集成电路器件包括：具有第一栅极氧化物厚度的第一晶体管; 具有不同于第一栅极氧化物厚度的第二栅极氧化物厚度的第二晶体管; 以及连接到第一晶体管和第二晶体管的读取电路，其中读取电路读取第一晶体管和第二晶体管之间的阈值电压差。

14. 发明授权

US09361027B1 System and method for fast modification of register content 有权
标题翻译：用于快速修改寄存器内容的系统和方法
公开(公告)号：US09361027B1
公开(公告)日：2016-06-07
申请号：US14571898
申请日：2014-12-16
申请人： Texas Instruments Incorporated
发明人： Saket Jalan , Rakesh Channabasappa Yaraduyathinahalli
IPC分类号： G06F12/00 , G06F3/06
CPC分类号： G06F9/30141 , G11C7/1009 , H03K3/037
摘要： The present invention is drawn to a register writing mechanism that does not require reading of the data in the register. In accordance with aspects of the present invention, each register is masked with a making bit provided by a masking component. In a first implementation, the first half of the bit registers are masked using data in the second half of the bit registers. In a second implementation, all the bit registers are masked using a masking word generated by the masking component.
摘要翻译：本发明涉及一种不需要读取寄存器中的数据的寄存器写入机制。根据本发明的方面，每个寄存器被掩蔽组件提供的制作位掩码。在第一个实现中，使用位寄存器的后半部分的数据对位寄存器的前半部分进行掩码。在第二实施例中，使用由掩蔽组件产生的屏蔽字来掩蔽所有位寄存器。

15. 发明授权

US09268738B2 Three-dimensional permute unit for a single-instruction multiple-data processor 有权
标题翻译：用于单指令多数据处理器的三维置换单元
公开(公告)号：US09268738B2
公开(公告)日：2016-02-23
申请号：US13775355
申请日：2013-02-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Harry Barowski , Tim Niggemeier
IPC分类号： G06F15/00 , G06F7/00 , G06F15/80 , G06F9/30
CPC分类号： G06F15/803 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30141 , G06F15/8053
摘要： A three-dimensional (3D) permute unit for a single-instruction-multiple-data stacked processor includes a first vector permute subunit and a second vector permute subunit. The first and second vector permute subunits are arranged in different layers of a 3D chip package. The vector permute subunits are each configured to process a portion of at least two input vectors. A first contact sub-field of the first vector permute subunit is configured to connect output ports of a first crossbar of the first vector permute subunit, holding an intermediate result of the first vector permute subunit, to a second contact sub-field of the second vector permute subunit. A first contact sub-field of the second vector permute subunit is configured to connect output ports of a first crossbar of the second vector permute subunit, holding an intermediate result of the second vector permute subunit, to a second contact sub-field of the first vector permute subunit.
摘要翻译：用于单指令多数据堆叠处理器的三维（3D）置换单元包括第一向量置换子单元和第二向量置换子单元。第一和第二矢量置换子单元布置在3D芯片封装的不同层中。向量置换子单元被配置为处理至少两个输入向量的一部分。第一矢量置换子单元的第一接触子场被配置为将保持第一矢量置换子单元的中间结果的第一矢量置换子单元的第一交叉开关的输出端口连接到第二矢量置换子单元的第二接触子场，载体置换亚基。第二矢量置换子单元的第一接触子场被配置为将保持第二矢量置换子单元的中间结果的第二矢量置换子单元的第一交叉开关的输出端口连接到第一矢量置换子单元的第一接触子场，载体置换亚基。

16. 发明授权

US09268571B2 Selective coupling of an address line to an element bank of a vector register file 有权
标题翻译：选择性地将地址线耦合到向量寄存器文件的元素库
公开(公告)号：US09268571B2
公开(公告)日：2016-02-23
申请号：US13654730
申请日：2012-10-18
申请人： QUALCOMM Incorporated
发明人： Ajay Anant Ingle , Marc M. Hoffman , Deepak Mathew
IPC分类号： G06F12/00 , G06F9/30
CPC分类号： G06F9/30141 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/3012
摘要： A method includes selectively coupling a first address line of a plurality of address lines and a second address line of the plurality of address lines to a first element bank of a plurality of element banks of a vector register file according to a selection pattern. The method also includes accessing data stored within the first element bank that is selectively addressed by the first address line via a single read port.
摘要翻译：一种方法包括根据选择模式将多个地址线的第一地址线和多个地址线的第二地址线选择性地耦合到向量寄存器堆的多个元素组的第一元素组。该方法还包括通过单个读取端口访问由第一地址线选择性寻址的存储在第一元素库内的数据。

17. 发明授权

US09164769B2 Analyzing data flow graph to detect data for copying from central register file to local register file used in different execution modes in reconfigurable processing array 有权
标题翻译：分析数据流图，以检测从可重构处理阵列中的不同执行模式中使用的中央寄存器文件到本地寄存器文件的复制数据
公开(公告)号：US09164769B2
公开(公告)日：2015-10-20
申请号：US12962741
申请日：2010-12-08
申请人： Won-Sub Kim , Tai-Song Jin , Dong-Hoon Yoo , Bernhard Egger , Jin-Seok Lee
发明人： Won-Sub Kim , Tai-Song Jin , Dong-Hoon Yoo , Bernhard Egger , Jin-Seok Lee
IPC分类号： G06F9/318 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30189 , G06F9/3012 , G06F9/30141 , G06F9/3887 , G06F9/3889
摘要： A reconfigurable array is provided. The reconfigurable array includes a Very Long Instruction Word (VLIW) mode and a Coarse-Grained Array (CGA) mode. When the VLIW mode is converted to the CGA mode, instead of sharing a central register file between the VLIW mode and the CGA mode, live data to be used in the CGA mode is copied from the central register file to local register files.
摘要翻译：提供可重构阵列。可重配置阵列包括超长指令字（VLIW）模式和粗粒子阵列（CGA）模式。当VLIW模式转换为CGA模式时，不是在VLIW模式和CGA模式之间共享中央寄存器文件，而是将CGA模式中使用的实时数据从中央寄存器文件复制到本地寄存器文件。

18. 发明申请

US20150277998A1 Prioritising Events to Which a Processor is to Respond 有权
标题翻译：处理器要响应的事件的优先级
公开(公告)号：US20150277998A1
公开(公告)日：2015-10-01
申请号：US14667755
申请日：2015-03-25
申请人： Imagination Technologies Limited
发明人： David William Knox , Adrian John Anderson
IPC分类号： G06F9/54 , G06F9/30
CPC分类号： G06F9/542 , G06F9/30141 , G06F9/4818
摘要： A computer system comprises a processor (106) configured to respond to events from a plurality of sources, and a prioritisation module (104) implemented in hardware and configured to prioritise the events for the processor. The prioritisation module comprises one or more decision modules (108) comprising multiple, prioritised inputs (110) configured to receive respective event flags relating to events from respective sources. The decision module stores a source identifier of the source corresponding to the highest priority asserted event flag. The processor can read the stored source identifier to identify the source of an event to which the processor is to respond. In this way, the decision as to which event a processor should respond to next is offloaded from the processor and implemented in hardware in the prioritisation module. This can reduce the workload of the processor and thereby result in a more efficient computer system.
摘要翻译：计算机系统包括被配置为响应来自多个源的事件的处理器（106）和以硬件实现并被配置为对处理器的事件进行优先级排列的优先化模块（104）。优先化模块包括一个或多个决策模块（108），其包括被配置为接收与来自各个源的事件相关的相应事件标志的多个优先输入（110）。决策模块存储与最高优先权有效事件标志对应的源的源标识符。处理器可以读取存储的源标识符以识别处理器要响应的事件的源。以这种方式，关于处理器应该对下一个响应的事件的决定从处理器中卸载并在优先级模块中以硬件实现。这可以减少处理器的工作量，从而导致更高效的计算机系统。

19. 发明申请

US20150269118A1 Apparatus and Method for Processing an Instruction Matrix Specifying Parallel and Dependent Operations 有权
公开(公告)号：US20150269118A1
公开(公告)日：2015-09-24
申请号：US14733827
申请日：2015-06-08
申请人： Soft Machines, Inc.
发明人： Mohammad A. Abdallah
IPC分类号： G06F15/80 , G06F9/38 , G06F9/30
CPC分类号： G06F15/8007 , G06F7/483 , G06F7/5318 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30109 , G06F9/3012 , G06F9/30123 , G06F9/30141 , G06F9/3016 , G06F9/30181 , G06F9/30189 , G06F9/3824 , G06F9/3828 , G06F9/3838 , G06F9/3851 , G06F9/3853 , G06F9/3867 , G06F9/3885 , G06F9/3887 , G06F9/3889 , G06F9/3891 , G06F15/80
摘要： A matrix of execution blocks form a set of rows and columns. The rows support parallel execution of instructions and the columns support execution of dependent instructions. The matrix of execution blocks process a single block of instructions specifying parallel and dependent instructions.

20. 发明授权

US08775724B2 Memory system in which extension function can easily be set 有权
标题翻译：扩展功能可以轻松设置的内存系统
公开(公告)号：US08775724B2
公开(公告)日：2014-07-08
申请号：US13560028
申请日：2012-07-27
申请人： Shinichi Matsukawa , Akihisa Fujimoto
发明人： Shinichi Matsukawa , Akihisa Fujimoto
IPC分类号： G06F12/02 , G06F9/30 , G06F3/06
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F9/3004 , G06F9/30141 , G06F2003/0697
摘要： According to one embodiment, a non-transitory medium, a controller, a memory, an extension function section, and an extension register. The controller controls the non-transitory medium. The memory which is serving as a work area is connected to the controller. The extension function section is controlled by the controller. The extension register which is provided on the memory is provided with a certain block length capable of defining an extension function of the extension function section. The controller processes a first command to write header data of a command to operate the extension function section to the extension function section through the extension register, and a second command to read header data of a response from the extension function section through the extension register.
摘要翻译：根据一个实施例，非暂时介质，控制器，存储器，扩展功能部分和扩展寄存器。控制器控制非暂时介质。用作工作区的存储器连接到控制器。扩展功能部分由控制器控制。提供在存储器上的扩展寄存器具有能够定义扩展功能部分的扩展功能的特定块长度。控制器通过扩展寄存器处理第一命令来写入扩展功能部分的扩展功能部分的命令的头部数据，以及通过扩展寄存器从扩展功能部分读出响应的标题数据的第二命令。

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