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11. 发明授权

US09857980B2 Memory resource optimization method and apparatus 有权
公开(公告)号：US09857980B2
公开(公告)日：2018-01-02
申请号：US15135822
申请日：2016-04-22
申请人： HUAWEI TECHNOLOGIES CO., LTD.
发明人： Lei Liu , Chengyong Wu , Xiaobing Feng
IPC分类号： G06F3/06 , G06F9/50 , G06F11/34 , G06F12/0811 , G06F12/0842 , G06F12/0897 , G06F12/084
CPC分类号： G06F3/0605 , G06F3/0631 , G06F3/0644 , G06F3/0653 , G06F3/0679 , G06F9/5016 , G06F11/3409 , G06F11/3433 , G06F11/3471 , G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0897 , G06F2201/81 , G06F2212/1041 , G06F2212/282 , G06F2212/6042 , G06F2212/653
摘要： Embodiments of the present invention provide a memory resource optimization method and apparatus, relate to the computer field, solve a problem that existing multi-level memory resources affect each other, and optimize an existing single partitioning mechanism. A specific solution is: obtaining performance data of each program in a working set by using a page coloring technology, obtaining a category of each program in light of a memory access frequency, selecting, according to the category of each program, a page coloring-based partitioning policy corresponding to the working set, and writing the page coloring-based partitioning policy to an operating system kernel, to complete corresponding page coloring-based partitioning processing. The present invention is used to eliminate or reduce mutual interference of processes or threads on a memory resource in light of a feature of the working set, thereby improving overall performance of a computer.

12. 发明申请

US20080055617A1 Page coloring with color inheritance for memory pages 有权
标题翻译：页面着色与内存页面的颜色继承
公开(公告)号：US20080055617A1
公开(公告)日：2008-03-06
申请号：US11513984
申请日：2006-08-31
申请人： Uday Savagaonkar
发明人： Uday Savagaonkar
IPC分类号： G06F15/00
CPC分类号： G06F12/1458 , G06F12/1009 , G06F12/145 , G06F2212/653
摘要： Apparatuses, methods, and media for page coloring with color inheritance for memory pages are disclosed. Some embodiments may include an interface to access a memory and a paging unit including translation logic, inheritance logic, and comparison logic. The translation logic translates a first address to a second address based on an entry in a data structure, wherein the first address is provided by an instruction stored in a first page in the memory and the entry includes a base address of a second page in the memory including the second address and a color of the second page. The inheritance logic may determine an effective current page color of the first page based on a color of the first page. The comparison logic may compare the effective current page color of the first page to the color of the second page. Other embodiments are disclosed and claimed.
摘要翻译：公开了用于内存页面的具有彩色继承的页面着色的装置，方法和媒体。一些实施例可以包括访问存储器的接口和包括翻译逻辑，继承逻辑和比较逻辑的寻呼单元。翻译逻辑基于数据结构中的条目将第一地址转换为第二地址，其中第一地址由存储在存储器中的第一页中的指令提供，并且条目包括第二地址的基地址存储器，其包括第二地址和第二页的颜色。继承逻辑可以基于第一页的颜色来确定第一页的有效的当前页面颜色。比较逻辑可以将第一页的有效当前页面颜色与第二页面的颜色进行比较。公开和要求保护其他实施例。

13. 发明授权

US07085890B2 Memory mapping to reduce cache conflicts in multiprocessor systems 失效
标题翻译：内存映射以减少多处理器系统中的缓存冲突
公开(公告)号：US07085890B2
公开(公告)日：2006-08-01
申请号：US10782362
申请日：2004-02-19
申请人： Sujatha Kashyap
发明人： Sujatha Kashyap
IPC分类号： G06F12/08
CPC分类号： G06F12/1054 , G06F2212/653
摘要： Methods, systems, and computer program products are disclosed for mapping a virtual memory page to a real memory page frame in a multiprocessing environment that supports a multiplicity of operating system images. Typical embodiments include retrieving into an operating system image, from memory accessible to a multiplicity of operating system images, a most recently used cache color for a cache, where the cache is shared by the operating system image with at least one other operating system image; selecting a new cache color in dependence upon the most recently used cache color; selecting in the operating system image a page frame in dependence upon the new cache color; and storing in the memory the new cache color as the most recently used cache color for the cache.
摘要翻译：公开了方法，系统和计算机程序产品，用于在支持多个操作系统图像的多处理环境中将虚拟存储器页面映射到实际存储器页面帧。典型的实施例包括从多个操作系统图像可访问的存储器检索操作系统映像，用于高速缓存的最近使用的高速缓存颜色，其中高速缓存由至少一个其他操作系统映像由操作系统映像共享; 根据最近使用的缓存颜色选择新的缓存颜色; 根据新的高速缓存颜色在操作系统映像中选择页面帧; 并将新的高速缓存颜色存储在存储器中作为高速缓存的最近使用的高速缓存颜色。

14. 发明授权

US5913222A Color correction method in a virtually addressed and physically indexed cache memory in the event of no cache hit 失效
标题翻译：在没有高速缓存命中的情况下，虚拟寻址和物理索引高速缓冲存储器中的色彩校正方法
公开(公告)号：US5913222A
公开(公告)日：1999-06-15
申请号：US727660
申请日：1997-02-03
申请人： Jochen Liedtke
发明人： Jochen Liedtke
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/1054 , G06F2212/653
摘要： In a virtually addressed and physically indexed cache memory, the allocation of a color of a cache entry can be changed for a color allocation of the virtual and physical pages by assigning a color information to each cache entry, by which a second cache address operation is executed after an unsuccessful first cache address operation. Should there still be no cache hit, another cache addressing is attempted by means of a color correction, i.e. an indexing of the cache memory using, among others, the physical color. Should this cache address operation also fail to produce a cache hit, there is a cache miss.
摘要翻译： PCT No.PCT / EP95 / 01378 Sec。 371日期1997年2月3日 102（e）日期1997年2月3日PCT提交1995年4月12日PCT公布。出版物WO95 / 28678 日期1995年10月26日在虚拟寻址和物理索引的高速缓冲存储器中，可以通过将颜色信息分配给每个高速缓存条目来改变对于虚拟和物理页面的颜色分配的高速缓存条目的颜色分配，由此在第一缓存地址操作不成功之后执行第二高速缓存地址操作。如果仍然没有高速缓存命中，则通过颜色校正来尝试另一个高速缓存寻址，即，使用诸如物理颜色的高速缓冲存储器的索引。如果此缓存地址操作也无法产生缓存命中，则会出现缓存未命中。

15. 发明授权

US5226133A Two-level translation look-aside buffer using partial addresses for enhanced speed 失效
标题翻译：使用部分地址进行增强速度的两级翻译
公开(公告)号：US5226133A
公开(公告)日：1993-07-06
申请号：US444594
申请日：1989-12-01
申请人： George S. Taylor , Michael P. Farmwald
发明人： George S. Taylor , Michael P. Farmwald
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/1054 , G06F2212/653
摘要： A translation of a portion of a virtual page number to a portion of a physical page number in a "TLB slice." The slice translation is used to index into a physical cache memory which has virtual tags in addition to physical tags and whose addresses are physical. By comparing the virtual tag to the input virtual address page number, it can be determined whether there was a hit or a miss in the combination of the TLB slice and the cache memory. By translating only a few bits of the virtual address to a few bits of a physical address, the speed of the device is greatly enhanced. This increased speed is achieved by making the TLB slice direct-mapped and by taking advantage of its small size to build it with special hardware (either high-speed RAM (random access memory) or with latches and multiplexers). There is no separate comparison at the TLB slice output for determining a TLB slice hit. The subsequent cache tag comparison is used to indicate both whether the translation was correct and whether there was a cache hit. To achieve this dual purpose comparison, however, a virtual tag must be combined with a physical cache to determine whether there is a hit, since the entire virtual address has not been translated and therefore there is no translated physical address to compare with a physical tag.

16. 发明授权

US09984003B2 Mapping processing method for a cache address in a processor to provide a color bit in a huge page technology 有权
公开(公告)号：US09984003B2
公开(公告)日：2018-05-29
申请号：US15257506
申请日：2016-09-06
申请人： Huawei Technologies Co., Ltd.
发明人： Zehan Cui , Licheng Chen , Mingyu Chen
IPC分类号： G06F12/00 , G06F12/1027 , G06F12/0802 , G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0895 , G06F12/0897 , G06F12/1009
CPC分类号： G06F12/1027 , G06F12/0802 , G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0895 , G06F12/0897 , G06F12/1009 , G06F2212/1016 , G06F2212/152 , G06F2212/6042 , G06F2212/651 , G06F2212/653 , G06F2212/657
摘要： A mapping processing method and apparatus for a cache address, where the method includes acquiring a physical address corresponding to an access address sent by a processing core, where the physical address includes a physical page number (PPN) and a page offset, mapping the physical address to a Cache address, where the Cache address includes a Cache set index 1, a Cache tag, a Cache set index 2, and a Cache block offset in sequence, where the Cache set index 1 with a high-order bit and the Cache set index 2 with a low-order bit together form a Cache set index, and the Cache set index 1 falls within a range of the PPN. Some bits of a PPN of a huge page PPN are mapped to a set index of a Cache so that the bits can be colored by an operating system.

17. 发明申请

US20180011638A1 MEMORY RESOURCE OPTIMIZATION METHOD AND APPARATUS 有权
公开(公告)号：US20180011638A1
公开(公告)日：2018-01-11
申请号：US15712296
申请日：2017-09-22
申请人： HUAWEI TECHNOLOGIES CO.,LTD.
发明人： Lei Liu , Chengyong Wu , Xiaobing Feng
IPC分类号： G06F3/06 , G06F11/34 , G06F9/50
CPC分类号： G06F3/0605 , G06F3/0631 , G06F3/0644 , G06F3/0653 , G06F3/0679 , G06F9/5016 , G06F11/3409 , G06F11/3433 , G06F11/3471 , G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0897 , G06F2201/81 , G06F2212/1041 , G06F2212/282 , G06F2212/6042 , G06F2212/653
摘要： Embodiments of the present invention provide a memory resource optimization method and apparatus, relate to the computer field, solve a problem that existing multi-level memory resources affect each other, and optimize an existing single partitioning mechanism. A specific solution is: obtaining performance data of each program in a working set by using a page coloring technology, obtaining a category of each program in light of a memory access frequency, selecting, according to the category of each program, a page coloring-based partitioning policy corresponding to the working set, and writing the page coloring-based partitioning policy to an operating system kernel, to complete corresponding page coloring-based partitioning processing. The present invention is used to eliminate or reduce mutual interference of processes or threads on a memory resource in light of a feature of the working set, thereby improving overall performance of a computer.

18. 发明申请

US20160239213A1 MEMORY RESOURCE OPTIMIZATION METHOD AND APPARATUS 有权
标题翻译：存储资源优化方法和设备
公开(公告)号：US20160239213A1
公开(公告)日：2016-08-18
申请号：US15135822
申请日：2016-04-22
申请人： HUAWEI TECHNOLOGIES CO.,LTD.
发明人： Lei Liu , Chenyong Wu , Xiaobing Feng
IPC分类号： G06F3/06 , G06F12/08
CPC分类号： G06F3/0605 , G06F3/0631 , G06F3/0644 , G06F3/0653 , G06F3/0679 , G06F9/5016 , G06F11/3409 , G06F11/3433 , G06F11/3471 , G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0897 , G06F2201/81 , G06F2212/1041 , G06F2212/282 , G06F2212/6042 , G06F2212/653
摘要： Embodiments of the present invention provide a memory resource optimization method and apparatus, relate to the computer field, solve a problem that existing multi-level memory resources affect each other, and optimize an existing single partitioning mechanism. A specific solution is: obtaining performance data of each program in a working set by using a page coloring technology, obtaining a category of each program in light of a memory access frequency, selecting, according to the category of each program, a page coloring-based partitioning policy corresponding to the working set, and writing the page coloring-based partitioning policy to an operating system kernel, to complete corresponding page coloring-based partitioning processing. The present invention is used to eliminate or reduce mutual interference of processes or threads on a memory resource in light of a feature of the working set, thereby improving overall performance of a computer.
摘要翻译：本发明的实施例提供了一种与计算机领域相关的存储器资源优化方法和装置，解决了现有多级存储器资源相互影响的问题，并优化了现有的单分区机制。一个具体的解决方案是：通过使用页面着色技术在工作集中获取每个节目的演奏数据，根据存储器访问频率获得每个节目的类别，根据每个节目的类别选择一个页面着色 - 与工作集相对应的分区策略，并将基于页面着色的分区策略写入操作系统内核，完成相应的基于页面着色的分区处理。本发明用于根据工作组的特征消除或减少存储器资源上的进程或线程的相互干扰，从而提高计算机的整体性能。

19. 发明申请

US20130275649A1 Access Optimization Method for Main Memory Database Based on Page-Coloring 有权
标题翻译：基于页面着色的主内存数据库访问优化方法
公开(公告)号：US20130275649A1
公开(公告)日：2013-10-17
申请号：US13514291
申请日：2012-05-16
申请人： Yan-Song Zhang , Shan Wang , Xuan Zhou , Min Jiao , Zhan-Wei Wang
发明人： Yan-Song Zhang , Shan Wang , Xuan Zhou , Min Jiao , Zhan-Wei Wang
IPC分类号： G06F12/10
CPC分类号： G06F12/1045 , G06F2212/653
摘要： An access optimization method for a main memory database based on page-coloring is described. An access sequence of all data pages of a weak locality dataset is ordered by page-color, and all the data pages are grouped by page-color, and then all the data pages of the weak locality dataset are scanned in a sequence of page-color grouping. Further, a number of memory pages having the same page-color are preset as a page-color queue, in which the page-color queue serves as a memory cache before a memory page is loaded into a CPU cache; the data page of the weak locality dataset first enters the page-color queue in an asynchronous mode, and is then loaded into the CPU cache to complete data processing. Accordingly, cache conflicts between datasets with different data locality strengths can be effectively reduced.
摘要翻译：描述了基于页面着色的主存储数据库的访问优化方法。弱位置数据集的所有数据页的访问序列按页面颜色排序，所有数据页按页面颜色分组，然后按照页面颜色顺序扫描弱位置数据集的所有数据页面，颜色分组。此外，将具有相同页面颜色的多个存储器页面预设为页面颜色队列，其中在将存储器页面加载到CPU高速缓存之前，页面颜色队列用作存储器高速缓存; 弱位置数据集的数据页首先以异步模式进入页面颜色队列，然后加载到CPU缓存中以完成数据处理。因此，可以有效地减少具有不同数据局部性强度的数据集之间的缓存冲突。

20. 发明授权

US07913040B2 Managing working set use of a cache via page coloring 有权
标题翻译：通过页面着色来管理缓存的工作集
公开(公告)号：US07913040B2
公开(公告)日：2011-03-22
申请号：US12781172
申请日：2010-05-17
申请人： Bradford Beckmann , Bradley M. Waters
发明人： Bradford Beckmann , Bradley M. Waters
IPC分类号： G06F13/00
CPC分类号： G06F12/1054 , G06F12/0842 , G06F2212/653
摘要： A processor cache is indexed by a group of distinct page colors. The use of this cache by different working sets is controlled using page coloring. Translations of virtual addresses of the instructions and/or data of a working set are constrained to physical addresses the page colors of which are in a subgroup of the group of distinct page colors.
摘要翻译：处理器缓存由一组不同的页面颜色索引。使用页面着色来控制不同工作集使用此缓存。指令和/或工作集的数据的虚拟地址的翻译被限制为其页面颜色位于不同页面颜色组的子组中的物理地址。

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