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11. 发明申请

US20140245090A1 PARALLEL SCAN DISTRIBUTORS AND COLLECTORS AND PROCESS OF TESTING INTEGRATED CIRCUITS 审中-公开
标题翻译：并行扫描分配器和收集器以及测试集成电路的过程
公开(公告)号：US20140245090A1
公开(公告)日：2014-08-28
申请号：US14268073
申请日：2014-05-02
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177
CPC分类号： G01R31/2851 , G01R31/31715 , G01R31/3177 , G01R31/318536 , G01R31/318555 , G01R31/318563 , G01R31/31919
摘要： An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together. The scan distributor and collector circuits can be formed in core circuits (704). The core circuits then can be connected to other core circuits and functional circuits with simple connections to the parallel scan circuits through the scan distributor and collector circuits.
摘要翻译：具有并行扫描路径（824-842,924-942）的集成电路（70）包括一对或一对扫描分配器（800,900）和扫描收集器（844,944）电路。扫描路径将激励测试数据应用于集成电路上的功能电路（702），并从功能电路接收响应测试数据。扫描分配器电路（800）从外围接合焊盘（802）接收串行测试数据，并将其分配到每个并行扫描路径。扫描收集器电路（844）从并行扫描路径收集测试数据并将其应用于外围接合焊盘（866）。这使得更长的并行扫描路径能够连接到功能电路。扫描分配器和集电极电路可以分别串联连接以提供并行连接到更平行的扫描路径。此外，多路复用器电路（886,890）可以选择性地将成对的扫描分配器和集电极电路连接在一起。扫描分配器和集电极电路可以形成在核心电路（704）中。然后，核心电路可以通过扫描分配器和集电极电路与并行扫描电路的简单连接连接到其他核心电路和功能电路。

12. 发明授权

US08749258B2 Parallel scan paths with three bond pads, distributors and collectors 有权
标题翻译：具有三个焊盘，分配器和收集器的并行扫描路径
公开(公告)号：US08749258B2
公开(公告)日：2014-06-10
申请号：US13657115
申请日：2012-10-22
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3187
CPC分类号： G01R31/2851 , G01R31/31715 , G01R31/3177 , G01R31/318536 , G01R31/318555 , G01R31/318563 , G01R31/31919
摘要： An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together. The scan distributor and collector circuits can be formed in core circuits (704). The core circuits then can be connected to other core circuits and functional circuits with simple connections to the parallel scan circuits through the scan distributor and collector circuits.
摘要翻译：具有并行扫描路径（824-842,924-942）的集成电路（70）包括一对或一对扫描分配器（800,900）和扫描收集器（844,944）电路。扫描路径将激励测试数据应用于集成电路上的功能电路（702），并从功能电路接收响应测试数据。扫描分配器电路（800）从外围接合焊盘（802）接收串行测试数据，并将其分配到每个并行扫描路径。扫描收集器电路（844）从并行扫描路径收集测试数据并将其应用于外围接合焊盘（866）。这使得更长的并行扫描路径能够连接到功能电路。扫描分配器和集电极电路可以分别串联连接以提供并行连接到更平行的扫描路径。此外，多路复用器电路（886,890）可以选择性地将成对的扫描分配器和集电极电路连接在一起。扫描分配器和集电极电路可以形成在核心电路（704）中。然后，核心电路可以通过扫描分配器和集电极电路与并行扫描电路的简单连接连接到其他核心电路和功能电路。

13. 发明申请

US20130278288A1 IC OUTPUT SIGNAL PATH WITH SWITCH, BUS HOLDER, AND BUFFER 审中-公开
公开(公告)号：US20130278288A1
公开(公告)日：2013-10-24
申请号：US13855955
申请日：2013-04-03
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： H03K19/173
CPC分类号： H03K19/173 , G01R31/31713 , G01R31/31715 , G01R31/318572
摘要： An electronic integrated circuit includes a signal path connected between the functional logic (15) thereof and an external output terminal. The signal path includes a switch (S), a bus holder circuit (121B), and an output buffer (19).

14. 发明申请

US20130243141A1 COMMUNICATION SYSTEM, DATA TRANSMITTER, AND DATA RECEIVER CAPABLE OF DETECTING INCORRECT RECEIPT OF DATA 有权
标题翻译：通信系统，数据发送器和数据接收器，能够检测数据不正确的接收
公开(公告)号：US20130243141A1
公开(公告)日：2013-09-19
申请号：US13873941
申请日：2013-04-30
申请人： MEGACHIPS CORPORATION
发明人： Ryuichi MORIIZUMI
IPC分类号： H04L7/00
CPC分类号： H04L7/0091 , G01R31/31715 , G01R31/3187 , H04L1/0061 , H04L2007/045
摘要： A transmitter cyclic pattern having a pattern length of N bits is generated and converted into an M-bit transmitter parallel data stream, where N≠M. A bit-sequence altered transmitter parallel data stream is generated by performing a transmitter altering process, converted into a serial data and transmitted together with a clock signal. The serial data is received and converted into an M-bit receiver parallel data stream, and a bit-sequence restored parallel data stream is generated by performing a process opposite to the transmitter altering process. A receiver cyclic pattern is generated by using bits in the bit-sequence restored parallel data stream and converted into an M-bit reference parallel data stream, and a bit-sequence altered reference parallel data stream is generated by performing a process same as the transmitter altering process and compared with the received parallel data to test if the data is correctly received.
摘要翻译：产生具有N比特的模式长度的发射机循环模式，并将其转换为M比特发射机并行数据流，其中N≤M。通过执行发射机改变处理，转换成串行数据并与时钟信号一起传输，产生位序列改变的发射机并行数据流。串行数据被接收并转换成M位接收器并行数据流，并且通过执行与发送器改变处理相反的处理来生成比特序列恢复的并行数据流。通过使用比特序列恢复的并行数据流中的比特来生成接收机循环模式并将其转换成M比特参考并行数据流，并且通过执行与发射机相同的处理来生成比特序列改变的参考并行数据流更改流程并与收到的并行数据进行比较，以测试数据是否正确接收。

15. 发明授权

US08531197B2 Integrated circuit die, an integrated circuit package and a method for connecting an integrated circuit die to an external device 有权
标题翻译：集成电路管芯，集成电路封装以及将集成电路管芯连接到外部器件的方法
公开(公告)号：US08531197B2
公开(公告)日：2013-09-10
申请号：US13054122
申请日：2008-07-17
申请人： Yefim-Haim Fefer , Valery Neiman , Sergey Sofer
发明人： Yefim-Haim Fefer , Valery Neiman , Sergey Sofer
IPC分类号： G01R31/3187
CPC分类号： G01R31/31715
摘要： An integrated circuit die comprises an electronic circuit and one or more output ports for outputting signals from the die via an external impedance, to a load, external from the die. The output port is connected to the electronic circuit. The die is further provided with an on-die sampling oscilloscope circuit connected to the output port, for measuring a waveform of the outputted signals.
摘要翻译：集成电路管芯包括电子电路和一个或多个输出端口，用于将来自管芯的信号经由外部阻抗输出到管芯外部的负载。输出端口连接到电子电路。模具还设置有连接到输出端口的管芯采样示波器电路，用于测量输出信号的波形。

16. 发明授权

US08441285B2 Latching control buffer between functional logic and tri-state output buffer 失效
标题翻译：功能逻辑和三态输出缓冲器之间的锁存控制缓冲器
公开(公告)号：US08441285B2
公开(公告)日：2013-05-14
申请号：US13286423
申请日：2011-11-01
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： H03K19/173
CPC分类号： H03K19/173 , G01R31/31713 , G01R31/31715 , G01R31/318572
摘要： An electronic integrated circuit includes a signal path connected between the functional logic (15) thereof and an external output terminal. The signal path includes a switch (S), a bus holder circuit (121B), and an output buffer (19).
摘要翻译：电子集成电路包括连接在其功能逻辑（15）和外部输出端之间的信号路径。信号路径包括开关（S），总线保持器电路（121B）和输出缓冲器（19）。

17. 发明授权

US08401812B2 Tester, method for testing a device under test and computer program 有权
标题翻译：测试仪，被测设备的测试方法和计算机程序
公开(公告)号：US08401812B2
公开(公告)日：2013-03-19
申请号：US11989731
申请日：2006-12-22
申请人： Martin Schmitz
发明人： Martin Schmitz
IPC分类号： G01R17/00 , G01R17/02 , G01R17/04 , G01R31/02
CPC分类号： G01R31/31926 , G01R31/31715 , G01R31/31919
摘要： A tester for testing a device under test has a first channel unit and a second channel unit. The first channel unit has a corresponding first pin connection for a signal from a device under test, a corresponding first test processor adapted to process, at least partially, data obtained from the first pin connection, and a corresponding first memory coupled with the first test processor and adapted to store data provided by the first test processor. The first channel unit is adapted to transfer at least a part of the data obtained from the first pin connection to the second channel unit as transfer data. The second channel unit has a corresponding second test processor adapted to process, at least partly, the transfer data from the first channel unit.
摘要翻译：用于测试被测设备的测试仪具有第一通道单元和第二通道单元。第一通道单元具有用于来自被测器件的信号的对应的第一引脚连接，适用于至少部分地处理从第一引脚连接获得的数据的对应的第一测试处理器以及与第一测试相结合的对应的第一存储器处理器并且适于存储由第一测试处理器提供的数据。第一通道单元适于将从第一引脚连接获得的数据的至少一部分传送到第二通道单元作为传送数据。第二通道单元具有适于至少部分地处理来自第一通道单元的传送数据的对应的第二测试处理器。

18. 发明申请

US20120317451A1 PROBELESS TESTING OF PAD BUFFERS ON WAFER 有权
标题翻译：垫片缓冲区的无阻试验
公开(公告)号：US20120317451A1
公开(公告)日：2012-12-13
申请号：US13591347
申请日：2012-08-22
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177 , G01R31/31715 , G01R31/318505 , G01R31/318511 , G01R31/318533 , G01R31/318558 , G01R31/318572 , G01R31/318594 , G11C29/006 , G11C29/022 , G11C29/48 , G11C2029/3202
摘要： The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.
摘要翻译：测试晶片上的集成电路管芯的外围电路（350,360，ESD，BH），而不会物理接触管芯的接合焊盘。

19. 发明授权

US08175823B2 Probing analog signals 有权
标题翻译：探测模拟信号
公开(公告)号：US08175823B2
公开(公告)日：2012-05-08
申请号：US12316900
申请日：2008-12-17
申请人： Amir Mezer , Assaf Benhamou
发明人： Amir Mezer , Assaf Benhamou
IPC分类号： H03K5/153
CPC分类号： G01R31/3163 , G01R31/31715
摘要： A device, comprising a monitoring slicer adapted to repeatedly sample an internal analog signal to provide a sequence of digital outputs indicating a result of a comparison of the level of the internal analog signal to a reference voltage and an operative unit adapted to perform a task of the device and provide a result without using digital outputs from the monitoring slicer.
摘要翻译：一种装置，包括监视限幅器，适于反复取样内部模拟信号，以提供指示内部模拟信号的电平与参考电压的比较结果的数字输出序列，以及适于执行任务的操作单元该设备并提供结果，而不使用来自监控限幅器的数字输出。

20. 发明申请

US20120096324A1 TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT 有权
标题翻译： JTAG大连环境中的测试压缩
公开(公告)号：US20120096324A1
公开(公告)日：2012-04-19
申请号：US13330788
申请日：2011-12-20
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/317
CPC分类号： G01R31/3177 , G01R31/31715 , G01R31/3172 , G01R31/31725 , G01R31/318547
摘要： The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.
摘要翻译：本公开描述了当设备以与其他设备的JTAG菊花链配置存在时用于控制设备的TCA电路的新颖的方法和设备。当设备与其他设备（例如在使用该设备的客户系统中）放置在JTAG菊花链配置中时，这些方法和设备允许在设备制造期间使用的TCA测试模式集被重用。在本公开中还提供和描述了另外的实施例。

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