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11. 发明申请

US20060114032A1 Clock frequency detect with programmable jitter tolerance 失效
标题翻译：具有可编程抖动容限的时钟频率检测
公开(公告)号：US20060114032A1
公开(公告)日：2006-06-01
申请号：US11000439
申请日：2004-11-30
申请人： Charles Geer , Robert Shearer
发明人： Charles Geer , Robert Shearer
IPC分类号： H03D13/00
CPC分类号： G01R23/005 , H03D13/00
摘要： An apparatus and method is disclosed for programmable determination of frequency, phase, and jitter relationship of a first clock and a second clock in an electronic system. In a first, initialization, mode, a first register and a second register are initialized with a first bit pattern and a second bit pattern, respectively. In a second, normal, mode, the first clock is coupled to the first register and the second clock is coupled to the second register. A compare unit observes the bit patterns of the first and second registers and reports when one or more predetermined relationships between the first clock and the second clock occur.
摘要翻译：公开了用于可编程确定电子系统中第一时钟和第二时钟的频率，相位和抖动关系的装置和方法。首先，初始化，模式，第一寄存器和第二寄存器分别以第一位模式和第二位模式初始化。在第二正常模式中，第一时钟耦合到第一寄存器，第二时钟耦合到第二寄存器。当第一时钟和第二时钟之间的一个或多个预定关系发生时，比较单元观察第一和第二寄存器的位模式并报告。

12. 发明授权

US06859026B2 Method and device for verifying frequency of clock signal 有权
标题翻译：用于验证时钟信号频率的方法和装置
公开(公告)号：US06859026B2
公开(公告)日：2005-02-22
申请号：US10624750
申请日：2003-07-22
申请人： Chen-Hua Hsi , Cheng-Yuan Wu , Chih-Hsien Weng
发明人： Chen-Hua Hsi , Cheng-Yuan Wu , Chih-Hsien Weng
IPC分类号： G01R23/00 , G01R31/02
CPC分类号： G01R23/005
摘要： A device for verifying frequency of a clock signal generated from a clock signal generator includes a reference signal generator, a frequency divider and a comparative detector. A reference clock signal and a reset signal are provided by the reference signal generator. The frequency divider in communication with the reference signal generator and the clock signal generator receives and frequency-divides the clock signal into a bi-level divided clock signal in response to the reset signal. Then the comparative detector in communication with the frequency divider and the reference signal generator detects a level of the bi-level divided clock signal in response to the reset signal and the reference clock signal, and verifies frequency of the clock signal according to a period deviation range Te when the bi-level divided clock signal is detected to be a first level from the first to the (p−q)th detected points but a second level at the (p+1)th detected point.
摘要翻译：用于验证从时钟信号发生器产生的时钟信号的频率的装置包括参考信号发生器，分频器和比较检测器。参考信号发生器提供参考时钟信号和复位信号。与参考信号发生器和时钟信号发生器通信的分频器接收并响应于复位信号将时钟信号分频为双电平分频时钟信号。然后与分频器和参考信号发生器通信的比较检测器响应于复位信号和参考时钟信号检测双电平分频时钟信号的电平，并根据周期偏差验证时钟信号的频率当检测到双电平分频时钟信号为从第一检测点到第（pq）检测点的第一电平，而在第（p + 1）检测点处检测到第二电平时，测量范围Te。

13. 发明授权

US06194918B1 Phase and frequency detector with high resolution 有权
标题翻译：相位和频率检测器具有高分辨率
公开(公告)号：US06194918B1
公开(公告)日：2001-02-27
申请号：US09506440
申请日：2000-02-18
申请人： Clarence Jörn Niklas Fransson , Mats Wilhelmsson
发明人： Clarence Jörn Niklas Fransson , Mats Wilhelmsson
IPC分类号： H03D1300
CPC分类号： G01R25/08 , G01R23/005 , G01R23/10
摘要： A phase detector for measuring phase differences between K input signals is provided. The phase detector includes a counter, K first registers and a first subtractor. Each first register receives the counter signal of the counter and a respective input signal for updating a counter value in response to timing information on the input signal. The first subtractor receives the counter values to generate phase difference representing values. A frequency detector is also provided. The first subtractor is substituted by a second subtractor and K second registers are included. Each second register is connected to a respective first register. Each second register receives the counter value of its first register and the same input signal as that of its first register for backing-up the counter value as a back-up counter value in response to the timing information on the input signal. The second subtractor subtracts, for each second register and its first register, the counter values thereof to generate a frequency representing value.
摘要翻译：提供了用于测量K个输入信号之间的相位差的相位检测器。相位检测器包括计数器，K个第一寄存器和第一个减法器。每个第一寄存器接收计数器的计数器信号和用于响应于关于输入信号的定时信息来更新计数器值的相应输入信号。第一个减法器接收计数器值以生成相位差表示值。还提供了频率检测器。第一个减法器由第二个减法器代替，并包括K个第二个寄存器。每个第二寄存器连接到相应的第一寄存器。每个第二寄存器响应于关于输入信号的定时信息，接收其第一寄存器的计数器值和与其第一寄存器相同的输入信号，用于将计数器值备份为备用计数器值。第二减法器对于每个第二寄存器及其第一寄存器，减去其计数器值以产生频率表示值。

14. 发明授权

US5926042A Precision clock frequency detector having reduced supply voltage dependence 失效
标题翻译：精密时钟频率检测器具有降低的电源电压依赖性
公开(公告)号：US5926042A
公开(公告)日：1999-07-20
申请号：US994137
申请日：1997-12-19
申请人： Ronald F. Talaga, Jr.
发明人： Ronald F. Talaga, Jr.
IPC分类号： G01R23/00 , H03K5/153 , H03K5/19 , G01R23/02 , H03D3/00 , H03K9/06
CPC分类号： G01R23/005 , H03K5/153 , H03K5/19
摘要： A clock frequency detector is provided having a precise trip frequency which is insensitive to power supply variations. In one embodiment, the clock frequency detector employs a current source to discharge a capacitor at a constant rate and a gated current source to charge the capacitor at a frequency-dependent rate. If the charge rate exceeds the discharge rate, the capacitor will charge and an output signal is asserted. The gated current source is controlled by an edge-triggered pulse generator which generates pulses of a precise width in response to edges in the input clock signal. To create these pulses, the pulse generator produces an inverted clock signal with delayed transitions and combined this signal with the clock signal. The delayed transitions are created using a capacitor which is charged by a current source. The capacitor is provided with a shunt transistor which drains the charge from the capacitor whenever the clock signal is asserted. When the clock signal is de-asserted, the capacitor is allowed to charge, and an op-amp detects when the capacitor voltage exceeds a reference voltage and asserts an output signal. The reference voltage is also provided using a current source, so the transition delay is independent of changes in the power supply voltage. The clock frequency detector provided herein has a high precision with respect to process variation. A consistent frequency detection performance is achieved which is insensitive to changes in power supply voltage. This advantageously provides microprocessors with an added degree of reliability as higher circuit densities and lower supply voltages are pursued.
摘要翻译：提供了具有对电源变化不敏感的精确跳闸频率的时钟频率检测器。在一个实施例中，时钟频率检测器采用电流源以恒定速率放电电容器和门控电流源，以频率依赖率对电容器充电。如果充电速率超过放电速率，电容器将充电并输出一个输出信号。门控电流源由边沿触发脉冲发生器控制，边沿触发脉冲发生器响应于输入时钟信号中的边沿产生精确宽度的脉冲。为了产生这些脉冲，脉冲发生器产生具有延迟转换的反相时钟信号，并将该信号与时钟信号组合。使用由电流源充电的电容器产生延迟转换。电容器设有分流晶体管，每当时钟信号被断言时，该晶体管从电容器中消耗电荷。当时钟信号被取消置位时，允许电容器充电，并且运算放大器检测电容器电压何时超过参考电压并断言输出信号。参考电压也使用电流源提供，因此转换延迟与电源电压的变化无关。这里提供的时钟频率检测器具有相对于工艺变化的高精度。实现了对电源电压变化不敏感的一致的频率检测性能。这有利地为微处理器提供了更高的可靠性，因为追求更高的电路密度和更低的电源电压。

15. 发明授权

US5657361A Variant frequency detector circuit 失效
标题翻译：变频检波电路
公开(公告)号：US5657361A
公开(公告)日：1997-08-12
申请号：US523602
申请日：1995-09-05
申请人： Yasukuni Inagaki , Hitoshi Takahashi
发明人： Yasukuni Inagaki , Hitoshi Takahashi
IPC分类号： G01R23/00 , H03K9/06 , H03K21/38
CPC分类号： G01R23/005
摘要： A detector circuit for detecting abnormalities in the oscillation frequency of a clock signal, includes a counter and a comparator. The counter is supplied with a reference clock signal, and counts the number of pulses of the reference clock signal to output a signal indicative of the count value. In response to the clock signal, the counter clears the count value. The comparator compares the count value of the counter with a specified value stored in its register, and generates a detection signal indicating whether the frequency of the clock signal is within expected limits, based on the comparison result.
摘要翻译：用于检测时钟信号的振荡频率异常的检测器电路包括计数器和比较器。计数器提供参考时钟信号，并对参考时钟信号的脉冲数进行计数，以输出表示计数值的信号。响应于时钟信号，计数器清除计数值。比较器将计数器的计数值与存储在其寄存器中的指定值进行比较，并且基于比较结果生成指示时钟信号的频率是否在预期限度内的检测信号。

16. 发明授权

US5487097A Period measuring device 失效
标题翻译：周期测量装置
公开(公告)号：US5487097A
公开(公告)日：1996-01-23
申请号：US291285
申请日：1994-08-16
申请人： Makoto Hatakenaka , Haruo Sakurai , Hideo Nagano
发明人： Makoto Hatakenaka , Haruo Sakurai , Hideo Nagano
IPC分类号： G01R23/00 , G01R23/10 , H03K21/00
CPC分类号： G01R23/005 , G01R23/10
摘要： It is an object to accurately obtain the period of the horizontal synchronizing signal in the video signal. The number of internal pulses are measured in a predetermined measurement period defined by the horizontal synchronizing signal. It is assumed that the periods of the horizontal synchronizing signal and the internal pulse are denoted as T.sub.H and T.sub.S, and the measurement period is defined by one period of a divided signal NS which is obtained by N-dividing the horizontal synchronizing signal. In this case, the length of the measurement period is N.multidot.T.sub.H. The period of the horizontal synchronizing signal is obtained when the internal pulse is activated K times in the measurement period. After the measurement period is started, the divided signal NS transits between the Kth activation of the internal pulse and the (K+1)th activation, and the measurement period is ended. Accordingly, there is the relation of T.sub.S .multidot.K
摘要翻译：其目的在于准确地获得视频信号中的水平同步信号的周期。在由水平同步信号定义的预定测量周期内测量内部脉冲的数量。假设水平同步信号和内部脉冲的周期被表示为TH和TS，并且测量周期由通过N分割水平同步信号获得的分频信号NS的一个周期来定义。在这种情况下，测量周期的长度为N×TH。在测量周期内内部脉冲激活K次时，获得水平同步信号的周期。在测量周期开始之后，分频信号NS在内部脉冲的第K次激活和第（K + 1）激活之间转换，并且测量周期结束。因此，存在TSxK

17. 发明授权

US5436927A Method and apparatus for testing frequency symmetry of digital signals 失效
标题翻译：用于测试数字信号频率对称性的方法和装置
公开(公告)号：US5436927A
公开(公告)日：1995-07-25
申请号：US40477
申请日：1993-03-31
申请人： Gary Brady , David Ellis
发明人： Gary Brady , David Ellis
IPC分类号： G01R23/00 , G01R31/30 , H04B3/46 , H04B17/00
CPC分类号： G01R31/30 , G01R23/005
摘要： A first and a second input generating circuits, a first and a second set of counters, and a first and a second comparison circuits are provided to test whether the frequencies of a first and a second periodic digital signal are symmetric. The first and second input generating circuits generate enable inputs for the first and second sets of counters using the first and second digital signals respectively. The first and second sets of counters count the first and second digital signals while the enable inputs are provided. The first comparison circuit monitors the first set of counters, and stops both input generating circuits from providing further enable inputs to both sets of counters, after the first set of counters reaches a predetermined level, thereby stopping both sets of counters from further counting. The second comparison circuit monitors the second set of counters, and issues a control signal indicating the first and second digital signals are symmetric to each other in frequency, if the second set of counters also stops substantially at the predetermined level, i.e. within an acceptable threshold.
摘要翻译：提供第一和第二输入产生电路，第一和第二组计数器以及第一和第二比较电路以测试第一和第二周期数字信号的频率是否对称。第一和第二输入产生电路分别使用第一和第二数字信号产生用于第一和第二组计数器的使能输入。当提供使能输入时，第一组和第二组计数器对第一和第二数字信号进行计数。第一比较电路监视第一组计数器，并且在第一组计数器达到预定电平之后停止两个输入发生电路，以对两组计数器提供进一步的使能输入，从而停止两组计数器进一步计数。第二比较电路监视第二组计数器，并发出指示第一和第二数字信号在频率上彼此对称的控制信号，如果第二组计数器也基本停止在预定电平，即在可接受的阈值内。

18. 发明授权

US4791360A Method and apparatus for simultaneous instantaneous signal frequency measurement 失效
标题翻译：用于同步瞬时信号频率测量的方法和装置
公开(公告)号：US4791360A
公开(公告)日：1988-12-13
申请号：US37846
申请日：1987-04-13
申请人： Andre Gagnon , Myles McMillan , P. Michael Gale
发明人： Andre Gagnon , Myles McMillan , P. Michael Gale
IPC分类号： G01R23/00 , G01R23/165 , G01R23/175 , G01R33/20
CPC分类号： G01R23/175 , G01R23/005 , G01R23/165
摘要： A method and apparatus for performing simultaneous instantaneous signal frequency measurement using a signal sorter in conjunction with a frequency measurement receiver. Simultaneous signals of similar amplitude are received and successively applied to a plurality of either frequency or time dependent signal modifying circuits, via switching circuitry. Respective ones of the received signals are separated with respect to frequency in one or both of amplitude and time from one another via the signal modifying circuits which can be, for instance low pass and high pass filters, or positive and negative dispersive delay lines. In addition, the received signals are applied to a straight-through signal path for transmitting the signals to the frequency measurement receiver unaltered. Signals output from the signal modifying circuits and the straight-through signal path are successively applied to the frequency measurement receiver for detecting the frequency of respective ones of the separated received signals.
摘要翻译：一种使用信号分类器与频率测量接收机一起执行同时瞬时信号频率测量的方法和装置。经由开关电路接收并连续地将多个频率或时间相关的信号修正电路同时施加相同振幅的信号。接收到的信号中的各个信号通过信号修正电路（例如低通滤波器，高通滤波器）或正和负色散延迟线路相互间的振幅和时间中的一个或两个中的频率分离。此外，所接收的信号被施加到直通信号路径，用于将信号发送到频率测量接收机不变。从信号修正电路和直通信号路径输出的信号被连续地施加到频率测量接收机，用于检测分离的接收信号中各个信号的频率。

19. 发明授权

US4785251A Digital frequency and phase comparator 失效
标题翻译：数字频率和相位比较器
公开(公告)号：US4785251A
公开(公告)日：1988-11-15
申请号：US008087
申请日：1987-01-21
申请人： Tetsuo Akiyama , Satoshi Kusano
发明人： Tetsuo Akiyama , Satoshi Kusano
IPC分类号： G01R23/10 , G01R23/00 , G01R25/00 , G01R25/08 , H03K5/26
CPC分类号： G01R25/005 , G01R23/005 , H03K5/26
摘要： A digital frequency and phase comparator for both detecting a frequency of a digital signal and the phase thereof relative to a reference signal, wherein polarity inversions of the output phase different signal and saturated characteristics of the circuit when the phase difference succeeds a predetermined value are eliminated. The inventive digital frequency and phase comparator includes a time counter, an input holding circuit for holding a first and a second count value of the time counter at two different input timings of an input signal, a first arithmetic device for determining one of the frequency and period of the inputs signal in response to the first and second count values held by the input timing holding device, and a second arithmetic device for determining a phase of the input signal relative to a reference signal in response to a selected one of the first and second count values held in the input timing holding device.
摘要翻译：一种数字频率和相位比较器，用于检测数字信号的频率及其相对于参考信号的相位，其中当相位差成为预定值时，输出相位不同信号和饱和特性的极性反转被消除。本发明的数字频率和相位比较器包括时间计数器，用于在输入信号的两个不同输入定时保持时间计数器的第一和第二计数值的输入保持电路，用于确定频率之一和响应于由输入定时保持装置保持的第一和第二计数值的输入信号的周期;以及第二运算装置，用于响应于所选择的第一和第二计数值中的一个，确定输入信号相对于参考信号的相位; 保持在输入定时保持装置中的第二计数值。

20. 发明授权

US4404520A Differential absolute equalization measurement circuit 失效
标题翻译：差分绝对均衡测量电路
公开(公告)号：US4404520A
公开(公告)日：1983-09-13
申请号：US304428
申请日：1981-09-21
申请人： Richard A. Nichols
发明人： Richard A. Nichols
IPC分类号： G01R19/00 , G01R23/00 , H03K5/24 , G01R23/12
CPC分类号： G01R19/0038 , G01R23/005 , H03K5/24
摘要： A circuit for measuring the Differential Absolute Delay Equalization between two data signals (each signal consisting of a data stream and its associated clock) is provided. The circuit generates an equalization error signal which is a composite of error signal and a pedestal voltage. The circuit also generates a replica of the pedestal voltage by taking the algebraic summation of the output of the comparison circuit and the complement of the output of the comparison circuit. The equalization error is the difference between the error signal and the replica pedestal voltage.
摘要翻译：提供了用于测量两个数据信号之间的差分绝对延迟均衡的电路（由数据流及其关联的时钟组成的每个信号）。该电路产生均衡误差信号，其是误差信号和基座电压的复合。电路还通过比较电路的输出和比较电路的输出的补码的代数求和来产生基座电压的复制品。均衡误差是误差信号与复制基座电压之差。

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