专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06194918B1 Phase and frequency detector with high resolution 有权
标题翻译：相位和频率检测器具有高分辨率
公开(公告)号：US06194918B1
公开(公告)日：2001-02-27
申请号：US09506440
申请日：2000-02-18
申请人： Clarence Jörn Niklas Fransson , Mats Wilhelmsson
发明人： Clarence Jörn Niklas Fransson , Mats Wilhelmsson
IPC分类号： H03D1300
CPC分类号： G01R25/08 , G01R23/005 , G01R23/10
摘要： A phase detector for measuring phase differences between K input signals is provided. The phase detector includes a counter, K first registers and a first subtractor. Each first register receives the counter signal of the counter and a respective input signal for updating a counter value in response to timing information on the input signal. The first subtractor receives the counter values to generate phase difference representing values. A frequency detector is also provided. The first subtractor is substituted by a second subtractor and K second registers are included. Each second register is connected to a respective first register. Each second register receives the counter value of its first register and the same input signal as that of its first register for backing-up the counter value as a back-up counter value in response to the timing information on the input signal. The second subtractor subtracts, for each second register and its first register, the counter values thereof to generate a frequency representing value.
摘要翻译：提供了用于测量K个输入信号之间的相位差的相位检测器。相位检测器包括计数器，K个第一寄存器和第一个减法器。每个第一寄存器接收计数器的计数器信号和用于响应于关于输入信号的定时信息来更新计数器值的相应输入信号。第一个减法器接收计数器值以生成相位差表示值。还提供了频率检测器。第一个减法器由第二个减法器代替，并包括K个第二个寄存器。每个第二寄存器连接到相应的第一寄存器。每个第二寄存器响应于关于输入信号的定时信息，接收其第一寄存器的计数器值和与其第一寄存器相同的输入信号，用于将计数器值备份为备用计数器值。第二减法器对于每个第二寄存器及其第一寄存器，减去其计数器值以产生频率表示值。

2. 发明授权

US06172533B2 Phase and frequency detector with high resolution 有权
公开(公告)号：US06172533B2
公开(公告)日：2001-01-09
申请号：US09133151
申请日：1998-08-12
申请人： Clarence Jörn Niklas Fransson , Mats Wilhelmsson
发明人： Clarence Jörn Niklas Fransson , Mats Wilhelmsson
IPC分类号： H03K19195
CPC分类号： G01R25/08 , G01R23/02 , G01R25/005 , H03D13/00
摘要： A phase detector for measuring phase differences between K input signals is provided. The phase detector includes a counter, K first registers and a first subtractor. Each first register receives the counter signal of the counter and a respective input signal for updating a counter value in response to timing information on the input signal. The first subtractor receives the counter values to generate phase difference representing values. A frequency detector is also provided. The first subtractor is substituted by a second subtractor and K second registers are included. Each second register is connected to a respective first register. Each second register receives the counter value of its first register and the same input signal as that of its first register for backing-up the counter value as a back-up counter value in response to the timing information on the input signal. The second subtractor subtracts, for each second register and its first register, the counter values thereof to generate a frequency representing value.

3. 发明授权

US06256360B1 Method for reducing transients in a clock signal generating system 失效
标题翻译：降低时钟信号发生系统瞬变的方法
公开(公告)号：US06256360B1
公开(公告)日：2001-07-03
申请号：US09085027
申请日：1998-05-28
申请人： Mats Göran Wilhelmsson , Clarence Jörn Niklas Fransson
发明人： Mats Göran Wilhelmsson , Clarence Jörn Niklas Fransson
IPC分类号： H04L700
CPC分类号： H03L7/087 , H03L7/07 , H03L7/093 , H04J3/0688
摘要： Methods reduce transients in a redundant clock system forming part of a switch in a telecommunication network. In general, the transients, normally in the form of phase steps, are caused by reconfigurations in the clock system. Examples of reconfiguration are an inclusion or an exclusion of a redundant clock generating circuit, referred to as a plane, or an activation of a network synchronization. These transients are eliminated by successively adding an increment to a variable representative of a physical quantity in the clock generating system. In the case of an inclusion of a plane or an activation of the network synchronization, a positive increment is successively added to the gain of an amplifier. In the case of an exclusion of a plane, an increment is successively added to a phase difference representing signal.
摘要翻译：方法减少形成电信网络中交换机的一部分的冗余时钟系统中的瞬变。一般情况下，瞬态，通常是相位步骤的形式，由时钟系统中的重新配置引起。重新配置的示例是包括或排除被称为平面的冗余时钟生成电路或网络同步的激活。通过在时钟发生系统中连续向表示物理量的变量增加增量来消除这些瞬变。在包括平面或激活网络同步的情况下，将正增量连续地加到放大器的增益上。在排除平面的情况下，相继增加相位差表示信号的增量。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式