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11. 发明公开

US20230365402A1 BONDING PROCESS FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE 审中-公开
公开(公告)号：US20230365402A1
公开(公告)日：2023-11-16
申请号：US18354012
申请日：2023-07-18
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chih-Hang Chang , I-Shi Wang , Jen-Hao Liu
IPC分类号： B81C1/00 , B81C3/00
CPC分类号： B81C1/00238 , B81C1/00269 , B81C1/00888 , B81C3/005 , B81C2201/013 , B81C2201/0143 , B81C2201/0146 , B81C2203/035
摘要： A semiconductor device structure is provided. The semiconductor device structure includes a first substrate including a first face and a second face opposite the first face. A second substrate is bonded to the first face of the first substrate such that the second face of the first substrate faces away from the second substrate. One or more recesses are arranged in the second face of the first substrate and are configured to compensate for thermal expansion or thermal contraction.

12. 发明授权

US10626010B2 Bonding process for forming semiconductor device structure 有权
公开(公告)号：US10626010B2
公开(公告)日：2020-04-21
申请号：US16123719
申请日：2018-09-06
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chih-Hang Chang , I-Shi Wang , Jen-Hao Liu
IPC分类号： B81C1/00 , B81C3/00
CPC分类号： B81C1/00238 , B81C1/00269 , B81C1/00888 , B81C3/005 , B81C2201/013 , B81C2201/0143 , B81C2201/0146 , B81C2203/035
摘要： A method for forming a semiconductor device structure is provided. The method includes receiving a first wafer having multiple predetermined die areas. The method also includes forming a recess in the first wafer, and the recess extends in a direction substantially parallel to an edge of one of the predetermined die areas. The method further includes receiving a second wafer. In addition, the method includes bonding the first wafer and the second wafer at an elevated temperature after the recess is formed.

13. 发明授权

US09862600B2 Chip structure 有权
公开(公告)号：US09862600B2
公开(公告)日：2018-01-09
申请号：US14718152
申请日：2015-05-21
申请人： ams International AG
发明人： Roel Daamen , Hendrik Bouman , Kailash Vijayakumar
IPC分类号： B81C1/00 , H01L23/64 , B81B7/00
CPC分类号： B81C1/00825 , B81B7/0016 , B81B2201/0264 , B81B2203/0127 , B81B2207/015 , B81B2207/03 , B81C2201/0104 , B81C2201/0146 , B81C2203/0735 , H01L23/642
摘要： One example discloses an chip, comprising: a substrate; a first side of a passivation layer coupled to the substrate; a device, having a device height and a cavity, wherein a first device surface is coupled to a second side of the passivation layer which is opposite to the first side of the passivation layer; and a set of structures coupled to the second side of the passivation layer and configured to have a structure height greater than or equal to the device height.

14. 发明申请

US20160340180A1 CHIP STRUCTURE 有权
标题翻译：芯片结构
公开(公告)号：US20160340180A1
公开(公告)日：2016-11-24
申请号：US14718152
申请日：2015-05-21
申请人： ams International AG
发明人： Roel Daamen , Hendrik Bouman , Kailash Vijayakumar
IPC分类号： B81C1/00 , B81B7/00
CPC分类号： B81C1/00825 , B81B7/0016 , B81B2201/0264 , B81B2203/0127 , B81B2207/015 , B81B2207/03 , B81C2201/0104 , B81C2201/0146 , B81C2203/0735 , H01L23/642
摘要： One example discloses an chip, comprising: a substrate; a first side of a passivation layer coupled to the substrate; a device, having a device height and a cavity, wherein a first device surface is coupled to a second side of the passivation layer which is opposite to the first side of the passivation layer; and a set of structures coupled to the second side of the passivation layer and configured to have a structure height greater than or equal to the device height.
摘要翻译：一个实例公开了一种芯片，包括：基板; 耦合到所述衬底的钝化层的第一侧; 具有器件高度和空腔的器件，其中第一器件表面耦合到钝化层的与钝化层的第一侧相对的第二侧; 以及耦合到钝化层的第二侧并且被配置为具有大于或等于器件高度的结构高度的一组结构。

15. 发明申请

US20110174634A1 MACHINE AND METHOD FOR MACHINING A PART BY MICRO-ELECTRICAL DISCHARGE MACHINING 失效
标题翻译：通过微电脑加工加工零件的机器和方法
公开(公告)号：US20110174634A1
公开(公告)日：2011-07-21
申请号：US13119490
申请日：2009-09-09
申请人： Michel Cabrera
发明人： Michel Cabrera
IPC分类号： B23H3/04 , B23H9/00
CPC分类号： B23H3/04 , B23H5/02 , B23H7/065 , B23H7/08 , B23H9/00 , B23H9/08 , B81C2201/0146
摘要： The invention relates to a machine for machining a part by micro-electrical discharge machining, said machine comprising a mechanism (44, 45, 46, 48) for modifying the configuration of the machine so as to alternatively and reversibly switch from a machining configuration to a sharpening configuration in which the tip of a same etching electrode (20) and another electrode (64) are dipped in an electrolyte bath in order to sharpen the tip of the etching electrode by electrochemnical corrosion.
摘要翻译：本发明涉及一种用于通过微放电加工来加工零件的机器，所述机器包括用于修改机器的构造的机构（44,45,46,48），以便可替代地且可逆地从加工构型切换到其中相同的蚀刻电极（20）的尖端和另一个电极（64）被浸入电解质浴中以通过电化学腐蚀来锐化腐蚀电极的尖端的锐化构造。

16. 发明授权

US07655496B1 Metal lift-off systems and methods using liquid solvent and frozen gas 有权
标题翻译：金属剥离系统和使用液体溶剂和冷冻气体的方法
公开(公告)号：US07655496B1
公开(公告)日：2010-02-02
申请号：US11831823
申请日：2007-07-31
申请人： Patrick Franklin , John J. Naughton
发明人： Patrick Franklin , John J. Naughton
IPC分类号： H01L21/00 , H01L21/44 , H01L21/461
CPC分类号： H01L21/0272 , B81C1/00634 , B81C2201/0146
摘要： A method of fabricating a semiconductor device includes patterning a layer of photoresist onto a surface of a wafer to define metal feature areas and residual metal areas. A layer of metal is deposited over the patterned layer of photoresist, the metal layer includes metal feature portions in the metal feature areas, residual metal areas in the residual metal areas, and residual metal flaps at the edges of the metal feature portions. The wafer is sprayed with high-pressure solvent at a pressure to dissolve the layer of photoresist and to physically remove the residual metal portions from the residual metal areas, leaving only at least a portion of the residual metal flaps. The wafer is sprayed with a stream of frozen gas particles to remove the residual metal flaps.
摘要翻译：制造半导体器件的方法包括将光致抗蚀剂层图案化到晶片的表面上以限定金属特征区域和残余金属区域。在图案化的光致抗蚀剂层上沉积金属层，金属层包括金属特征区域中的金属特征部分，残余金属区域中的残余金属区域以及金属特征部分边缘处的残余金属片。在压力下用高压溶剂喷涂晶片，以溶解光致抗蚀剂层，并将物理上从剩余的金属区域除去残留的金属部分，仅留下剩余金属片的至少一部分。用冷冻气体颗粒流喷射晶片以除去残留的金属襟翼。

17. 发明授权

US6140200A Methods of forming void regions dielectric regions and capacitor constructions 有权
标题翻译：形成空隙区电介质区域和电容器结构的方法
公开(公告)号：US6140200A
公开(公告)日：2000-10-31
申请号：US146117
申请日：1998-09-02
申请人： Jerome Michael Eldridge
发明人： Jerome Michael Eldridge
IPC分类号： B81B3/00 , H01L21/02 , H01L21/311 , H01L21/20
CPC分类号： B81C1/00119 , B81C1/00047 , H01L21/31138 , H01L28/40 , B81B2203/0315 , B81B2203/0338 , B81C2201/0109 , B81C2201/0146
摘要： In one aspect, the invention includes a method of forming a void region associated with a substrate, comprising: a) providing a substrate; b) forming a sacrificial mass over the substrate; c) subjecting the mass to hydrogen to convert a component of the mass to a volatile form; and d) volatilizing the volatile form of the component from the mass to leave a void region associated with the substrate. In another aspect, the invention includes a method of forming a capacitor construction, comprising: a) forming a first capacitor electrode over a substrate; b) forming a sacrificial material proximate the first capacitor electrode; c) forming a second capacitor electrode proximate the sacrificial material, the second capacitor electrode being separated from the first capacitor electrode by the sacrificial material, at least one of the first and second electrodes being a metal-comprising layer; and d) subjecting the sacrificial material to conditions which transport a component from the sacrificial material to the metal-comprising layer, the transported component leaving a void region between the first and second capacitor electrodes.
摘要翻译：一方面，本发明包括形成与衬底相关联的空隙区域的方法，包括：a）提供衬底; b）在衬底上形成牺牲物质; c）使所述物质经受氢气将所述物质的组分转化为挥发性形式; 以及d）从所述物质挥发所述组分的挥发性形式以留下与所述基材相关联的空隙区域。另一方面，本发明包括一种形成电容器结构的方法，包括：a）在衬底上形成第一电容器电极; b）在第一电容器电极附近形成牺牲材料; c）在所述牺牲材料附近形成第二电容器电极，所述第二电容器电极通过所述牺牲材料与所述第一电容器电极分离，所述第一和第二电极中的至少一个是含金属的层; 以及d）对所述牺牲材料进行将组分从所述牺牲材料输送到所述含金属层的条件，所述传输部件在所述第一和第二电容器电极之间留下空隙区域。

18. 发明授权

US11897763B2 Capless semiconductor package with a micro-electromechanical system (MEMS) 有权
公开(公告)号：US11897763B2
公开(公告)日：2024-02-13
申请号：US17103796
申请日：2020-11-24
申请人： STMICROELECTRONICS, INC.
发明人： Jefferson Sismundo Talledo
IPC分类号： B81C1/00 , B81B7/00
CPC分类号： B81C1/00309 , B81B7/0061 , B81B2201/0264 , B81B2201/0278 , B81B2207/012 , B81B2207/07 , B81C2201/0108 , B81C2201/0143 , B81C2201/0146
摘要： A semiconductor package that contains an application-specific integrated circuit (ASIC) die and a micro-electromechanical system (MEMS) die. The MEMS die and the ASIC die are coupled to a substrate that includes an opening that extends through the substrate and is in fluid communication with an air cavity positioned between and separating the MEMS die from the substrate. The opening exposes the air cavity to an external environment and, following this, the air cavity exposes a MEMS element of the MEMS die to the external environment. The air cavity separating the MEMS die from the substrate is formed with a method of manufacturing that utilizes a thermally decomposable die attach material.

19. 发明授权

US11840446B2 Fabrication of 3D microelectrodes and use thereof in multi-functional biosystems 有权
公开(公告)号：US11840446B2
公开(公告)日：2023-12-12
申请号：US16908666
申请日：2020-06-22
申请人： UNIVERSITY OF CENTRAL FLORIDA RESEARCH FOUNDATION, INC.
发明人： Swaminathan Rajaraman , Charles Didier , Avra Kundu
IPC分类号： B81C1/00 , B81B1/00 , C12M1/34 , G01N33/50
CPC分类号： B81C1/00111 , B81B1/008 , C12M41/46 , G01N33/5082 , B81B2201/055 , B81C2201/0146
摘要： Disclosed herein is a microelectrode platform that may be used for multiple biosystem applications including cell culturing techniques and biosensing. Also disclosed are microfabrication techniques for inexpensively producing microelectrode platforms.

20. 发明授权

US08709848B2 Method for etched cavity devices 有权
标题翻译：蚀刻腔体装置的方法
公开(公告)号：US08709848B2
公开(公告)日：2014-04-29
申请号：US13088100
申请日：2011-04-15
申请人： Srivatsa G. Kundalgurki , Scott Dye
发明人： Srivatsa G. Kundalgurki , Scott Dye
IPC分类号： H01L21/02 , H01L21/3065
CPC分类号： G01L9/0042 , B81C1/00047 , B81C2201/0123 , B81C2201/0146 , B81C2201/017 , H01L21/02057 , H01L21/30608 , H01L21/3065
摘要： MEMS devices (40) using etched cavities (42) are desirably formed using multiple etching steps. Preliminary cavities (20) formed by locally anisotropic etching to nearly the final depth have irregular (46) sidewalls (44) and steep and/or inconsistent sidewall (44) to bottom (54) intersection angles (48). This leads to less than desired cavity diaphragm (26) burst strengths. Final cavities (42) with smooth sidewalls (50), smaller and consistent sidewall (50) to bottom (54) intersection angles (58), and having more than doubled cavity diaphragm (26) burst strengths are obtained by treating the preliminary cavities (20) with TMAH etchant, preferably relatively dilute TMAH etchant. In a preferred embodiment, a cleaning step is performed between the etching step and the TMAH treatment step to remove any anisotropic etching by-products present on the preliminary cavities' (20) initial sidewalls (44). The multi-step cavity etching procedure is especially useful for forming robust MEMS pressure sensors, but is applicable to any type of MEMS device.
摘要翻译：期望使用多个蚀刻步骤形成使用蚀刻腔（42）的MEMS器件（40）。通过局部各向异性腐蚀形成的接近最终深度的初级腔（20）具有不规则的（46）侧壁（44）和陡峭和/或不一致的侧壁（44）至底部（54）交叉角（48）。这导致比所需的腔膜（26）突发强度小。通过处理预备空腔（2）获得具有平滑侧壁（50），更小且一致的侧壁（50）到底部（54）交叉角（58）并且具有多于两倍的腔隔膜（26）的突出强度的最终腔（42） 20）与TMAH蚀刻剂，优选相对稀释的TMAH蚀刻剂。在优选的实施方案中，在蚀刻步骤和TMAH处理步骤之间进行清洁步骤以去除预备空腔（20）初始侧壁（44）上存在的任何各向异性蚀刻副产物。多阶腔蚀刻程序对于形成坚固的MEMS压力传感器尤其有用，但适用于任何类型的MEMS器件。

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