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11. 发明申请

US20080128691A1 Test structures for development of metal-insulator-metal (MIM) devices 有权
公开(公告)号：US20080128691A1
公开(公告)日：2008-06-05
申请号：US11633930
申请日：2006-12-05
申请人： Steven Avanzino , Suzette K. Pangrle , Manuj Rathor , An Chen , Sameer Haddad , Nicholas Tripsas , Matthew Buynoski
发明人： Steven Avanzino , Suzette K. Pangrle , Manuj Rathor , An Chen , Sameer Haddad , Nicholas Tripsas , Matthew Buynoski
IPC分类号： H01L23/58
CPC分类号： H01L22/32
摘要： In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, and an insulating layer between the first and second electrodes. A portion of the conductor is exposed for access thereto.

12. 发明授权

US08089113B2 Damascene metal-insulator-metal (MIM) device 有权
标题翻译：大马士革金属绝缘子金属（MIM）器件
公开(公告)号：US08089113B2
公开(公告)日：2012-01-03
申请号：US11633929
申请日：2006-12-05
申请人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
发明人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
IPC分类号： H01L29/94 , H01L27/108
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/122 , H01L45/1233 , H01L45/146 , H01L45/1666
摘要： The present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening in the dielectric layer, providing a switching body in the opening, and providing a second conductive body in the opening.
摘要翻译：制造存储器件的本方法包括以下步骤：提供电介质层，在电介质层中提供开口，在电介质层的开口中提供第一导电体，在开口中提供开关体，并提供第二导电体在开口处。

13. 发明授权

US08445913B2 Metal-insulator-metal (MIM) device and method of formation thereof 有权
公开(公告)号：US08445913B2
公开(公告)日：2013-05-21
申请号：US11980213
申请日：2007-10-30
申请人： Steven Avanzino , Tzu-Ning Fang , Swaroop Kaza , Dongxiang Liao , Wai Lo , Christie Marrian , Sameer Haddad
发明人： Steven Avanzino , Tzu-Ning Fang , Swaroop Kaza , Dongxiang Liao , Wai Lo , Christie Marrian , Sameer Haddad
IPC分类号： H01L29/12
CPC分类号： H01L28/40 , H01G4/10 , H01G13/00 , H01L27/101 , H01L28/57 , Y10T29/435
摘要： In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.

14. 发明申请

US20080127480A1 METHOD OF FABRICATING METAL-INSULATOR-METAL (MIM) DEVICE WITH STABLE DATA RETENTION 有权
标题翻译：制造具有稳定数据保持性的金属绝缘体金属（MIM）器件的方法
公开(公告)号：US20080127480A1
公开(公告)日：2008-06-05
申请号：US11633942
申请日：2006-12-05
申请人： Steven Avanzino , Sameer Haddad , An Chen , Yi-Ching Jean Wu , Suzette K. Pangrle , Jeffrey A. Shields
发明人： Steven Avanzino , Sameer Haddad , An Chen , Yi-Ching Jean Wu , Suzette K. Pangrle , Jeffrey A. Shields
IPC分类号： H01S4/00
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1633 , H01L45/1675 , Y10T29/49002
摘要： In the method of fabricating a metal-insulator-metal (MIM) device, a first electrode of α-Ta is provided. The Ta of the first electrode is oxidized to form a Ta2O5 layer on the first electrode. A second electrode of β-Ta is provided on the Ta2O5 layer. Such a device exhibits strong data retention, along with resistance to performance degradation under high temperatures.
摘要翻译：在制造金属 - 绝缘体 - 金属（MIM）器件的方法中，提供了α-Ta的第一电极。在第一电极上氧化第一电极的Ta以形成Ta 2 O 5 O 5层。 β-Ta的第二电极设置在Ta 2 O 5层上。这种器件表现出强大的数据保持性，同时耐高温下的性能降解。

15. 发明申请

US20080123401A1 Damascene metal-insulator-metal (MIM) device with improved scaleability 有权
标题翻译：大马士革金属绝缘体金属（MIM）装置，具有改进的可扩展性
公开(公告)号：US20080123401A1
公开(公告)日：2008-05-29
申请号：US11521204
申请日：2006-09-14
申请人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
发明人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
IPC分类号： G11C11/34 , H01L21/44
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1633 , H01L45/1675 , H01L45/1683
摘要： A present method of fabricating a memory device includes the steps of providing a dielectric layer;, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.
摘要翻译：本发明的制造存储器件的方法包括以下步骤：提供电介质层;在电介质层中提供开口，在开口中提供第一导电体，在开口中提供开关体，第一导电体和开关体填充开口，并且在开关体上提供第二导电体。在替代实施例中，在第一介电层上提供第二电介质层，并且开关体设置在第二电介质层的开口中。

16. 发明授权

US09343666B2 Damascene metal-insulator-metal (MIM) device with improved scaleability 有权
标题翻译：大马士革金属绝缘体金属（MIM）装置，具有改进的可扩展性
公开(公告)号：US09343666B2
公开(公告)日：2016-05-17
申请号：US13529284
申请日：2012-06-21
申请人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael Vanbuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffery A. Shields
发明人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael Vanbuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffery A. Shields
IPC分类号： H01L21/20 , H01L45/00 , H01L27/24
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1633 , H01L45/1675 , H01L45/1683
摘要： A present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.
摘要翻译：制造存储器件的现有方法包括以下步骤：提供电介质层，在电介质层中提供开口，在开口中提供第一导电体，在开口中提供开关体，第一导电体和开关体填充物并且在开关体上设置第二导电体。在替代实施例中，在第一介电层上提供第二电介质层，并且开关体设置在第二电介质层的开口中。

17. 发明申请

US20090109598A1 Metal-insulator-metal (MIM) device and method of formation thereof 有权
标题翻译：金属绝缘体金属（MIM）器件及其形成方法
公开(公告)号：US20090109598A1
公开(公告)日：2009-04-30
申请号：US11980213
申请日：2007-10-30
申请人： Steven Avanzino , Tzu-Ning Fang , Swaroop Kaza , Dongxiang Liao , Wai Lo , Christie Marrian , Sameer Haddad
发明人： Steven Avanzino , Tzu-Ning Fang , Swaroop Kaza , Dongxiang Liao , Wai Lo , Christie Marrian , Sameer Haddad
IPC分类号： H01G4/002 , H01G7/00
CPC分类号： H01L28/40 , H01G4/10 , H01G13/00 , H01L27/101 , H01L28/57 , Y10T29/435
摘要： In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.
摘要翻译：在制造金属 - 绝缘体 - 金属（MIM）器件的方法中，首先提供第一电极。在第一电极上设置氧化物层，在氧化物层上设置保护层。提供通过保护层的开口以暴露氧化物层的一部分，氧化层的暴露部分下方的第一电极的一部分被氧化。提供与氧化物层的暴露部分接触的第二电极。在替代实施例中，可以消除初始提供的氧化物层，并且可以在开口中提供绝缘材料的间隔物。

18. 发明授权

US07468525B2 Test structures for development of metal-insulator-metal (MIM) devices 有权
标题翻译：金属 - 绝缘体 - 金属（MIM）器件的开发测试结构
公开(公告)号：US07468525B2
公开(公告)日：2008-12-23
申请号：US11633930
申请日：2006-12-05
申请人： Steven Avanzino , Suzette K. Pangrle , Manuj Rathor , An Chen , Sameer Haddad , Nicholas Tripsas , Matthew Buynoski
发明人： Steven Avanzino , Suzette K. Pangrle , Manuj Rathor , An Chen , Sameer Haddad , Nicholas Tripsas , Matthew Buynoski
IPC分类号： H01L29/10
CPC分类号： H01L22/32
摘要： In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, and an insulating layer between the first and second electrodes. A portion of the conductor is exposed for access thereto.
摘要翻译：在本发明的电子测试结构中，提供了覆盖基板的导体。电子器件覆盖导体的一部分，并且包括连接到导体的第一电极，第二电极和在第一和第二电极之间的绝缘层。导体的一部分被暴露以便进入其中。

19. 发明授权

US08482959B2 Method of programming, erasing and repairing a memory device 有权
标题翻译：编程，擦除和修复存储设备的方法
公开(公告)号：US08482959B2
公开(公告)日：2013-07-09
申请号：US13324759
申请日：2011-12-13
申请人： Swaroop Kaza , Sameer Haddad
发明人： Swaroop Kaza , Sameer Haddad
IPC分类号： G11C11/00 , G11C11/36
CPC分类号： G11C11/5685 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2213/15 , G11C2213/79
摘要： A method of repairing a memory device is provided. If an erase process is unsuccessful, a repair process is performed. A programmed state of the memory device is determined, A subsequent erase process dependent on the programmed state is performed. Also, a method of programming and erasing a memory device is provided. The memory device includes first and second electrodes and a switching layer therebetween. A first on-state resistance characteristic of the memory device is provided in programming the memory device by application of a first voltage to the gate of a transistor in series with the memory device. Other on-state resistance characteristics of the memory device, different from the first on-state resistance characteristic, may be provided by application of other voltages, different from the first voltage, to the gate of the transistor.
摘要翻译：提供了修复存储器件的方法。如果擦除过程不成功，则执行修复过程。确定存储器件的编程状态。执行取决于编程状态的后续擦除过程。另外，提供了编程和擦除存储器件的方法。存储器件包括第一和第二电极以及它们之间的开关层。提供存储器件的第一导通电阻特性，通过将第一电压施加到与存储器件串联的晶体管的栅极来对存储器件进行编程。可以通过将不同于第一电压的其他电压施加到晶体管的栅极来提供不同于第一导通电阻特性的存储器件的其他导通电阻特性。

20. 发明授权

US06737703B1 Memory array with buried bit lines 失效
标题翻译：内存阵列带埋线
公开(公告)号：US06737703B1
公开(公告)日：2004-05-18
申请号：US10095512
申请日：2002-03-12
申请人： Richard Fastow , Sameer Haddad , Yu Sun
发明人： Richard Fastow , Sameer Haddad , Yu Sun
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： In a memory device, a substrate has a plurality of source/drain regions in the substrate. Between the source/drain regions are trenches filled with oxide. Individual bit lines in the form of conductive regions are provided in the substrate, each bit line being under and running along the oxide in a trench. Each bit line connects to source/drain regions by means of connecting conductive regions extending from that bit line to source/drain regions.
摘要翻译：在存储器件中，衬底在衬底中具有多个源极/漏极区域。在源极/漏极区之间是填充有氧化物的沟槽。导电区域形式的单个位线设置在衬底中，每个位线沿着沟槽中的氧化物在下面并且沿着其延伸。每个位线通过将从该位线延伸的导电区域连接到源极/漏极区域而连接到源极/漏极区域。

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