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11. 发明授权

US07663186B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07663186B2
公开(公告)日：2010-02-16
申请号：US12118159
申请日：2008-05-09
申请人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
发明人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66712 , H01L29/7809
摘要： A semiconductor device includes: a substrate, a surface portion thereof serving as a drain layer; a first main electrode connected to the drain layer; an epitaxial layer formed on the drain layer; a base layer formed on the epitaxial layer; a source layer formed in a base layer surface portion; an insulated trench sandwiched by base layers; a JFET layer formed on trench side walls; an LDD layer formed in a base layer surface portion and connected to the JFET layer around a top face of the trench; a control electrode formed on a gate insulating film formed on an LDD layer surface part, on surfaces of source layer end parts facing each other across the trench, and on a base layer region sandwiched by the LDD and source layers; and a second main electrode connected to the source and base layers sandwiching the control electrode.
摘要翻译：半导体器件包括：衬底，用作漏极层的表面部分; 连接到漏极层的第一主电极; 形成在漏极层上的外延层; 形成在外延层上的基底层; 形成在基层表面部分中的源极层; 由基层夹住的绝缘沟槽; 形成在沟槽侧壁上的JFET层; LDD层，其形成在基底表面部分中并且围绕所述沟槽的顶面连接到所述JFET层; 形成在形成在LDD层表面部分上的栅极绝缘膜上的控制电极，在沟槽之间彼此面对的源极层部分的表面上以及由LDD和源极层夹持的基极层区域; 以及连接到夹持控制电极的源极和基极层的第二主电极。

12. 发明授权

US07061060B2 Offset-gate-type semiconductor device 失效
公开(公告)号：US07061060B2
公开(公告)日：2006-06-13
申请号：US10388509
申请日：2003-03-17
申请人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
发明人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L29/76
CPC分类号： H01L29/402 , H01L21/26586 , H01L29/1045 , H01L29/1079 , H01L29/1083 , H01L29/41725 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/41775 , H01L29/456 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7835
摘要： A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.

13. 发明授权

US06977414B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06977414B2
公开(公告)日：2005-12-20
申请号：US10460407
申请日：2003-06-13
申请人： Kazutoshi Nakamura , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Syotaro Ono , Akio Nakagawa
发明人： Kazutoshi Nakamura , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Syotaro Ono , Akio Nakagawa
IPC分类号： H01L21/285 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7816 , H01L21/28537 , H01L29/0619 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/4238 , H01L29/7801 , H01L29/7802 , H01L29/7809
摘要： A semiconductor device comprises: a semiconductor layer of a first conductivity type; a pair of base regions of a second conductivity type selectively provided on a surface of the semiconductor layer; and source regions of a first conductivity type, each of the source regions being selectively provided on a surface of each of the base regions. The semiconductor device further comprises an electrical field reducing region of a second conductivity type selectively provided on the surface of the semiconductor layer between the pair of the base regions; a gate insulating film provided on the surface of the base regions; a pair of gate electrodes provided on the gate insulating film, each of the gate electrodes being provided on the surface of the base regions between the source region and the electrical field reducing region; and a source electrode connected to the source regions. The electrical field reducing region is isolated from both of the gate electrode and the source electrode.
摘要翻译：半导体器件包括：第一导电类型的半导体层; 选择性地设置在半导体层的表面上的一对第二导电类型的基极区; 以及第一导电类型的源极区域，每个源区域选择性地设置在每个基极区域的表面上。所述半导体器件还包括选择性地设置在所述一对基极区域之间的所述半导体层的表面上的第二导电类型的电场减小区域; 设置在所述基底区域的表面上的栅极绝缘膜; 设置在所述栅极绝缘膜上的一对栅电极，在所述源极区域和所述电场减少区域之间的所述基极区域的表面上设置各栅极电极; 以及与源极区域连接的源电极。电场减少区域与栅极电极和源极电极隔离。

14. 发明申请

US20050127440A1 MOS field effect transistor with reduced on-resistance 审中-公开
标题翻译：具有降低导通电阻的MOS场效应晶体管
公开(公告)号：US20050127440A1
公开(公告)日：2005-06-16
申请号：US11033391
申请日：2005-01-12
申请人： Norio Yasuhara , Akio Nakagawa , Yusuke Kawaguchi , Kazutoshi Nakamura
发明人： Norio Yasuhara , Akio Nakagawa , Yusuke Kawaguchi , Kazutoshi Nakamura
IPC分类号： H01L29/06 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/78 , H01L31/119
CPC分类号： H01L29/7816 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/0886 , H01L29/1045 , H01L29/4175 , H01L29/41766 , H01L29/7801 , H01L29/7818 , H01L29/7824 , H01L29/7833 , H01L29/7835
摘要： A semiconductor substrate includes a first principal plane and a second principal plane opposite this first principal plane. A first semiconductor region is formed on the first principal plane of the semiconductor substrate. Second and third semiconductor regions are formed separately from each other on the first semiconductor region. A gate electrode is formed, via a gate insulator, on the first semiconductor region between the second semiconductor region and the third semiconductor region. An electric conductor is formed up to the semiconductor substrate from the second semiconductor region and electrically connects the second semiconductor region with the semiconductor substrate. A first main electrode is formed on the second principal plane of the semiconductor substrate and is electrically connected to the semiconductor substrate. A second main electrode is formed on the first semiconductor region via insulators and is electrically connected to the third semiconductor region.
摘要翻译：半导体衬底包括第一主平面和与该第一主平面相对的第二主平面。第一半导体区域形成在半导体衬底的第一主平面上。第二半导体区域和第三半导体区域在第一半导体区域上彼此分开地形成。栅电极经由栅极绝缘体形成在第二半导体区域和第三半导体区域之间的第一半导体区域上。从第二半导体区域形成直到半导体衬底的电导体，并且将第二半导体区域与半导体衬底电连接。第一主电极形成在半导体衬底的第二主平面上，并与半导体衬底电连接。第二主电极通过绝缘体形成在第一半导体区上，并与第三半导体区电连接。

15. 发明授权

US06614089B2 Field effect transistor 有权
公开(公告)号：US06614089B2
公开(公告)日：2003-09-02
申请号：US09994646
申请日：2001-11-28
申请人： Kazutoshi Nakamura , Yusuke Kawaguchi , Akio Nakagawa
发明人： Kazutoshi Nakamura , Yusuke Kawaguchi , Akio Nakagawa
IPC分类号： H01L2358
CPC分类号： H01L29/7835 , H01L21/266 , H01L29/0634 , H01L29/1045 , H01L29/36 , H01L29/42368 , H01L29/7824 , H01L2924/0002 , H01L2924/00
摘要： In an N-MOSFET having a Double RESURF structure, an n-drift layer and a p-base layer are formed to be adjacent to each other in the surface of a p-semiconductor active layer. An n+-drain layer and a p-RESURF layer are formed in the surface of the drift layer. An n+-source layer and a p+-contact layer are formed to be adjacent to each other in the surface of the base layer. A gate electrode is arranged through a gate insulating film on that region of the base layer, which is located between the drift layer and the source layer. The RESURF layer is doped with a p-carrier impurity at a dose that is set to be gradually higher from the drain layer side to the base layer side.

16. 发明授权

US06605844B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06605844B2
公开(公告)日：2003-08-12
申请号：US09949611
申请日：2001-09-12
申请人： Kazutoshi Nakamura , Yusuke Kawaguchi , Akio Nakagawa
发明人： Kazutoshi Nakamura , Yusuke Kawaguchi , Akio Nakagawa
IPC分类号： H01L2362
CPC分类号： H01L27/0262 , H01L27/0266 , H01L29/7436 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes an active layer of a first conductive type. A base layer of a second conductive type is selectively formed on a surface region of said active layer. A source layer of the first conductive type is selectively formed on a surface region of the base layer. An anode layer of the second conductive type is selectively formed on a surface region of the active layer, the anode layer being spaced from the base layer. A drain layer of the first conductive type is formed on a surface region between the base layer and the anode layer. A resistive layer of the first conductive type is formed on a surface region between the base layer and the drain layer. And, a gate electrode is formed above a region of the base layer between the source layer and the active layer, a gate insulating film being disposed between the base layer and the gate electrode. A source electrode is formed on the surface of the base layer and the source layer, while a drain electrode is formed on the surface of the drain layer and the anode layer.
摘要翻译：半导体器件包括第一导电类型的有源层。第二导电类型的基层选择性地形成在所述有源层的表面区域上。第一导电类型的源极层选择性地形成在基底层的表面区域上。第二导电类型的阳极层选择性地形成在有源层的表面区域上，阳极层与基底层间隔开。第一导电类型的漏极层形成在基极层和阳极层之间的表面区域上。第一导电类型的电阻层形成在基极层和漏极层之间的表面区域上。并且，在源极层和有源层之间的基极层的区域的上方形成有栅电极，栅极绝缘膜设置在基极层和栅极电极之间。源极电极形成在基极层和源极层的表面上，而漏电极形成在漏极层和阳极层的表面上。

17. 发明授权

US06552389B2 Offset-gate-type semiconductor device 有权
公开(公告)号：US06552389B2
公开(公告)日：2003-04-22
申请号：US10013874
申请日：2001-12-13
申请人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
发明人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L2976
CPC分类号： H01L29/402 , H01L21/26586 , H01L29/1045 , H01L29/1079 , H01L29/1083 , H01L29/41725 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/41775 , H01L29/456 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7835
摘要： A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.

18. 发明授权

US06380566B1 Semiconductor device having FET structure with high breakdown voltage 有权
标题翻译：具有具有高击穿电压的FET结构的半导体器件
公开(公告)号：US06380566B1
公开(公告)日：2002-04-30
申请号：US09669737
申请日：2000-09-26
申请人： Tomoko Matsudai , Yusuke Kawaguchi , Kazutoshi Nakamura , Hirofumi Nagano , Akio Nakagawa
发明人： Tomoko Matsudai , Yusuke Kawaguchi , Kazutoshi Nakamura , Hirofumi Nagano , Akio Nakagawa
IPC分类号： H01L2974
CPC分类号： H01L29/7824 , H01L29/0847 , H01L29/7816 , H01L29/7835 , H01L29/78624
摘要： An N-MOSFET is formed on an SOI substrate consisting of a semiconductor substrate, an insulating layer and an n−-active layer. A p-well layer, an n-RESURF layer, and an n-diffusion layer are formed in the surface of the n−-active layer between a source electrode and a drain electrode by means of impurity diffusion. The diffusion regions of the p-well layer and the n-RESURF layer overlap with each other. An end of the n-RESURF layer reaches a position below a gate electrode. The diffusion regions of the p-well layer and the n-diffusion layer do not overlap with each other, so that the n-RESURF layer has a region in direct contact with the n−-active layer between the p-well layer and the n-diffusion layer.
摘要翻译：在由半导体衬底，绝缘层和n-活性层组成的SOI衬底上形成N-MOSFET。通过杂质扩散在源电极和漏电极之间的n-活性层的表面上形成p阱层，n-RESURF层和n扩散层。 p阱层和n-RESURF层的扩散区域彼此重叠。 n-RESURF层的一端到达栅电极下方的位置。 p阱层和n扩散层的扩散区域彼此不重叠，使得n-RESURF层具有与p阱层和p阱层之间的n-活性层直接接触的区域 n扩散层。

19. 发明授权

US07067876B2 Semiconductor device 失效
公开(公告)号：US07067876B2
公开(公告)日：2006-06-27
申请号：US10139324
申请日：2002-05-07
申请人： Norio Yasuhara , Kazutoshi Nakamura , Yusuke Kawaguchi
发明人： Norio Yasuhara , Kazutoshi Nakamura , Yusuke Kawaguchi
IPC分类号： H01L29/76
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/0696 , H01L29/1045 , H01L29/1087 , H01L29/4175 , H01L29/41766 , H01L29/4238
摘要： A semiconductor device comprises a semiconductor substrate; a semiconductor layer having a higher resistance than that of said semiconductor substrate and provided on a top surface of said semiconductor substrate; a gate electrode provided on a gate insulating film on the top surface of said semiconductor layer; a drain layer of a first conductivity type selectively provided in a location in said semiconductor layer in one side of said gate electrode; a drain electrode connected to said drain layer; a source layer of the first conductivity type selectively provided in a location in said semiconductor layer in the other side of said gate electrode; an element-side connecting portion selectively provided on said semiconductor layer, which does not reach a channel portion between said source layer and said drain layer of said semiconductor layer and also does not reach to said semiconductor substrate, and which is in contact with said source layer and has lower resistance than that of said semiconductor layer; a contact-side connecting portion selectively provided on said semiconductor layer, having lower resistance than said semiconductor layer and extending deeper toward said semiconductor substrate than said element-side connecting portion; a first source electrode connecting said source layer, said element-side connect portion and said contact-side connect portion; and a bottom electrode provided on the bottom surface of said semiconductor substrate in connection therewith.

20. 发明授权

US07633153B2 Semiconductor module 失效
标题翻译：半导体模块
公开(公告)号：US07633153B2
公开(公告)日：2009-12-15
申请号：US11778516
申请日：2007-07-16
申请人： Kazuo Shimokawa , Takashi Koyanagawa , Masako Ooishi , Tatsuya Yamada , Osamu Usuda , Yoshiki Endo , Taiki Miura , Masaki Toyoshima , Ichiro Omura , Akio Nakagawa , Kenichi Matsushita , Yusuke Kawaguchi , Haruki Arai , Hiroshi Takei , Tomohiro Kawano , Noriaki Yoshikawa , Morio Takahashi , Yasuhito Saito , Masahiro Urase
发明人： Kazuo Shimokawa , Takashi Koyanagawa , Masako Ooishi , Tatsuya Yamada , Osamu Usuda , Yoshiki Endo , Taiki Miura , Masaki Toyoshima , Ichiro Omura , Akio Nakagawa , Kenichi Matsushita , Yusuke Kawaguchi , Haruki Arai , Hiroshi Takei , Tomohiro Kawano , Noriaki Yoshikawa , Morio Takahashi , Yasuhito Saito , Masahiro Urase
IPC分类号： H01L23/10
CPC分类号： H01L23/3121 , H01L21/565 , H01L23/36 , H01L23/367 , H01L23/4822 , H01L23/49805 , H01L23/49844 , H01L24/16 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/84 , H01L25/0655 , H01L25/165 , H01L29/4175 , H01L29/7802 , H01L29/7806 , H01L29/7809 , H01L29/7813 , H01L29/7835 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/40225 , H01L2224/73153 , H01L2224/73204 , H01L2224/73253 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.
摘要翻译：半导体模块包括安装板。多个电源开关器件芯片通过倒装芯片接合安装在安装板上。芯片具有上表面和下表面，并且被配置为面向安装板的上表面。通过倒装芯片接合将驱动IC芯片安装在安装板上。驱动IC芯片用于驱动形成在多个功率开关器件芯片中的晶体管的栅极。多个散热构件分别位于多个功率开关器件芯片的下表面上。提供树脂构件以将单个封装中的多个功率开关器件芯片和驱动IC芯片密封。

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