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11. 发明申请

US20050176201A1 Spacer for a split gate flash memory cell and a memory cell employing the same 有权
标题翻译：分离栅闪存单元的间隔器和采用其的存储单元
公开(公告)号：US20050176201A1
公开(公告)日：2005-08-11
申请号：US10775290
申请日：2004-02-10
申请人： Yuan-Hung Liu , Chih-Ta Wu , Yeur-Luen Tu , Chi-Hsin Lo , Chia-Shiung Tsai
发明人： Yuan-Hung Liu , Chih-Ta Wu , Yeur-Luen Tu , Chi-Hsin Lo , Chia-Shiung Tsai
IPC分类号： H01L21/336 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/423
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A spacer, a split gate flash memory cell, and related method of forming the same. In one aspect, a composite spacer includes a first spacer insulating layer having a first deposition distribution that varies as a function of a location on a substrate. The composite spacer also includes a second spacer insulating layer having a second deposition distribution that varies in substantial opposition to the first deposition distribution. In another aspect, a composite spacer includes a first spacer insulating layer having a substantially uniform deposition distribution across a surface thereof. The composite spacer also includes a second spacer insulating layer having a varying deposition distribution with a thinner composition in selected regions of the memory cell. In another aspect, a coupling spacer provides for a conductive layer that extends between a floating gate and a substrate insulating layer adjacent a source recessed into the substrate of the memory cell.
摘要翻译：间隔物，分裂栅极闪存单元及其相关方法。在一个方面，一种复合间隔物包括具有第一沉积分布的第一间隔绝缘层，其随着基底上的位置而变化。复合间隔物还包括具有与第一沉积分布基本相反地变化的第二沉积分布的第二间隔绝缘层。在另一方面，复合间隔物包括在其表面上具有基本均匀的沉积分布的第一间隔绝缘层。复合间隔物还包括具有在存储单元的选定区域中具有较薄组成的不同沉积分布的第二间隔绝缘层。在另一方面，耦合间隔物提供了在浮置栅极和与凹入到存储器单元的衬底中的源极相邻的衬底绝缘层之间延伸的导电层。

12. 发明申请

US20050215004A1 Method of forming MIM capacitor electrodes 有权
标题翻译：形成MIM电容器电极的方法
公开(公告)号：US20050215004A1
公开(公告)日：2005-09-29
申请号：US10811657
申请日：2004-03-29
申请人： Chih-Ta Wu , Kuo-Yin Lin , Tsung-Hsun Huang , Chung-Yi Yu , Lan-Lin Chao , Yeur-Luen Tu , Hsing-Lien Lin , Chia-Shiung Tsai
发明人： Chih-Ta Wu , Kuo-Yin Lin , Tsung-Hsun Huang , Chung-Yi Yu , Lan-Lin Chao , Yeur-Luen Tu , Hsing-Lien Lin , Chia-Shiung Tsai
IPC分类号： H01G4/005 , H01L21/02 , H01L21/28 , H01L21/3205 , H01L21/44 , H01L23/522 , H01L29/06
CPC分类号： H01L28/60 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A novel method for forming electrodes in the fabrication of an MIM (metal-insulator-metal) capacitor, is disclosed. The method improves MIM capacitor performance by preventing plasma-induced damage to a dielectric layer during deposition of a top electrode on the dielectric layer, as well as by reducing or preventing the formation of an interfacial layer between the dielectric layer and the electrode or electrodes, in fabrication of the MIM capacitor. The method typically includes the patterning of crown-type capacitor openings in a substrate; depositing a bottom electrode in each of the crown openings; subjecting the bottom electrode to a rapid thermal processing (RTP) or furnace anneal step; depositing a dielectric layer on the annealed bottom electrode; depositing a top electrode on the dielectric layer using a plasma-free CVD (chemical vapor deposition) or ALD (atomic layer deposition) process; and patterning the top electrode of each MIM capacitor.
摘要翻译：公开了一种用于在MIM（金属 - 绝缘体 - 金属）电容器的制造中形成电极的新颖方法。该方法通过在电介质层上的顶部电极沉积期间防止等离子体对电介质层的损伤，以及通过减少或防止介电层和电极或电极之间的界面层的形成来改善MIM电容器性能，在MIM电容器的制造中。该方法通常包括在衬底中图案化冠状电容器开口; 在每个冠状开口中沉积底部电极; 对底部电极进行快速热处理（RTP）或炉退火步骤; 在退火的底部电极上沉积介电层; 使用无等离子体CVD（化学气相沉积）或ALD（原子层沉积）工艺在电介质层上沉积顶部电极; 并对每个MIM电容器的顶部电极进行构图。

13. 发明授权

US07199001B2 Method of forming MIM capacitor electrodes 有权
标题翻译：形成MIM电容器电极的方法
公开(公告)号：US07199001B2
公开(公告)日：2007-04-03
申请号：US10811657
申请日：2004-03-29
申请人： Chih-Ta Wu , Kuo-Yin Lin , Tsung-Hsun Huang , Chung-Yi Yu , Lan-Lin Chao , Yeur-Luen Tu , Hsing-Lien Lin , Chia-Shiung Tsai
发明人： Chih-Ta Wu , Kuo-Yin Lin , Tsung-Hsun Huang , Chung-Yi Yu , Lan-Lin Chao , Yeur-Luen Tu , Hsing-Lien Lin , Chia-Shiung Tsai
IPC分类号： H01L21/8242
CPC分类号： H01L28/60 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A novel method for forming electrodes in the fabrication of an MIM (metal-insulator-metal) capacitor, is disclosed. The method improves MIM capacitor performance by preventing plasma-induced damage to a dielectric layer during deposition of a top electrode on the dielectric layer, as well as by reducing or preventing the formation of an interfacial layer between the dielectric layer and the electrode or electrodes, in fabrication of the MIM capacitor. The method typically includes the patterning of crown-type capacitor openings in a substrate; depositing a bottom electrode in each of the crown openings; subjecting the bottom electrode to a rapid thermal processing (RTP) or furnace anneal step; depositing a dielectric layer on the annealed bottom electrode; depositing a top electrode on the dielectric layer using a plasma-free CVD (chemical vapor deposition) or ALD (atomic layer deposition) process; and patterning the top electrode of each MIM capacitor.
摘要翻译：公开了一种用于在MIM（金属 - 绝缘体 - 金属）电容器的制造中形成电极的新颖方法。该方法通过在电介质层上的顶部电极沉积期间防止等离子体对电介质层的损伤，以及通过减少或防止介电层和电极或电极之间的界面层的形成来改善MIM电容器性能，在MIM电容器的制造中。该方法通常包括在衬底中图案化冠状电容器开口; 在每个冠状开口中沉积底部电极; 对底部电极进行快速热处理（RTP）或炉退火步骤; 在退火的底部电极上沉积介电层; 使用无等离子体CVD（化学气相沉积）或ALD（原子层沉积）工艺在电介质层上沉积顶部电极; 并对每个MIM电容器的顶部电极进行构图。

14. 发明申请

US20070096230A1 Magnetic memory cells and manufacturing methods 有权
标题翻译：磁记忆体和制造方法
公开(公告)号：US20070096230A1
公开(公告)日：2007-05-03
申请号：US11610760
申请日：2006-12-14
申请人： Yuan-Hung Liu , Chih-Ta Wu , Lan-Lin Chao , Yeur-Luen Tu , Wen-Chin Lin , Chia-Shiung Tsai
发明人： Yuan-Hung Liu , Chih-Ta Wu , Lan-Lin Chao , Yeur-Luen Tu , Wen-Chin Lin , Chia-Shiung Tsai
IPC分类号： H01L43/00 , H01L29/82
CPC分类号： H01L43/12 , H01L27/228
摘要： An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.
摘要翻译：改进的磁阻存储器件具有减小的磁存储元件与用于写入磁存储器元件的导电存储器线之间的距离。通过根据包括在磁阻存储元件上形成掩模并在掩模层上形成绝缘层，然后使用平坦化处理去除绝缘层的部分的方法，通过形成改进的磁阻存储器件来简化缩短的距离。然后可以在掩模层中形成导电通孔，例如使用镶嵌工艺。然后可以在掩模层和导电通孔上形成导电存储器线。

15. 发明授权

US07554145B2 Magnetic memory cells and manufacturing methods 有权
标题翻译：磁记忆体和制造方法
公开(公告)号：US07554145B2
公开(公告)日：2009-06-30
申请号：US11610760
申请日：2006-12-14
申请人： Yuan-Hung Liu , Chih-Ta Wu , Lan-Lin Chao , Yeur-Luen Tu , Wen-Chin Lin , Chia-Shiung Tsai
发明人： Yuan-Hung Liu , Chih-Ta Wu , Lan-Lin Chao , Yeur-Luen Tu , Wen-Chin Lin , Chia-Shiung Tsai
IPC分类号： H01L29/76
CPC分类号： H01L43/12 , H01L27/228
摘要： An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.
摘要翻译：改进的磁阻存储器件具有减小的磁存储元件与用于写入磁存储器元件的导电存储器线之间的距离。通过根据包括在磁阻存储元件上形成掩模并在掩模层上形成绝缘层，然后使用平坦化处理去除绝缘层的部分的方法，通过形成改进的磁阻存储器件来简化缩短的距离。然后可以在掩模层中形成导电通孔，例如使用镶嵌工艺。然后可以在掩模层和导电通孔上形成导电存储器线。

16. 发明申请

US20060183318A1 MAGNETIC MEMORY CELLS AND MANUFACTURING METHODS 有权
标题翻译：磁记忆细胞和制造方法
公开(公告)号：US20060183318A1
公开(公告)日：2006-08-17
申请号：US10906357
申请日：2005-02-15
申请人： Yuan-Hung Liu , Chih-Ta Wu , Lan-Lin Chao , Yeur-Luen Tu , Wen-Chin Lin , Chia-Shiung Tsai
发明人： Yuan-Hung Liu , Chih-Ta Wu , Lan-Lin Chao , Yeur-Luen Tu , Wen-Chin Lin , Chia-Shiung Tsai
IPC分类号： H01L21/4763 , H01L21/00
CPC分类号： H01L43/12 , H01L27/228
摘要： An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.
摘要翻译：改进的磁阻存储器件具有减小的磁存储元件与用于写入磁存储器元件的导电存储器线之间的距离。通过根据包括在磁阻存储元件上形成掩模并在掩模层上形成绝缘层，然后使用平坦化处理去除绝缘层的部分的方法，通过形成改进的磁阻存储器件来简化缩短的距离。然后可以在掩模层中形成导电通孔，例如使用镶嵌工艺。然后可以在掩模层和导电通孔上形成导电存储器线。

17. 发明授权

US07172908B2 Magnetic memory cells and manufacturing methods 有权
公开(公告)号：US07172908B2
公开(公告)日：2007-02-06
申请号：US10906357
申请日：2005-02-15
申请人： Yuan-Hung Liu , Chih-Ta Wu , Lan-Lin Chao , Yeur-Luen Tu , Wen-Chin Lin , Chia-Shiung Tsai
发明人： Yuan-Hung Liu , Chih-Ta Wu , Lan-Lin Chao , Yeur-Luen Tu , Wen-Chin Lin , Chia-Shiung Tsai
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , H01L27/228
摘要： An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.

18. 发明授权

US06486025B1 Methods for forming memory cell structures 有权
标题翻译：形成记忆细胞结构的方法
公开(公告)号：US06486025B1
公开(公告)日：2002-11-26
申请号：US10047265
申请日：2002-01-14
申请人： Yuan-Hung Liu , Yeur-Luen Tu , Chia-Shiung Tsai , Min-Hwa Chi , Chih-Hsing Yu
发明人： Yuan-Hung Liu , Yeur-Luen Tu , Chia-Shiung Tsai , Min-Hwa Chi , Chih-Hsing Yu
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L27/10811 , H01L28/84 , H01L28/91
摘要： Within a first of a pair of methods for forming a memory cell structure there is employed a sacrificial spacer layer formed adjacent a capacitor structure and subsequently stripped therefrom to provide an air gap void interposed between a bitline stud layer and the capacitor structure. Within a second of the pair of methods for forming a memory cell structure there is employed a topographically variable thickness masking layer as a self aligned mask layer for forming a patterned capacitor plate layer from a topographic blanket capacitor plate layer. The methods provide for readily forming the memory cell structure with enhanced performance.
摘要翻译：在用于形成存储单元结构的一对方法中的第一种中，采用邻近电容器结构形成并随后从其中剥离的牺牲隔离层，以提供位于位线支柱层和电容器结构之间的气隙空隙。在用于形成存储单元结构的一对方法的一秒钟内，采用形貌可变的厚度掩模层作为自对准掩模层，用于从地形覆盖电容器板层形成图案化电容器板层。该方法提供了容易地形成具有增强性能的存储单元结构。

19. 发明授权

US06780731B1 HDP gap-filling process for structures with extra step at side-wall 失效
标题翻译： HDP间隙填充过程，用于侧壁额外加工的结构
公开(公告)号：US06780731B1
公开(公告)日：2004-08-24
申请号：US10225803
申请日：2002-08-22
申请人： Yeur-Luen Tu , Tsung-Hsun Huang , Chung-Yi Yu , Yuan-Hung Liu
发明人： Yeur-Luen Tu , Tsung-Hsun Huang , Chung-Yi Yu , Yuan-Hung Liu
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A multi-step HDP deposition and sputtering process for void-free filling of high aspect ratio trenches having stepped cross-sectional profiles. The method is particularly applicable to filling trenches formed in triply layered substrates comprising a silicon first layer, an oxide second layer and a nitride third layer, wherein the nitride layer is pulled back from the edge of the trench opening and forms a step. The method allows the void-free filling of such a trench without dam aging the nitride layer in the process. Briefly, the essence of the method is the formation of deposited layers on the side walls of the trench wherein the first layer is deposited with a high deposition to sputtering ratio and low bias power to form a layer with an overhang at the upper surface of the trench. This deposition if followed by a sputtering process to form an enlarged opening in that overhang. This approach is found to prevent the formation of an overhang at the position of the step, whereat it would cause progressive restriction of the trench throat and void formation.
摘要翻译：一种多步骤HDP沉积和溅射方法，用于无缝填充具有阶梯形横截面轮廓的高纵横比沟槽。该方法特别适用于填充形成在包括硅第一层，氧化物第二层和氮化物第三层的三层分层衬底中的沟槽，其中氮化物层从沟槽开口的边缘被拉回并形成一个台阶。该方法允许这种沟槽的无空隙填充，而不会使该过程中的氮化物层老化。简而言之，该方法的本质是在沟槽的侧壁上形成沉积层，其中第一层以高沉积至溅射比沉积，并且具有低偏压能力以在上表面形成具有突出端的层沟。该沉积如果随后是溅射工艺以在该突出端形成扩大的开口。发现这种方法可以防止在台阶位置形成突出端，从而导致沟槽喉部和空隙形成的逐渐限制。

20. 发明申请

US20090130814A1 SEMICONDUCTOR METHODS 有权
标题翻译：半导体方法
公开(公告)号：US20090130814A1
公开(公告)日：2009-05-21
申请号：US12357661
申请日：2009-01-22
申请人： Yuan-Hung LIU , Ming Chyi Liu , Yeur-Luen Tu , Chi-Hsin Lo , Chai-Shiung Tsai
发明人： Yuan-Hung LIU , Ming Chyi Liu , Yeur-Luen Tu , Chi-Hsin Lo , Chai-Shiung Tsai
IPC分类号： H01L21/20
CPC分类号： H01L21/02274 , H01L21/02115 , H01L21/28273 , H01L21/3086 , H01L21/31116 , H01L21/31144 , H01L21/3146 , H01L21/76816 , H01L21/7682 , H01L21/76885 , H01L21/76897 , H01L27/115 , H01L27/11521 , H01L27/14632 , H01L27/14687 , H01L28/91 , H01L29/42328 , H01L29/7881
摘要： A method includes forming an amorphous carbon layer over a first dielectric layer formed over a substrate, forming a second dielectric layer over the amorphous carbon layer; and forming an opening within the amorphous carbon layer and second dielectric layer by a first etch process to partially expose a top surface of the first dielectric layer. A substantially conformal metal-containing layer is formed over the second dielectric layer and within the opening. The second dielectric layer and a portion of the metal-containing layer are removed. The amorphous carbon layer is removed by an oxygen-containing plasma process to expose a top surface of the first dielectric layer. An insulating layer is formed over the metal-containing layer, and a second metal-containing layer is formed over the insulating layer to form a capacitor.
摘要翻译：一种方法包括在形成在衬底上的第一电介质层上形成无定形碳层，在非晶碳层上形成第二电介质层; 以及通过第一蚀刻工艺在所述非晶碳层和所述第二介电层内形成开口，以部分地暴露所述第一介电层的顶表面。在第二电介质层上并在开口内形成基本上共形的含金属层。去除第二电介质层和一部分含金属层。通过含氧等离子体工艺除去无定形碳层以暴露第一介电层的顶表面。在含金属层的上方形成有绝缘层，在绝缘层上形成第二含金属层，形成电容器。

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