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    • 16. 发明授权
    • Testing circuit and testing method for semiconductor device and semiconductor chip
    • 半导体器件和半导体芯片的测试电路和测试方法
    • US07603248B2
    • 2009-10-13
    • US11474393
    • 2006-06-26
    • Hidetoshi SugiyamaMasao NakajimaHaruyuki MouriHideaki Suzuki
    • Hidetoshi SugiyamaMasao NakajimaHaruyuki MouriHideaki Suzuki
    • G06F19/00
    • G01R31/31719G01R31/31701G01R31/31721
    • A testing circuit for a semiconductor device having a test mode in which the information about built-in memory cannot be read after conducting a test on a semiconductor device, and cutting a pad formed in a scribe area is provided. The scribe PAD and the scribe ROM are formed in the cutting area of a wafer. Upon power-up of a chip a, the power-on reset circuit transmits a reset signal to the mode register. After setting the initial resister value to “00”, a mode switch signal is input from the mode switch terminal, the scribe ROM is activated, and the test mode is set. In this process, a Manchester coded signal is provided from the scribe PAD, decoded by a clock of dividing frequency provided from the clock dividing circuit, the value of the register in the test mode in the mode register is set, and external reset is asserted or negated.
    • 一种半导体器件的测试电路,具有测试模式,其中在对半导体器件进行测试之后无法读取关于内置存储器的信息,并且切割形成在划线区域中的焊盘。 划片PAD和划线ROM形成在晶片的切割区域中。 在芯片a上电时,上电复位电路将复位信号发送到模式寄存器。 将初始电阻值设置为“00”后,从模式开关端子输入模式切换信号,激活划线ROM,并设置测试模式。 在这个过程中,曼彻斯特编码信号由划片PAD提供,由时钟分频电路提供的分频时钟解码,设置模式寄存器中的测试模式中的寄存器的值,并且断言外部复位 或否定。
    • 17. 发明授权
    • Semiconductor memory device which reduces the consumption current at the time of operation
    • 半导体存储器件,其减少了操作时的消耗电流
    • US06894943B2
    • 2005-05-17
    • US10341455
    • 2003-01-14
    • Hideaki SuzukiMasao Nakajima
    • Hideaki SuzukiMasao Nakajima
    • G11C11/22G11C7/06G11C7/18G11C8/12G11C8/00
    • G11C7/06G11C7/18G11C8/12G11C2207/065
    • A semiconductor memory device includes a memory bank which is divided into a plurality of memory blocks including a first memory block and a second memory block. A first sense amplifier control unit activates sense amplifiers connected with the first memory block, in response to a first activation signal. A second sense amplifier control unit activates sense amplifiers connected with the second memory block, in response to a second activation signal. A signal control unit outputs the first activation signal and the second activation signal to the first sense amplifier control unit and the second sense amplifier control unit, separately from each other, the signal control unit outputting the second activation signal to the second sense amplifier control unit by delaying the first activation signal by a predetermined time after the outputting of the first activation signal.
    • 半导体存储器件包括存储体,其被分成包括第一存储块和第二存储块的多个存储块。 响应于第一激活信号,第一读出放大器控制单元启动与第一存储器块连接的读出放大器。 响应于第二激活信号,第二读出放大器控制单元激活与第二存储器块连接的读出放大器。 信号控制单元将第一激活信号和第二激活信号彼此分离地输出到第一读出放大器控制单元和第二读出放大器控制单元,信号控制单元将第二激活信号输出到第二读出放大器控制单元 通过在第一激活信号的输出之后的预定时间延迟第一激活信号。
    • 19. 发明授权
    • Failsafe for an engine control
    • 发动机控制失效
    • US4491112A
    • 1985-01-01
    • US339155
    • 1982-01-13
    • Hidetoshi KanegaeMasaharu AsanoSeishi YasuharaMasao Nakajima
    • Hidetoshi KanegaeMasaharu AsanoSeishi YasuharaMasao Nakajima
    • F02B1/04F02D17/04F02D41/22F02D41/38F02B3/00F02D1/04F02D11/10
    • F02D41/38F02D17/04F02D41/221F02B1/04F02D2041/226F02D2200/703F02D41/408
    • A failsafe system for an engine-control servomotor compares a servomotor command signal to a feedback signal from the servomotor. When the magnitude of the difference between the two signals is greater than a predetermined value for a predetermined time, the failsafe system shuts down the servomotor or performs some other engine shut-down procedure. The failsafe system includes a comparator for comparing the two signals, the output of which leads to two other op-amp-type comparators connected in parallel, which work on negative or positive outputs of the first-mentioned comparator, respectively. Each of the later comparators receives a reference voltage input against which to compare the output of the first-mentioned comparator. Their outputs lead parallelly to time-delay circuits which check for a positive output for a predetermined length of time by a well-known capacitor-integration technique.
    • 用于发动机控制伺服电动机的故障保护系统将伺服电机命令信号与来自伺服电动机的反馈信号进行比较。 当两个信号之间的差值的大小在预定时间内大于预定值时,故障安全系统关闭伺服电动机或执行一些其它发动机停机程序。 故障保护系统包括比较器,用于比较两个信号,其输出端分别连接两个并联的运算放大器类型的比较器,它们分别用于前述比较器的负或正输出。 后面的比较器中的每一个接收一个参考电压输入,用于比较第一个提及的比较器的输出。 它们的输出并行引导到时间延迟电路,该电路通过公知的电容器集成技术来检查预定时间长度的正输出。
    • 20. 发明申请
    • Testing circuit and testing method for semiconductor device and semiconductor chip
    • 半导体器件和半导体芯片的测试电路和测试方法
    • US20070203662A1
    • 2007-08-30
    • US11474393
    • 2006-06-26
    • Hidetoshi SugiyamaMasao NakajimaHaruyuki MouriHideaki Suzuki
    • Hidetoshi SugiyamaMasao NakajimaHaruyuki MouriHideaki Suzuki
    • G06F19/00
    • G01R31/31719G01R31/31701G01R31/31721
    • A testing circuit for a semiconductor device having a test mode in which the information about built-in memory cannot be read after conducting a test on a semiconductor device, and cutting a pad formed in a scribe area is provided. The scribe PAD and the scribe ROM are formed in the cutting area of a wafer. Upon power-up of a chip a, the power-on reset circuit transmits a reset signal to the mode register. After setting the initial resister value to “00”, a mode switch signal is input from the mode switch terminal, the scribe ROM is activated, and the test mode is set. In this process, a Manchester coded signal is provided from the scribe PAD, decoded by a clock of dividing frequency provided from the clock dividing circuit, the value of the register in the test mode in the mode register is set, and external reset is asserted or negated.
    • 一种半导体器件的测试电路,具有测试模式,其中在对半导体器件进行测试之后无法读取关于内置存储器的信息,并且切割形成在划线区域中的焊盘。 划片PAD和划线ROM形成在晶片的切割区域中。 在芯片a上电时,上电复位电路将复位信号发送到模式寄存器。 将初始电阻值设置为“00”后,从模式开关端子输入模式切换信号,激活划线ROM,并设置测试模式。 在这个过程中,曼彻斯特编码信号由划片PAD提供,由时钟分频电路提供的分频时钟解码,设置模式寄存器中的测试模式中的寄存器的值,并且断言外部复位 或否定。