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11. 发明授权

US06509763B2 Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权
公开(公告)号：US06509763B2
公开(公告)日：2003-01-21
申请号：US10162565
申请日：2002-06-06
申请人： Masao Taguchi , Hiroyoshi Tomita , Yasurou Matsuzaki , Miki Yanagawa
发明人： Masao Taguchi , Hiroyoshi Tomita , Yasurou Matsuzaki , Miki Yanagawa
IPC分类号： G01R1900
CPC分类号： H03L7/0805 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/135 , H03K5/151 , H03K2005/00234 , H03L7/0814
摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

12. 发明授权

US06272069B1 LSI device with memory and logics mounted thereon 有权
公开(公告)号：US06272069B1
公开(公告)日：2001-08-07
申请号：US09764446
申请日：2001-01-19
申请人： Hiroyoshi Tomita , Yasurou Matsuzaki , Masao Taguchi
发明人： Hiroyoshi Tomita , Yasurou Matsuzaki , Masao Taguchi
IPC分类号： G11C800
摘要： A data signal is output from an output circuit of a first chip and sent to a data input terminal in the second chip via a data lead line based on an output clock in first chip, which is sent to the second chip. And an input circuit in a second chip receives the data signal and transfers it inside in response to a transfer clock that has been generated from the output clock in the first chip. In synchronism with a single reference clock in the first chip, therefore, a data signal can be transferred to the second chip from the first chip at a high speed.

13. 发明授权

US6063640A Semiconductor wafer testing method with probe pin contact 失效
标题翻译：半导体晶圆测试方法与探针接触
公开(公告)号：US6063640A
公开(公告)日：2000-05-16
申请号：US30349
申请日：1998-02-25
申请人： Masataka Mizukoshi , Hidehiko Akasaki , Masao Nakano , Yasuhiro Fujii , Shinnosuke Kamata , Makoto Yanagisawa , Yasurou Matsuzaki , Toyonobu Yamada , Masami Matsuoka , Hiroyoshi Tomita
发明人： Masataka Mizukoshi , Hidehiko Akasaki , Masao Nakano , Yasuhiro Fujii , Shinnosuke Kamata , Makoto Yanagisawa , Yasurou Matsuzaki , Toyonobu Yamada , Masami Matsuoka , Hiroyoshi Tomita
IPC分类号： H01L23/58 , G01R31/26 , H01L21/66
CPC分类号： H01L22/32 , H01L22/22 , H01L2224/05554 , Y10S438/977
摘要： A semiconductor wafer testing method includes a pre-test step for forming a temporary test film on a surface of a semiconductor wafer, a test step for testing the semiconductor wafer by applying a probe to the temporary test film and a post-test step for exfoliating the temporary test film from the surface of the semiconductor wafer. The temporary test film includes test electrode groups each provided with a plurality of regularly arranged test electrodes, and wiring patterns for electrically connecting the test electrodes with corresponding ones of semiconductor unit electrodes in respective semiconductor units on the semiconductor wafer. Probe pins of said probe are arranged so as to be aligned with corresponding ones of the test electrodes of the respective test electrode groups.
摘要翻译：半导体晶片测试方法包括：在半导体晶片的表面上形成临时测试膜的预测试步骤，通过向临时测试膜施加探针来测试半导体晶片的测试步骤和用于去角质的后测试步骤来自半导体晶片表面的临时测试膜。临时测试膜包括各自设置有多个规则排列的测试电极的测试电极组和用于将测试电极与半导体晶片上的各个半导体单元中的相应半导体单元电极电连接的布线图案。所述探针的探头针布置成与各个测试电极组的相应测试电极对齐。

14. 发明授权

US06907555B1 Self-test circuit and memory device incorporating it 有权
标题翻译：自检电路和结合其的存储器件
公开(公告)号：US06907555B1
公开(公告)日：2005-06-14
申请号：US09691115
申请日：2000-10-19
申请人： Yukihiro Nomura , Hiroyuki Fujimoto , Takahiro Suzuki , Tatsuya Kanda , Yasurou Matsuzaki , Masahiko Saitou , Hiroyoshi Tomita
发明人： Yukihiro Nomura , Hiroyuki Fujimoto , Takahiro Suzuki , Tatsuya Kanda , Yasurou Matsuzaki , Masahiko Saitou , Hiroyoshi Tomita
IPC分类号： G01R31/28 , G01R31/3185 , G06F12/16 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/06 , G11C29/12 , G11C29/44
CPC分类号： G11C29/44
摘要： The present invention is a self-test circuit (BIST) incorporated in the memory device, which is activated in response to a test activation signal from outside. When this self-test circuit is activated in response to a test activation signal (WBIZ) from outside, it generates a test operation command (WBI-CMD), generates a test address (WBI-ADD), and generates test data (WBI-DATA). Furthermore, after the self-test circuit writes the test data to a memory cell, it effects a comparison to establish whether or not the read data that is read from this memory cell is the same as the test data that was written thereto and stores information as to the result of this comparison. This comparison result information is then output to the outside.
摘要翻译：本发明是一种结合在存储器件中的自检电路（BIST），其响应于来自外部的测试激活信号被激活。当该自检电路响应于来自外部的测试激活信号（WBIZ）被激活时，它产生测试操作命令（WBI-CMD），生成测试地址（WBI-ADD），并生成测试数据（WBI- 数据）。此外，在自检电路将测试数据写入存储单元之后，进行比较以确定从该存储单元读取的读取数据是否与写入的测试数据相同并存储信息关于这个比较的结果。然后将该比较结果信息输出到外部。

15. 发明授权

US06198689B1 Integrated circuit device with built-in self timing control circuit 有权
标题翻译：具有内置自定时控制电路的集成电路器件
公开(公告)号：US06198689B1
公开(公告)日：2001-03-06
申请号：US09440667
申请日：1999-11-16
申请人： Masafumi Yamazaki , Hiroyoshi Tomita , Yasurou Matsuzaki
发明人： Masafumi Yamazaki , Hiroyoshi Tomita , Yasurou Matsuzaki
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C7/1072 , G11C7/22
摘要： The present invention is an integrated circuit device having a self timing control circuit for generating an input loading timing signal whose phase is adjusted with an external clock, where loading of input signals supplied from outside, such as a command input signal, address input signal and data input signal, to internal circuits is forbidden when the self timing control circuit is adjusting phase. And when the self timing control circuit finishes adjusting the phase to a certain degree, the loading operation of an input signal at the input circuit using the input loading timing signal is enabled. To execute such an operation, the input circuit generates an input loading control signal based on a lock-on signal or adjustment signal of the DLL circuit, or based on an input stop cancellation signal, for example. The input circuit controls the stop and restart of loading of the input signal according to this input loading control signal.
摘要翻译：本发明是一种具有自定时控制电路的集成电路装置，该自定时控制电路用于产生输入负载定时信号，该输入负载定时信号的相位是用外部时钟调整的，其中从外部输入的输入信号如命令输入信号，地址输入信号和数据输入信号，当自定时控制电路正在调整相位时，禁止内部电路。并且当自定时控制电路在一定程度上完成相位调整时，可以使用输入负载定时信号在输入电路处的输入信号的加载操作。为了执行这种操作，输入电路基于例如DLL电路的锁定信号或调整信号，或者基于输入停止消除信号，生成输入负载控制信号。输入电路根据该输入负载控制信号控制输入信号的停止和重新启动。

16. 发明授权

US06181174B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06181174B2
公开(公告)日：2001-01-30
申请号：US09404221
申请日：1999-09-23
申请人： Waichirou Fujieda , Yasuharu Sato , Nobutaka Taniguchi , Hiroyoshi Tomita , Yasurou Matsuzaki
发明人： Waichirou Fujieda , Yasuharu Sato , Nobutaka Taniguchi , Hiroyoshi Tomita , Yasurou Matsuzaki
IPC分类号： H03L706
CPC分类号： H03L7/0805 , G06F1/08 , G06F1/10 , G11C7/1039 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , H03K5/133 , H03K23/58 , H03L7/0814
摘要： A semiconductor integrated circuit device includes a DLL circuit. The DLL circuit includes a frequency divider which frequency-divides an input clock at a frequency dividing ratio which is varied depending on a frequency of the input clock and thus results in a dummy clock and a reference clock. A delay system includes a variable delay circuit which delays the dummy clock. A control circuit controls a delay amount of the variable delay circuit so that a phase of a delayed dummy clock from the delay system and the reference clock becomes zero.
摘要翻译：半导体集成电路装置包括DLL电路。 DLL电路包括分频器，该分频器以分频比对输入时钟进行分频，该分频比根据输入时钟的频率而变化，从而产生虚拟时钟和参考时钟。延迟系统包括延迟虚拟时钟的可变延迟电路。控制电路控制可变延迟电路的延迟量，使得来自延迟系统和参考时钟的延迟的虚拟时钟的相位变为零。

17. 发明授权

US6108793A Semiconductor device having timing-stabilization circuit and method of testing such semiconductor device 失效
标题翻译：具有时序稳定电路的半导体器件和测试这种半导体器件的方法
公开(公告)号：US6108793A
公开(公告)日：2000-08-22
申请号：US40288
申请日：1998-03-18
申请人： Yasuhiro Fujii , Hiroyoshi Tomita , Nobutaka Taniguchi , Yasurou Matsuzaki
发明人： Yasuhiro Fujii , Hiroyoshi Tomita , Nobutaka Taniguchi , Yasurou Matsuzaki
IPC分类号： G01R31/30 , G06F1/04 , H03L7/081 , H03L7/087 , H03L7/095
CPC分类号： H03L7/0805 , G01R31/3016 , G06F1/04 , H03L7/0814 , H03L7/087 , H03L7/095
摘要： A method of measuring a time which a timing-stabilization circuit requires in order to complete timing stabilization with regard to a semiconductor device provided with a first function to reset the timing-stabilization circuit and a second function to output a signal indicative of completion of the timing stabilization is disclosed. The method includes the steps of a) activating the timing-stabilization circuit, b) detecting a timing of the completion of the timing stabilization by using the second function, and c) measuring the time which the timing-stabilization circuit requires to complete the timing stabilization based on the timing.
摘要翻译：一种测量定时稳定电路所需的时间的方法，以便对具有第一功能的半导体器件完成定时稳定以复位定时稳定电路，以及第二功能，以输出指示完成的信号公开了定时稳定。该方法包括以下步骤：a）激活定时稳定电路，b）通过使用第二功能来检测定时稳定的定时，以及c）测量定时稳定电路完成定时所需的时间基于时间稳定。

18. 发明授权

US6075393A Clock synchronous semiconductor device system and semiconductor devices used with the same 失效
标题翻译：时钟同步半导体器件系统和使用的半导体器件
公开(公告)号：US6075393A
公开(公告)日：2000-06-13
申请号：US998478
申请日：1997-12-29
申请人： Hiroyoshi Tomita , Yoshihiro Takemae
发明人： Hiroyoshi Tomita , Yoshihiro Takemae
IPC分类号： G11C11/413 , G06F1/10 , G06F12/00 , G11C7/00 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , H03K5/135 , H03L7/081 , H03L7/00
CPC分类号： G11C7/222 , G11C7/1078 , G11C7/22 , H03L7/0812
摘要： A clock synchronous semiconductor device system and semiconductor devices used with the system have the read and write operations performed at a proper timing without increasing the types of clock or the amount of wiring. The system includes a plurality of semiconductor devices operated in synchronism with a clock. One of the semiconductor devices operates as a controller for producing a signal related to the controlling of the remaining semiconductor devices. A clock signal line for transmitting a clock to each semiconductor device is arranged in parallel with the other signal lines. A clock source is arranged at a position far from the controller not to cause any skew when the read data arrive at the controller from the remaining semiconductor devices. The timing at which each memory retrieves the write data from the controller is adjusted by an input timing adjusting circuit included in each memory, thereby permitting each memory to retrieve the write data at an optimum timing.
摘要翻译：与系统一起使用的时钟同步半导体器件系统和半导体器件具有在适当的定时执行的读和写操作，而不增加时钟的类型或布线的数量。该系统包括与时钟同步操作的多个半导体器件。其中一个半导体器件用作用于产生与其余半导体器件的控制有关的信号的控制器。用于将时钟发送到每个半导体器件的时钟信号线与其他信号线并联布置。当远离控制器的位置处的时钟源被布置在读取数据从其余半导体器件到达控制器时不会产生任何偏斜。通过每个存储器中包括的输入定时调整电路调整每个存储器从控制器检索写数据的定时，从而允许每个存储器在最佳定时检索写数据。

19. 发明授权

US5896347A Semiconductor memory system using a clock-synchronous semiconductor device and semiconductor memory device for use in the same 失效
标题翻译：使用时钟同步半导体器件的半导体存储器系统和用于其的半导体存储器件
公开(公告)号：US5896347A
公开(公告)日：1999-04-20
申请号：US925458
申请日：1997-09-08
申请人： Hiroyoshi Tomita , Yoshihiro Takemae
发明人： Hiroyoshi Tomita , Yoshihiro Takemae
IPC分类号： G11C11/413 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/409 , H03L7/00 , G11C8/00
CPC分类号： G11C7/1093 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222
摘要： A semiconductor memory system using a synchronous memory and operating at a higher speed due to a reduced margin required when reading data from the SDRAM, and a semiconductor memory device for achieving the same are disclosed. The semiconductor memory system comprises at least one semiconductor memory device and a control device for performing data input/output to and from the semiconductor memory device, wherein the control device outputs data to be stored in the semiconductor memory device, synchronously with a first synchronizing signal that the control device outputs, and the semiconductor memory device delivers output data therefrom synchronously with a second synchronizing signal that the semiconductor memory device outputs. In the thus constructed semiconductor memory system, the semiconductor memory device incorporates an output phase shift circuit which introduces a prescribed phase angle between the output data and second synchronizing signal, and provisions are made so that at the semiconductor memory device side the output data and the second synchronizing signal are controlled precisely at the prescribed phase angle with respect to each other, and so that a latch pulse can be immediately generated at the controller side upon reception of a data strobe signal.
摘要翻译：公开了一种使用同步存储器并且由于在从SDRAM读取数据时所需的余量减小而以更高速度工作的半导体存储器系统，以及用于实现其的半导体存储器件。半导体存储器系统包括至少一个半导体存储器件和用于对半导体存储器件进行数据输入/输出的控制器件，其中控制器件与第一同步信号同步地输出要存储在半导体存储器件中的数据控制装置输出，半导体存储装置与半导体存储装置输出的第二同步信号同步地输出输出数据。在这样构成的半导体存储器系统中，半导体存储器件包括在输出数据和第二同步信号之间引入规定相位角的输出移相电路，并且在半导体存储器件侧进行输出数据和第二同步信号相对于彼此精确地以规定的相位角被控制，并且使得在接收数据选通信号时可以在控制器侧立即产生锁存脉冲。

20. 发明授权

US5901101A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5901101A
公开(公告)日：1999-05-04
申请号：US919505
申请日：1997-08-28
申请人： Takaaki Suzuki , Masao Nakano , Hiroyoshi Tomita , Yasuharu Sato , Kotoku Sato , Nobutaka Taniguchi
发明人： Takaaki Suzuki , Masao Nakano , Hiroyoshi Tomita , Yasuharu Sato , Kotoku Sato , Nobutaka Taniguchi
IPC分类号： G11C11/403 , G11C11/406 , G11C11/407 , G11C7/00
CPC分类号： G11C11/406
摘要： In a semiconductor memory device operable in synchronism with a clock signal externally supplied thereto, there are provided a first part which detects a state of a predetermined signal after a given command is input to the semiconductor memory; and a second part which sets, on the basis of the state of the predetermined signal, the semiconductor memory device to a self-refresh mode in which a refresh operation is carried out without an external signal.
摘要翻译：在与外部提供给其的时钟信号同步操作的半导体存储器件中，提供了第一部分，其在将给定命令输入到半导体存储器之后检测预定信号的状态; 以及第二部分，其基于预定信号的状态将半导体存储器件设置为在没有外部信号的情况下执行刷新操作的自刷新模式。

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