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11. 发明申请

US20100321069A1 AC-COUPLED INTERFACE CIRCUIT 有权
标题翻译：交流耦合接口电路
公开(公告)号：US20100321069A1
公开(公告)日：2010-12-23
申请号：US12526227
申请日：2007-07-23
申请人： Yoshihide Komatsu , Tsuyoshi Ebuchi , Satoshi Hori , Takashi Hirata , Junji Nakatsuka
发明人： Yoshihide Komatsu , Tsuyoshi Ebuchi , Satoshi Hori , Takashi Hirata , Junji Nakatsuka
IPC分类号： H03K3/00
CPC分类号： H04L25/0266 , H04L25/0272
摘要： A differential driver (101) includes a pair of output terminals connected to a pair of signal lines (102A and 102B), wherein in a data transmission operation, the differential driver (101) converts transmit data (TXD) to a differential signal to output the differential signal. A differential receiver includes a pair of input terminals connected to the pair of signal lines (102A and 102B), wherein in a data reception operation, the differential receiver receives a differential signal transferred to the pair of signal lines and converts the differential signal to receive data (RXD). A potential setting section (106) sets a potential of the pair of signal lines to a predetermined stable potential before the differential signal is transferred to the pair of signal lines (102A and 102B).
摘要翻译：差分驱动器（101）包括连接到一对信号线（102A和102B）的一对输出端子，其中在数据传输操作中，差分驱动器（101）将发送数据（TXD）转换为差分信号以输出差分信号。差分接收器包括连接到该对信号线（102A和102B）的一对输入端，其中在数据接收操作中，差分接收器接收传送到该对信号线的差分信号，并将差分信号转换成接收数据（RXD）。电位设定部（106）将差分信号传送到信号线对（102A，102B）之前，将一对信号线的电位设定为规定的稳定电位。

12. 发明申请

US20100127739A1 SPREAD SPECTRUM CONTROL PLL CIRCUIT AND ITS START-UP METHOD 有权
标题翻译：传播频谱控制PLL电路及其启动方法
公开(公告)号：US20100127739A1
公开(公告)日：2010-05-27
申请号：US12595008
申请日：2008-03-18
申请人： Tsuyoshi Ebuchi , Yoshihide Komatsu , Michiyo Yamamoto
发明人： Tsuyoshi Ebuchi , Yoshihide Komatsu , Michiyo Yamamoto
IPC分类号： H03L7/08
CPC分类号： H03L7/197 , H03L7/0898 , H03L7/093 , H03L7/0995 , H03L7/1976
摘要： A calibration circuit (19) adjusts at least one of one of a charging current of a charge pump circuit (12) and a capacitance value of a filter capacitor in a loop filter circuit (13) and a gain of a voltage controlled oscillator (14), depending on a frequency of a reference clock signal input to a calibration circuit (10).
摘要翻译：校准电路（19）调整环路滤波器电路（13）中的电荷泵电路（12）的充电电流和滤波电容器的电容值中的至少一个以及压控振荡器（14）的增益中的至少一个），取决于输入到校准电路（10）的参考时钟信号的频率。

13. 发明授权

US07007212B2 Transmission device, reception device, test circuit, and test method 失效
标题翻译：传输设备，接收设备，测试电路和测试方法
公开(公告)号：US07007212B2
公开(公告)日：2006-02-28
申请号：US10387132
申请日：2003-03-13
申请人： Yoshihide Komatsu , Toru Iwata
发明人： Yoshihide Komatsu , Toru Iwata
IPC分类号： G01R31/28
CPC分类号： G01R31/31716
摘要： The present invention provides a transmission device, a reception device, a test circuit and a test method, which enable internal parts of the circuit to operate at high speed, while performing inputting/outputting to/from a tester at low speed. The test circuit comprises a PLL 111 which divides the frequency of a test clock input from the tester to generate a PLL clock CKp1, a FIFO 113 which stores input data input from the tester on the test clock and outputs the data on the PLL clock CKp1, an encoder 114 which distributes bits of the input data, a driver 115 which transmits the output signal from the encoder 114 to the outside, a PLL 121 which divides the frequency of the test clock to generate a PLL clock CKp2, a decoder 124 which arranges the bits of the signal received by a receiver 123.
摘要翻译：本发明提供了一种在低速地进行/从测试仪输入/输出的同时使得电路的内部部分能够高速运行的发送装置，接收装置，测试电路和测试方法。测试电路包括一个PLL 111，它分频输入测试时钟的频率，产生一个PLL时钟CKp 1，一个FIFO 113，它将测试时输入的输入数据存储在测试时钟上，并输出PLL时钟上的数据 CKp 1，分配输入数据的位的编码器114，将来自编码器114的输出信号发送到外部的驱动器115，分频测试时钟的频率以产生PLL时钟CKp 2的PLL 121; 解码器124，其布置由接收器123接收的信号的位。

14. 发明授权

US08665872B2 Transmission apparatus and transmission method 失效
标题翻译：传输装置及传输方式
公开(公告)号：US08665872B2
公开(公告)日：2014-03-04
申请号：US13064469
申请日：2011-03-28
申请人： Yoshihide Komatsu
发明人： Yoshihide Komatsu
IPC分类号： H04L12/28
CPC分类号： H04L12/42 , H04L12/4641
摘要： When a packet received from a ring network is addressed to a device on a local network established under a transmission apparatus, then that transmission apparatus detects whether a memory device installed therein is in the memory full state. If the memory device is determined to be in the memory full state, then the transmission apparatus sends the packet, which was received from the ring network, back to the ring network. Subsequently, when the memory device recovers from the memory full state, the transmission apparatus sends the packet to the specified device in the local network.
摘要翻译：当从环形网络接收的分组被寻址到在传输设备下建立的本地网络上的设备时，该传输设备检测其中安装的存储设备是否处于存储器满状态。如果确定存储器件处于存储器满状态，则发送装置将从环形网络接收到的数据包发回环网。随后，当存储器装置从存储器完全状态恢复时，发送装置将分组发送到本地网络中的指定装置。

15. 发明授权

US07020817B2 Method for testing semiconductor chips and semiconductor device 失效
公开(公告)号：US07020817B2
公开(公告)日：2006-03-28
申请号：US10159024
申请日：2002-06-03
申请人： Yoshihide Komatsu
发明人： Yoshihide Komatsu
IPC分类号： G01R31/28
CPC分类号： G01R31/31922 , G01R31/31937
摘要： The delay characteristic of a chip under test on which a function test is performed first is detected by performing an edge search for stabilizing the test without awaiting the delay characteristic to be stabilized and the result of detection is stored in a memory. By using the delay characteristic stored in the memory, the function test is performed repeatedly on the chip under test till NG (FAIL) occurs. When NG occurs, the function test is performed repeatedly till the NG count of the chip under test reaches a first specified number. If the NG count exceeds the first specified number, the foregoing process is repeated starting from the edge search. If the NG count reaches a second specified number, the chip under test is determined to be defective and the test is ended.

16. 发明申请

US20050201375A1 Uninterrupted transfer method in IP network in the event of line failure 审中-公开
标题翻译：发生线路故障时IP网络中不间断的传输方式
公开(公告)号：US20050201375A1
公开(公告)日：2005-09-15
申请号：US11122381
申请日：2005-05-05
申请人： Yoshihide Komatsu , Hirofumi Yagawa , Kazuya Ryu , Kazuaki Yoshida , Toshinobu Tsunematsu
发明人： Yoshihide Komatsu , Hirofumi Yagawa , Kazuya Ryu , Kazuaki Yoshida , Toshinobu Tsunematsu
IPC分类号： H04L12/28
CPC分类号： H04L43/50 , H04L1/0045 , H04L1/1893 , H04L41/0677 , H04L2001/0096
摘要： An uninterruptible transfer can be realized during a line failure in a transmission system performing a packet transmission between transmitting apparatuses connected via a plurality of lines. In a method for realizing the uninterruptible transfer, test packets including information of the number of packets received from the transmitting apparatus of a destination are periodically sent to the transmitting apparatus of a source. The transmitting apparatus of the source compares the received information of the number of packets included in the received test packets with the number of packets sent out to the transmitting apparatus of the destination via one line. When the comparison shows a disagreement between the number of the received packets and the number of the sent-out packets, packets corresponding to the disagreement are resent to the transmitting apparatus of the destination via another line. The packets, before being sent out to the transmitting apparatus of the destination, are stored in a buffer memory. When the comparison shows an agreement between the number of the received packets and the number of the sent-out packets, packets, which are stored in the buffer memory, corresponding to the agreement are released from the buffer memory.
摘要翻译：在通过多条线路连接的发送装置之间执行分组传输的传输系统的线路故障期间，可以实现不间断传送。在实现不间断传送的方法中，周期性地向源的发送装置发送包括从目的地的发送装置接收的分组数量的信息的测试分组。源的发送装置将接收到的测试分组中包含的分组数量的接收信息与经由一行发送到目的地的发送装置的分组的数量进行比较。当比较表示接收到的分组数与发送分组的数量之间存在分歧时，对应于不一致的分组通过另一行重新发送到目的地的发送装置。在发送到目的地的发送装置之前，分组被存储在缓冲存储器中。当比较表示接收到的数据包的数量和发送数据包的数量之间的一致性时，从缓冲存储器释放对应于协议的存储在缓冲存储器中的数据包。

17. 发明授权

US06262568B1 Common mode bias generator 有权
标题翻译：共模偏置发生器
公开(公告)号：US06262568B1
公开(公告)日：2001-07-17
申请号：US09734191
申请日：2000-12-12
申请人： Yoshihide Komatsu , Hironori Akamatsu , Takashi Hirata , Satoshi Takahashi , Yutaka Terada
发明人： Yoshihide Komatsu , Hironori Akamatsu , Takashi Hirata , Satoshi Takahashi , Yutaka Terada
IPC分类号： G05F304
CPC分类号： G05F3/205
摘要： An inventive potential generator generates a predetermined potential and includes first operational amplifier, current supply circuit and current sink circuit. A first reference potential is applied to the non-inverting input terminal of the first amplifier and a potential at the output node of the first amplifier is not only applied to the inverting input terminal of the first amplifier but also used as the output of the generator. The current supply circuit supplies a current to the output node of the first amplifier if the potential at the output node of the first amplifier is lower than a predefined level. And the current sink circuit drains a current from the output node of the first amplifier if the potential at the output node of the first amplifier is higher than the predefined level.
摘要翻译：本发明的潜在发生器产生预定电位并且包括第一运算放大器，电流供应电路和电流吸收电路。第一参考电位被施加到第一放大器的非反相输入端，并且第一放大器的输出节点处的电位不仅被施加到第一放大器的反相输入端，而且还用作发生器的输出。如果第一放大器的输出节点处的电位低于预定义电平，则电流供应电路向第一放大器的输出节点提供电流。并且如果第一放大器的输出节点处的电位高于预定义电平，则电流吸收电路从第一放大器的输出节点漏出电流。

18. 发明授权

US08548069B2 Data transmission system capable of transmitting interrupt signal without interrupt gate period 有权
标题翻译：数据传输系统能够在不中断门限周期的情况下传输中断信号
公开(公告)号：US08548069B2
公开(公告)日：2013-10-01
申请号：US13142655
申请日：2010-10-13
申请人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito , Kohei Masuda , Yoshihide Komatsu , Masashi Suzuki
发明人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito , Kohei Masuda , Yoshihide Komatsu , Masashi Suzuki
IPC分类号： H04B3/00
CPC分类号： H04L25/0278
摘要： A data transmission system comprises: a pair of transmission lines connecting a plurality of apparatuses; a bridge termination resistor connected between the transmission lines and having a resistance value matching a differential impedance of the transmission lines; a first switch connecting the bridge termination resistor to the transmission lines when being turned on, and disconnecting the bridge termination resistor from the transmission lines when being turned off; pull-up/down resistors connected between the transmission lines and a fixed voltage node, and having resistance values respectively matching characteristic impedances of the transmission lines, the fixed voltage node being a power supply or a ground; and second switches connecting the pull-up/down resistors between the transmission lines and the fixed voltage node when being turned on, and disconnecting the pull-up/down resistors from the transmission lines when being turned off.
摘要翻译：数据传输系统包括：一对连接多个设备的传输线; 连接在传输线之间并具有与传输线的差分阻抗匹配的电阻值的桥接终端电阻; 第一开关，其在接通时将桥接端接电阻器连接到传输线;以及当断开时将桥接终端电阻器与传输线路断开; 连接在传输线路和固定电压节点之间的上拉/下拉电阻器，具有分别匹配传输线路的特征阻抗，固定电压节点为电源或接地的电阻值; 以及第二开关，其在接通时将传输线和固定电压节点之间的上拉/下拉电阻连接起来，以及在断开时从传输线断开上拉/下拉电阻。

19. 发明授权

US08265195B2 Hybrid data transmission circuit 有权
标题翻译：混合数据传输电路
公开(公告)号：US08265195B2
公开(公告)日：2012-09-11
申请号：US13242962
申请日：2011-09-23
申请人： Tsuyoshi Ebuchi , Yoshihide Komatsu
发明人： Tsuyoshi Ebuchi , Yoshihide Komatsu
IPC分类号： H04L27/00 , H03D3/24
CPC分类号： H04L25/028 , H03K3/0322 , H03K5/15093 , H03L7/081 , H03L7/0995 , H03L2207/06 , H03M9/00 , H04L7/0337 , H04L25/0272
摘要： A data transmitter having a parallel-to-serial conversion function is supplied with a clock by a PLL circuit unit. In the PLL circuit unit, a first multiphase clock supplied to a first parallel-to-serial conversion circuit is generated and output by a multiphase VCO circuit, while a second multiphase clock supplied to a second parallel-to-serial conversion circuit is generated and output by a multiphase clock generator. The multiphase clock generator generates the second multiphase clock based on the clock output from the multiphase VCO circuit.
摘要翻译：具有并行到串行转换功能的数据发射机由PLL电路单元提供时钟。在PLL电路单元中，提供给第一并行转换电路的第一多相时钟由多相VCO电路产生并输出，同时产生提供给第二并行 - 串行转换电路的第二多相时钟，由多相时钟发生器输出。多相时钟发生器基于来自多相VCO电路的时钟输出产生第二多相时钟。

20. 发明申请

US20110280322A1 DATA TRANSMISSION SYSTEM CAPABLE OF TRANSMITTING INTERRUPT SIGNAL WITHOUT INTERRUPT GATE PERIOD 有权
标题翻译：无中断门限发送中断信号的数据传输系统
公开(公告)号：US20110280322A1
公开(公告)日：2011-11-17
申请号：US13142655
申请日：2010-10-13
申请人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito , Kohei Masuda , Yoshihide Komatsu , Masashi Suzuki
发明人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito , Kohei Masuda , Yoshihide Komatsu , Masashi Suzuki
IPC分类号： H04B3/00
CPC分类号： H04L25/0278
摘要： A data transmission system comprises: a pair of transmission lines connecting a plurality of apparatuses; a bridge termination resistor connected between the transmission lines and having a resistance value matching a differential impedance of the transmission lines; a first switch connecting the bridge termination resistor to the transmission lines when being turned on, and disconnecting the bridge termination resistor from the transmission lines when being turned off; pull-up/down resistors connected between the transmission lines and a fixed voltage node, and having resistance values respectively matching characteristic impedances of the transmission lines, the fixed voltage node being a power supply or a ground; and second switches connecting the pull-up/down resistors between the transmission lines and the fixed voltage node when being turned on, and disconnecting the pull-up/down resistors from the transmission lines when being turned off.
摘要翻译：数据传输系统包括：一对连接多个设备的传输线; 连接在传输线之间并具有与传输线的差分阻抗匹配的电阻值的桥接终端电阻; 第一开关，其在接通时将桥接端接电阻器连接到传输线;以及当断开时将桥接终端电阻器与传输线路断开; 连接在传输线路和固定电压节点之间的上拉/下拉电阻器，具有分别匹配传输线路的特征阻抗，固定电压节点为电源或接地的电阻值; 以及第二开关，其在接通时将传输线和固定电压节点之间的上拉/下拉电阻连接起来，以及在断开时从传输线断开上拉/下拉电阻。

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