专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20120280307A1 INTEGRATING SCHOTTKY DIODE INTO POWER MOSFET 有权
标题翻译：将肖特基二极管集成到功率MOSFET中
公开(公告)号：US20120280307A1
公开(公告)日：2012-11-08
申请号：US13098852
申请日：2011-05-02
申请人： Yi Su , Daniel Ng , Anup Bhalla , Hong Chang , Jongoh Kim , John Chen
发明人： Yi Su , Daniel Ng , Anup Bhalla , Hong Chang , Jongoh Kim , John Chen
IPC分类号： H01L27/06 , H01L21/336
CPC分类号： H01L29/7801 , H01L21/26586 , H01L29/0623 , H01L29/0696 , H01L29/0891 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/4238 , H01L29/47 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/78 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/782 , H01L29/872
摘要： A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.
摘要翻译：半导体器件包括多个沟槽，包括有源区域中的有源栅极沟槽和栅极流道/终止沟槽以及在有源区域外部的终止区域中的屏蔽电极拾取沟槽。栅极流道/终止沟槽包括限定位于有源区域之外的台面的一个或多个沟槽。在多个沟槽中形成第一导电区域。在限定台面的沟槽中形成中间介质区域和端接保护区域。在限定台面的沟槽部分中形成第二导电区域。第二导电区域通过中间介电区域与第一导电区域电隔离。对第二导电区域进行第一电接触，并且在屏蔽电极拾取沟槽中对第一导电区域进行第二电接触。在台面内形成一个或多个肖特基二极管。

12. 发明申请

US20120248530A1 APPROACH TO INTERGRATE SCHOTTKY IN MOSFET 有权
标题翻译：将肖特考虑在MOSFET中的方法
公开(公告)号：US20120248530A1
公开(公告)日：2012-10-04
申请号：US13079675
申请日：2011-04-04
申请人： Sik Lui , Yi Su , Daniel Ng , Anup Bhalla
发明人： Sik Lui , Yi Su , Daniel Ng , Anup Bhalla
IPC分类号： H01L29/78 , H01L29/872 , H01L21/8234
CPC分类号： H01L29/7806 , H01L27/0629 , H01L29/0619 , H01L29/0623 , H01L29/1095 , H01L29/41766 , H01L29/66734 , H01L29/7813 , H01L29/872 , H01L29/8725
摘要： An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions.
摘要翻译：集成结构结合了场效应晶体管和肖特基二极管。形成衬底组合物的沟槽沿其中形成台面的衬底组合物的深度延伸。每个沟槽填充有导电材料，该导电材料通过形成栅极区域的电介质材料与沟槽壁分离。每个台面形状内部的两个第一导电类型体区部分地沉积到基底组合物的深度中。衬底组合物的暴露部分分离身体区域。每个身体区域内的第二导电类型源区域与每个孔的相邻侧和相邻侧相邻。每个孔内的肖特基势垒金属在分离体区的基底组合物的暴露部分的暴露的垂直侧壁的界面处形成肖特基结。

13. 发明申请

US20120007206A1 Structures and methods for forming schottky diodes on a p-substrate or a bottom anode schottky diode 审中-公开
标题翻译：在p型衬底或底部阳极肖特基二极管上形成肖特基二极管的结构和方法
公开(公告)号：US20120007206A1
公开(公告)日：2012-01-12
申请号：US13199264
申请日：2011-08-23
申请人： Anup Bhalla , Sik K. Lui , Yi Su
发明人： Anup Bhalla , Sik K. Lui , Yi Su
IPC分类号： H01L29/47 , H01L21/329
CPC分类号： H01L29/872 , H01L29/0649 , H01L29/861
摘要： This invention discloses bottom-anode Schottky (BAS) device supported on a semiconductor substrate having a bottom surface functioning as an anode electrode with an epitaxial layer has a same doped conductivity as said anode electrode overlying the anode electrode. The BAS device further includes an Schottky contact metal disposed in a plurality of trenches and covering a top surface of the semiconductor substrate between the trenches. The BAS device further includes a plurality of doped JBS regions disposed on sidewalls and below a bottom surface of the trenches doped with an opposite conductivity type from the anode electrode constituting a junction barrier Schottky (JBS) with the epitaxial layer disposed between the plurality of doped JBS regions. The BAS device further includes an ultra-shallow Shannon implant layer disposed immediate below the Schottky contact metal in the epitaxial layer between the plurality of doped JBS regions.
摘要翻译：本发明公开了一种支撑在具有作为具有外延层的阳极电极的底面的半导体衬底上的底阳极肖特基（BAS）器件具有与覆盖在阳极电极上的所述阳极电极相同的掺杂电导率。 BAS装置还包括设置在多个沟槽中并且在沟槽之间覆盖半导体衬底的顶表面的肖特基接触金属。 BAS器件还包括多个掺杂的JBS区域，其布置在沟槽的底表面的下表面上，掺杂有来自构成结屏障肖特基（JBS）的阳极电极的相反导电类型，其外延层设置在多个掺杂的 JBS地区。 BAS装置还包括在多个掺杂的JBS区域之间的外延层中立即设置在肖特基接触金属下方的超浅香农注入层。

14. 发明授权

US08053808B2 Layouts for multiple-stage ESD protection circuits for integrating with semiconductor power device 有权
标题翻译：用于与半导体功率器件集成的多级ESD保护电路布局
公开(公告)号：US08053808B2
公开(公告)日：2011-11-08
申请号：US11804906
申请日：2007-05-21
申请人： Yi Su , Anup Bhalla , Daniel Ng , Wei Wang , Ji Pan
发明人： Yi Su , Anup Bhalla , Daniel Ng , Wei Wang , Ji Pan
IPC分类号： H01L29/66
CPC分类号： H01L29/7811 , H01L27/0255 , H01L29/0696 , H01L29/66734 , H01L29/7808 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate includes a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a source metal connected to the source region, and a gate metal configured as a metal stripe surrounding a peripheral region of the substrate connected to a gate pad wherein the gate metal and the gate pad are separated from the source metal by a metal gap. The semiconductor power device further includes an ESD protection circuit includes a plurality of doped polysilicon regions of opposite conductivity types constituting ESD diodes extending across the metal gap and connected between the gate metal and the source metal on the peripheral region of the substrate.
摘要翻译：支撑在半导体衬底上的半导体功率器件包括多个晶体管单元，每个晶体管单元具有源极和漏极，栅极用于控制在源极和漏极之间传输的电流。半导体还包括连接到源极区的源极金属和栅极金属，该栅极金属被配置为围绕连接到栅极焊盘的衬底的外围区域的金属条，其中栅极金属和栅极焊盘与源极金属分离金属间隙。半导体功率器件还包括ESD保护电路，其包括构成ESD保护二极管的相反导电类型的多个掺杂多晶硅区域，该ESD二极管延伸穿过金属间隙并连接在栅极金属与源极金属之间。

15. 发明申请

US20110151628A1 Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection 有权
标题翻译：门极漏极（GD）钳位和ESD保护电路的配置用于电源器件击穿保护
公开(公告)号：US20110151628A1
公开(公告)日：2011-06-23
申请号：US12932584
申请日：2011-02-28
申请人： Yi Su , Anup Bhalla , Daniel Ng
发明人： Yi Su , Anup Bhalla , Daniel Ng
IPC分类号： H01L21/822
CPC分类号： H01L29/7813 , H01L27/0255 , H01L27/0629 , H01L29/0615 , H01L29/0638 , H01L29/0646 , H01L29/0692 , H01L29/0696 , H01L29/66734 , H01L29/7803 , H01L29/7804 , H01L29/7808 , H01L29/7811 , H01L29/7815 , H01L29/8611 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped well disposed below and engulfing the U-shaped bend.
摘要翻译：一种半导体功率器件，其被支撑在半导体衬底上，该半导体衬底包括多个晶体管单元，每个晶体管单元具有源极和漏极，栅极用于控制在源极和漏极之间传输的电流。半导体还包括在栅极和漏极之间串联连接的栅极 - 漏极（GD）钳位端接器，还包括串联连接到硅二极管的多个背对背多晶硅二极管，包括半导体中的并行掺杂的列衬底，其中平行掺杂的柱具有预定的间隙。掺杂的柱还包括U形弯曲柱，其将平行掺杂的柱的端部连接在一起，深度掺杂的阱设置在U形弯曲部下方并吞噬U形弯曲部。

16. 发明申请

US20100153315A1 BOOSTING ALGORITHM FOR RANKING MODEL ADAPTATION 有权
标题翻译：用于排序模型适应的增强算法
公开(公告)号：US20100153315A1
公开(公告)日：2010-06-17
申请号：US12337623
申请日：2008-12-17
申请人： Jianfeng Gao , Yi Su , Qiang Wu , Chris J.C. Burges , Krysta Svore , Elbio Renato Torres Abib
发明人： Jianfeng Gao , Yi Su , Qiang Wu , Chris J.C. Burges , Krysta Svore , Elbio Renato Torres Abib
IPC分类号： G06F15/18 , G06F17/30
CPC分类号： G06F17/3053
摘要： Model adaptation may be performed to take a general model trained with a set of training data (possibly large), and adapt the model using a set of domain-specific training data (possibly small). The parameters, structure, or configuration of a model trained in one domain (called the background domain) may be adapted to a different domain (called the adaptation domain), for which there may be a limited amount of training data. The adaption may be performed using the Boosting Algorithm to select an optimal basis function that optimizes a measure of error of the model as it is being iteratively refined, i.e., adapted.
摘要翻译：可以执行模型适配以采用用一组训练数据（可能较大）训练的通用模型，并且使用一组特定领域的训练数据（可能小）来适配模型。在一个域（称为背景域）中训练的模型的参数，结构或配置可以适应于可能存在有限量的训练数据的不同域（称为适配域）。可以使用升压算法来执行自适应，以选择最优基函数，该优化基函数优化模型的误差量度，因为其被迭代地改进，即适应。

17. 发明授权

US08829603B2 Shielded gate trench MOSFET package 有权
标题翻译：屏蔽栅沟MOSFET封装
公开(公告)号：US08829603B2
公开(公告)日：2014-09-09
申请号：US13212940
申请日：2011-08-18
申请人： Sik Lui , Yi Su , Daniel Ng , Daniel Calafut , Anup Bhalla
发明人： Sik Lui , Yi Su , Daniel Ng , Daniel Calafut , Anup Bhalla
IPC分类号： H01L29/66 , H01L23/64 , H01L29/78 , H01L29/40 , H01L29/423 , H01L23/00
CPC分类号： H01L29/7813 , H01L23/647 , H01L24/06 , H01L24/48 , H01L24/49 , H01L29/407 , H01L29/42368 , H01L29/4238 , H01L29/66734 , H01L29/7803 , H01L29/7811 , H01L2224/0603 , H01L2224/4813 , H01L2224/48247 , H01L2224/4911 , H01L2224/49111 , H01L2924/00014 , H01L2924/10253 , H01L2924/12032 , H01L2924/13091 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A shielded gate trench field effect transistor can be formed on a substrate having an epitaxial layer on the substrate and a body layer on the epitaxial layer. A trench formed in the body layer and epitaxial layer is lined with a dielectric layer. A shield electrode is formed within a lower portion of the trench. The shield electrode is insulated by the dielectric layer. A gate electrode is formed in the trench above the shield electrode and insulated from the shield electrode by an additional dielectric layer. One or more source regions formed within the body layer is adjacent a sidewall of the trench. A source pad formed above the body layer is electrically connected to the one or more source regions and insulated from the gate electrode and shield electrode. The source pad provides an external contact to the source region. A gate pad provides an external contact to the gate electrode. A shield electrode pad provides an external contact to the shield electrode. A resistive element can be electrically connected between the shield electrode pad and the source lead in the package.
摘要翻译：可以在衬底上具有外延层的衬底上形成屏蔽栅沟槽场效应晶体管，并在外延层上形成体层。形成在体层和外延层中的沟槽衬有介电层。屏蔽电极形成在沟槽的下部内。屏蔽电极由电介质层绝缘。栅极电极形成在屏蔽电极上方的沟槽中，并通过附加的介电层与屏蔽电极绝缘。形成在体层内的一个或多个源极区域与沟槽的侧壁相邻。形成在主体层上方的源极焊盘与一个或多个源极区域电连接并与栅电极和屏蔽电极绝缘。源极焊盘提供与源极区域的外部接触。栅极焊盘提供与栅电极的外部接触。屏蔽电极焊盘提供与屏蔽电极的外部接触。电阻元件可以电连接在封装中的屏蔽电极焊盘和源极引线之间。

18. 发明授权

US08802509B2 Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection 有权
标题翻译：门极漏极（GD）钳位和ESD保护电路的配置用于电源器件击穿保护
公开(公告)号：US08802509B2
公开(公告)日：2014-08-12
申请号：US12932584
申请日：2011-02-28
申请人： Yi Su , Anup Bhalla , Daniel Ng
发明人： Yi Su , Anup Bhalla , Daniel Ng
IPC分类号： H01L21/822
CPC分类号： H01L29/7813 , H01L27/0255 , H01L27/0629 , H01L29/0615 , H01L29/0638 , H01L29/0646 , H01L29/0692 , H01L29/0696 , H01L29/66734 , H01L29/7803 , H01L29/7804 , H01L29/7808 , H01L29/7811 , H01L29/7815 , H01L29/8611 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped well disposed below and engulfing the U-shaped bend.
摘要翻译：一种半导体功率器件，其被支撑在半导体衬底上，该半导体衬底包括多个晶体管单元，每个晶体管单元具有源极和漏极，栅极用于控制在源极和漏极之间传输的电流。半导体还包括在栅极和漏极之间串联连接的栅极 - 漏极（GD）钳位端接器，还包括串联连接到硅二极管的多个背对背多晶硅二极管，包括半导体中的并行掺杂的列衬底，其中平行掺杂的柱具有预定的间隙。掺杂的柱还包括U形弯曲柱，其将平行掺杂的柱的端部连接在一起，深度掺杂的阱设置在U形弯曲部下方并吞噬U形弯曲部。

19. 发明授权

US08764448B2 Robotic device for use in image-guided robot assisted surgical training 有权
标题翻译：用于图像引导机器人辅助外科手术的机器人装置
公开(公告)号：US08764448B2
公开(公告)日：2014-07-01
申请号：US13820065
申请日：2011-09-01
申请人： Tao Yang , Liangjing Yang , Jiang Liu , Chee Kong Chui , Weimin Huang , Jing Zhang , Jiayin Zhou , Beng Hai Lee , Ngan Meng Tan , Wing Kee Damon Wong , Fengshou Yin , Kin Yong Chang , Yi Su
发明人： Tao Yang , Liangjing Yang , Jiang Liu , Chee Kong Chui , Weimin Huang , Jing Zhang , Jiayin Zhou , Beng Hai Lee , Ngan Meng Tan , Wing Kee Damon Wong , Fengshou Yin , Kin Yong Chang , Yi Su
IPC分类号： G09B23/28 , A61B17/00 , G06G7/58 , A61B19/00
CPC分类号： G09B23/28 , A61B34/30 , B25J3/04 , B25J7/00 , G09B23/285
摘要： A robotic device for use in image-guided robot assisted surgical training, the robotic device comprising a manual interface structure configured to simulate handling of a surgical tool; a translational mechanism for translational motion of the manual interface structure; a rotational mechanism for rotational motion of the manual interface structure; and a spherical mechanism configured to decouple the orientation of the manual interface structure into spatial coordinates, wherein a linkage between the rotational mechanism, the rotational mechanism and the spherical mechanism, and the manual interface structure are disposed on opposing sides of an intersection of a pitch axis and a yaw axis of the spherical mechanism.
摘要翻译：一种用于图像引导机器人辅助外科手术训练的机器人装置，所述机器人装置包括被配置为模拟外科手术工具的处理的手动界面结构; 手动界面结构的平移运动的平移机制; 用于手动接口结构的旋转运动的旋转机构; 以及球面机构，被配置为将手动界面结构的取向分离成空间坐标，其中旋转机构，旋转机构和球面机构之间的联动以及手动界面结构设置在俯仰的交叉点的相对侧上轴和球面机构的偏转轴。

20. 发明授权

US08502302B2 Integrating Schottky diode into power MOSFET 有权
标题翻译：将肖特基二极管集成到功率MOSFET中
公开(公告)号：US08502302B2
公开(公告)日：2013-08-06
申请号：US13098852
申请日：2011-05-02
申请人： Yi Su , Daniel Ng , Anup Bhalla , Hong Chang , Jongoh Kim , John Chen
发明人： Yi Su , Daniel Ng , Anup Bhalla , Hong Chang , Jongoh Kim , John Chen
IPC分类号： H01L27/06 , H01L21/336
CPC分类号： H01L29/7801 , H01L21/26586 , H01L29/0623 , H01L29/0696 , H01L29/0891 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/4238 , H01L29/47 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/78 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/782 , H01L29/872
摘要： A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.
摘要翻译：半导体器件包括多个沟槽，包括有源区域中的有源栅极沟槽和栅极流道/终止沟槽以及在有源区域外部的终止区域中的屏蔽电极拾取沟槽。栅极流道/终止沟槽包括限定位于有源区域之外的台面的一个或多个沟槽。在多个沟槽中形成第一导电区域。在限定台面的沟槽中形成中间介质区域和端接保护区域。在限定台面的沟槽部分中形成第二导电区域。第二导电区域通过中间介电区域与第一导电区域电隔离。对第二导电区域进行第一电接触，并且在屏蔽电极拾取沟槽中对第一导电区域进行第二电接触。在台面内形成一个或多个肖特基二极管。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式