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1. 发明申请

US20130043527A1 SHIELDED GATE TRENCH MOSFET PACKAGE 有权
标题翻译：屏蔽栅极晶体管封装
公开(公告)号：US20130043527A1
公开(公告)日：2013-02-21
申请号：US13212940
申请日：2011-08-18
申请人： SIK LUI , Yi Su , Daniel Ng , Daniel Calafut , Anup Bhalla
发明人： SIK LUI , Yi Su , Daniel Ng , Daniel Calafut , Anup Bhalla
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L23/647 , H01L24/06 , H01L24/48 , H01L24/49 , H01L29/407 , H01L29/42368 , H01L29/4238 , H01L29/66734 , H01L29/7803 , H01L29/7811 , H01L2224/0603 , H01L2224/4813 , H01L2224/48247 , H01L2224/4911 , H01L2224/49111 , H01L2924/00014 , H01L2924/10253 , H01L2924/12032 , H01L2924/13091 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A shielded gate trench field effect transistor can be formed on a substrate having an epitaxial layer on the substrate and a body layer on the epitaxial layer. A trench formed in the body layer and epitaxial layer is lined with a dielectric layer. A shield electrode is formed within a lower portion of the trench. The shield electrode is insulated by the dielectric layer. A gate electrode is formed in the trench above the shield electrode and insulated from the shield electrode by an additional dielectric layer. One or more source regions formed within the body layer is adjacent a sidewall of the trench. A source pad formed above the body layer is electrically connected to the one or more source regions and insulated from the gate electrode and shield electrode. The source pad provides an external contact to the source region. A gate pad provides an external contact to the gate electrode. A shield electrode pad provides an external contact to the shield electrode. A resistive element can be electrically connected between the shield electrode pad and the source lead in the package.
摘要翻译：可以在衬底上具有外延层的衬底上形成屏蔽栅沟槽场效应晶体管，并在外延层上形成体层。形成在体层和外延层中的沟槽衬有介电层。屏蔽电极形成在沟槽的下部内。屏蔽电极由电介质层绝缘。栅极电极形成在屏蔽电极上方的沟槽中，并通过附加的介电层与屏蔽电极绝缘。形成在体层内的一个或多个源极区域与沟槽的侧壁相邻。形成在主体层上方的源极焊盘与一个或多个源极区域电连接并与栅电极和屏蔽电极绝缘。源极焊盘提供与源极区域的外部接触。栅极焊盘提供与栅电极的外部接触。屏蔽电极焊盘提供与屏蔽电极的外部接触。电阻元件可以电连接在封装中的屏蔽电极焊盘和源极引线之间。

2. 发明授权

US08829603B2 Shielded gate trench MOSFET package 有权
标题翻译：屏蔽栅沟MOSFET封装
公开(公告)号：US08829603B2
公开(公告)日：2014-09-09
申请号：US13212940
申请日：2011-08-18
申请人： Sik Lui , Yi Su , Daniel Ng , Daniel Calafut , Anup Bhalla
发明人： Sik Lui , Yi Su , Daniel Ng , Daniel Calafut , Anup Bhalla
IPC分类号： H01L29/66 , H01L23/64 , H01L29/78 , H01L29/40 , H01L29/423 , H01L23/00
CPC分类号： H01L29/7813 , H01L23/647 , H01L24/06 , H01L24/48 , H01L24/49 , H01L29/407 , H01L29/42368 , H01L29/4238 , H01L29/66734 , H01L29/7803 , H01L29/7811 , H01L2224/0603 , H01L2224/4813 , H01L2224/48247 , H01L2224/4911 , H01L2224/49111 , H01L2924/00014 , H01L2924/10253 , H01L2924/12032 , H01L2924/13091 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A shielded gate trench field effect transistor can be formed on a substrate having an epitaxial layer on the substrate and a body layer on the epitaxial layer. A trench formed in the body layer and epitaxial layer is lined with a dielectric layer. A shield electrode is formed within a lower portion of the trench. The shield electrode is insulated by the dielectric layer. A gate electrode is formed in the trench above the shield electrode and insulated from the shield electrode by an additional dielectric layer. One or more source regions formed within the body layer is adjacent a sidewall of the trench. A source pad formed above the body layer is electrically connected to the one or more source regions and insulated from the gate electrode and shield electrode. The source pad provides an external contact to the source region. A gate pad provides an external contact to the gate electrode. A shield electrode pad provides an external contact to the shield electrode. A resistive element can be electrically connected between the shield electrode pad and the source lead in the package.
摘要翻译：可以在衬底上具有外延层的衬底上形成屏蔽栅沟槽场效应晶体管，并在外延层上形成体层。形成在体层和外延层中的沟槽衬有介电层。屏蔽电极形成在沟槽的下部内。屏蔽电极由电介质层绝缘。栅极电极形成在屏蔽电极上方的沟槽中，并通过附加的介电层与屏蔽电极绝缘。形成在体层内的一个或多个源极区域与沟槽的侧壁相邻。形成在主体层上方的源极焊盘与一个或多个源极区域电连接并与栅电极和屏蔽电极绝缘。源极焊盘提供与源极区域的外部接触。栅极焊盘提供与栅电极的外部接触。屏蔽电极焊盘提供与屏蔽电极的外部接触。电阻元件可以电连接在封装中的屏蔽电极焊盘和源极引线之间。

3. 发明申请

US20140151790A1 APPROACH TO INTEGRATE SCHOTTKY IN MOSFET 有权
标题翻译：在MOSFET中整合肖特基的方法
公开(公告)号：US20140151790A1
公开(公告)日：2014-06-05
申请号：US13873017
申请日：2013-04-29
申请人： Sik Lui , Yi Su , Daniel Ng , Anup Bhalla
发明人： Sik Lui , Yi Su , Daniel Ng , Anup Bhalla
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7806 , H01L27/0629 , H01L29/0619 , H01L29/0623 , H01L29/1095 , H01L29/41766 , H01L29/66734 , H01L29/7813 , H01L29/872 , H01L29/8725
摘要： An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions.
摘要翻译：集成结构结合了场效应晶体管和肖特基二极管。形成衬底组合物的沟槽沿其中形成台面的衬底组合物的深度延伸。每个沟槽填充有导电材料，该导电材料通过形成栅极区域的电介质材料与沟槽壁分离。每个台面形状内部的两个第一导电类型体区部分地沉积到基底组合物的深度中。衬底组合物的暴露部分分离身体区域。每个身体区域内的第二导电类型源区域与每个孔的相邻侧和相邻侧相邻。每个孔内的肖特基势垒金属在分离体区的基底组合物的暴露部分的暴露的垂直侧壁的界面处形成肖特基结。

4. 发明授权

US08431470B2 Approach to integrate Schottky in MOSFET 有权
标题翻译：将肖特基集成在MOSFET中的方法
公开(公告)号：US08431470B2
公开(公告)日：2013-04-30
申请号：US13079675
申请日：2011-04-04
申请人： Sik Lui , Yi Su , Daniel Ng , Anup Bhalla
发明人： Sik Lui , Yi Su , Daniel Ng , Anup Bhalla
IPC分类号： H01L21/28 , H01L21/02
CPC分类号： H01L29/7806 , H01L27/0629 , H01L29/0619 , H01L29/0623 , H01L29/1095 , H01L29/41766 , H01L29/66734 , H01L29/7813 , H01L29/872 , H01L29/8725
摘要： An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions.
摘要翻译：集成结构结合了场效应晶体管和肖特基二极管。形成衬底组合物的沟槽沿其中形成台面的衬底组合物的深度延伸。每个沟槽填充有导电材料，该导电材料通过形成栅极区域的电介质材料与沟槽壁分离。每个台面形状内部的两个第一导电类型体区部分地沉积到基底组合物的深度中。衬底组合物的暴露部分分离身体区域。每个身体区域内的第二导电类型源区域与每个孔的相邻侧和相邻侧相邻。每个孔内的肖特基势垒金属在分离体区的基底组合物的暴露部分的暴露的垂直侧壁的界面处形成肖特基结。

5. 发明申请

US20120248530A1 APPROACH TO INTERGRATE SCHOTTKY IN MOSFET 有权
标题翻译：将肖特考虑在MOSFET中的方法
公开(公告)号：US20120248530A1
公开(公告)日：2012-10-04
申请号：US13079675
申请日：2011-04-04
申请人： Sik Lui , Yi Su , Daniel Ng , Anup Bhalla
发明人： Sik Lui , Yi Su , Daniel Ng , Anup Bhalla
IPC分类号： H01L29/78 , H01L29/872 , H01L21/8234
CPC分类号： H01L29/7806 , H01L27/0629 , H01L29/0619 , H01L29/0623 , H01L29/1095 , H01L29/41766 , H01L29/66734 , H01L29/7813 , H01L29/872 , H01L29/8725
摘要： An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions.
摘要翻译：集成结构结合了场效应晶体管和肖特基二极管。形成衬底组合物的沟槽沿其中形成台面的衬底组合物的深度延伸。每个沟槽填充有导电材料，该导电材料通过形成栅极区域的电介质材料与沟槽壁分离。每个台面形状内部的两个第一导电类型体区部分地沉积到基底组合物的深度中。衬底组合物的暴露部分分离身体区域。每个身体区域内的第二导电类型源区域与每个孔的相邻侧和相邻侧相邻。每个孔内的肖特基势垒金属在分离体区的基底组合物的暴露部分的暴露的垂直侧壁的界面处形成肖特基结。

6. 发明授权

US08759908B2 Two-dimensional shielded gate transistor device and method of manufacture 有权
标题翻译：二维屏蔽晶体管器件及其制造方法
公开(公告)号：US08759908B2
公开(公告)日：2014-06-24
申请号：US13286733
申请日：2011-11-01
申请人： Sik Lui , Anup Bhalla , Daniel Ng
发明人： Sik Lui , Anup Bhalla , Daniel Ng
IPC分类号： H01L29/78
CPC分类号： H01L29/4238 , H01L29/407 , H01L29/4236 , H01L29/66734 , H01L29/7813
摘要： A shielded gate transistor device may include one or more shield electrodes formed in a semiconductor substrate at a first level and one or more gate electrodes formed in the semiconductor substrate at a second level that is different from the first level. One or more portions of the one or more gate electrodes overlap one or more portions of the one or more shield electrodes. At least a portion of the gate electrodes is oriented non-parallel to the one or more shield electrodes. The shield electrodes are electrically insulated from the semiconductor substrate and the one or more gate electrodes are electrically insulated from the substrate and shield electrodes.
摘要翻译：屏蔽栅晶体管器件可以包括形成在第一电平的半导体衬底中的一个或多个屏蔽电极和形成在与第一电平不同的第二电平的半导体衬底中的一个或多个栅电极。一个或多个栅电极的一个或多个部分重叠一个或多个屏蔽电极的一个或多个部分。栅电极的至少一部分取向为不平行于一个或多个屏蔽电极。屏蔽电极与半导体衬底电绝缘，并且一个或多个栅电极与衬底和屏蔽电极电绝缘。

7. 发明申请

US20060202264A1 Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout 有权
标题翻译：增强肖特基击穿电压（BV），而不影响集成MOSFET肖特基器件布局
公开(公告)号：US20060202264A1
公开(公告)日：2006-09-14
申请号：US11413249
申请日：2006-04-29
申请人： Anup Bhalla , Daniel Ng , Sik Lui
发明人： Anup Bhalla , Daniel Ng , Sik Lui
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0615 , H01L29/0619 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/872
摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells and a junction barrier Schottky (JBS) area. The semiconductor power device includes the JBS area that further includes a plurality of Schottky diodes each having a PN junction disposed on an epitaxial layer near a top surface of a semiconductor substrate wherein the PN junction further includes a counter dopant region disposed in the epitaxial layer for reducing a sudden reversal of dopant profile near the PN junction for preventing an early breakdown in the PN junction.
摘要翻译：本发明公开了一种半导体功率器件，其包括具有多个功率晶体管单元和接合势垒肖特基（JBS）区域的有源单元区域。半导体功率器件包括JBS区域，其还包括多个肖特基二极管，每个肖特基二极管各自具有设置在半导体衬底的顶表面附近的外延层上的PN结，其中PN结还包括设置在外延层中的反掺杂剂区域减少PN结附近的掺杂剂分布的突然反转，以防止PN结中的早期击穿。

8. 发明申请

US20130105886A1 TWO-DIMENSIONAL SHIELDED GATE TRANSISTOR DEVICE AND METHOD OF MANUFACTURE 有权
标题翻译：二维屏蔽栅极晶体管器件及其制造方法
公开(公告)号：US20130105886A1
公开(公告)日：2013-05-02
申请号：US13286733
申请日：2011-11-01
申请人： SIK LUI , Anup Bhalla , Daniel Ng
发明人： SIK LUI , Anup Bhalla , Daniel Ng
IPC分类号： H01L29/78
CPC分类号： H01L29/4238 , H01L29/407 , H01L29/4236 , H01L29/66734 , H01L29/7813
摘要： A shielded gate transistor device may include one or more shield electrodes formed in a semiconductor substrate at a first level and one or more gate electrodes formed in the semiconductor substrate at a second level that is different from the first level. One or more portions of the one or more gate electrodes overlap one or more portions of the one or more shield electrodes. At least a portion of the gate electrodes is oriented non-parallel to the one or more shield electrodes. The shield electrodes are electrically insulated from the semiconductor substrate and the one or more gate electrodes are electrically insulated from the substrate and shield electrodes.
摘要翻译：屏蔽栅晶体管器件可以包括形成在第一电平的半导体衬底中的一个或多个屏蔽电极和形成在与第一电平不同的第二电平的半导体衬底中的一个或多个栅电极。一个或多个栅电极的一个或多个部分重叠一个或多个屏蔽电极的一个或多个部分。栅电极的至少一部分取向为不平行于一个或多个屏蔽电极。屏蔽电极与半导体衬底电绝缘，并且一个或多个栅电极与衬底和屏蔽电极电绝缘。

9. 发明申请

US20060249785A1 Power MOSFET device structure for high frequency applications 有权
标题翻译：功率MOSFET器件结构用于高频应用
公开(公告)号：US20060249785A1
公开(公告)日：2006-11-09
申请号：US11125506
申请日：2005-05-09
申请人： Anup Bhalla , Daniel Ng , Tiesheng Li , Sik Lui
发明人： Anup Bhalla , Daniel Ng , Tiesheng Li , Sik Lui
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66712 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41775 , H01L29/42368 , H01L29/42372 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/7802 , H01L29/7811 , H01L29/7827
摘要： This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.
摘要翻译：本发明公开了一种支撑在半导体上的新开关装置，其包括设置在第一表面上的漏极和设置在与第一表面相对的所述半导体的第二表面附近的源极区域。开关装置还包括设置在第二表面顶部的用于控制源极到漏极电流的绝缘栅电极。开关装置还包括插入到绝缘栅电极中的源电极，用于基本上防止栅电极和绝缘栅电极下方的外延区之间的电场的耦合。源电极进一步覆盖并延伸在绝缘栅上，以覆盖半导体的第二表面上的区域以接触源区。半导体衬底还包括设置在漏极区以上且具有与漏极区不同的掺杂浓度的外延层。绝缘栅电极还包括用于使栅电极与源电极绝缘的绝缘层，其中绝缘层的厚度取决于垂直功率器件的Vgsmax等级。

10. 发明授权

US07952144B2 Integration of a sense FET into a discrete power MOSFET 有权
标题翻译：将感测FET集成到分立功率MOSFET中
公开(公告)号：US07952144B2
公开(公告)日：2011-05-31
申请号：US12860777
申请日：2010-08-20
申请人： Yi Su , Anup Bhalla , Daniel Ng
发明人： Yi Su , Anup Bhalla , Daniel Ng
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L21/8234 , H01L27/088 , H01L29/0646 , H01L29/0653 , H01L29/0696 , H01L29/66734 , H01L29/7815 , H01L2224/0603 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs, and a common gate pad. The main FET and the one or more sense FETs are formed in a common substrate. The main FET and each of the sense FETs include a source terminal, a gate terminal and a drain terminal. The common gate pad connects the gate terminals of the main FET and the one or more sense FETs. An electrical isolation is disposed between the gate terminals of the main FET and the one or more sense FETs. Embodiments of this invention may be applied to both N-channel and P-channel MOSFET devices.
摘要翻译：半导体器件包括主场效应晶体管（FET）和一个或多个感测FET以及公共栅极焊盘。主FET和一个或多个感测FET形成在公共衬底中。主FET和每个感测FET包括源极端子，栅极端子和漏极端子。公共栅极焊盘连接主FET和一个或多个感测FET的栅极端子。在主FET和一个或多个感测FET的栅极端子之间设置电隔离。本发明的实施例可以应用于N沟道和P沟道MOSFET器件。

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