专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20130309868A1 METHODS FOR FORMING AN INTEGRATED CIRCUIT WITH STRAIGHTENED RECESS PROFILE 有权
标题翻译：用于形成具有连续记录轮廓的集成电路的方法
公开(公告)号：US20130309868A1
公开(公告)日：2013-11-21
申请号：US13476860
申请日：2012-05-21
申请人： Xiuyu Cai , Xunyuan Zhang , Ruilong Xie , Errol T. Ryan , John A. Iacoponi
发明人： Xiuyu Cai , Xunyuan Zhang , Ruilong Xie , Errol T. Ryan , John A. Iacoponi
IPC分类号： H01L21/311
CPC分类号： H01L21/311 , H01L21/3105 , H01L21/31116 , H01L21/76801 , H01L21/76816 , H01L21/76828 , H01L21/76831 , H01L29/66545
摘要： Methods are provided for forming an integrated circuit. In an embodiment, the method includes forming a sacrificial mandrel overlying a base substrate. Sidewall spacers are formed adjacent sidewalls of the sacrificial mandrel. The sidewall spacers have a lower portion that is proximal to the base substrate, and the lower portion has a substantially perpendicular outer surface relative to the base substrate. The sidewall spacers also have an upper portion that is spaced from the base substrate. The upper portion has a sloped outer surface. A first dielectric layer is formed overlying the base substrate and is conformal to at least a portion of the upper portion of the sidewall spacers. The upper portion of the sidewall spacers is removed after forming the first dielectric layer to form a recess having a re-entrant profile in the first dielectric layer. The re-entrant profile of the recess is straightened.
摘要翻译：为形成集成电路提供了方法。在一个实施例中，该方法包括形成覆盖在基底衬底上的牺牲心轴。侧壁间隔件形成在牺牲心轴的相邻侧壁处。侧壁间隔件具有靠近基底基底的下部，并且下部具有相对于基底的基本垂直的外表面。侧壁间隔物还具有与基底基板间隔开的上部。上部具有倾斜的外表面。第一电介质层形成在基底衬底上，并且与侧壁间隔物的上部的至少一部分共形。在形成第一介电层之后去除侧壁间隔物的上部，以在第一介电层中形成具有凹入轮廓的凹部。凹槽的重新设计简洁直观。

12. 发明授权

US08936979B2 Semiconductor devices having improved gate height uniformity and methods for fabricating same 有权
标题翻译：具有改善的栅极高度均匀性的半导体器件及其制造方法
公开(公告)号：US08936979B2
公开(公告)日：2015-01-20
申请号：US13493865
申请日：2012-06-11
申请人： Ruilong Xie , Xiuyu Cai , Andy C. Wei , Robert Miller
发明人： Ruilong Xie , Xiuyu Cai , Andy C. Wei , Robert Miller
IPC分类号： H01L21/00
CPC分类号： H01L29/6653 , H01L21/823828 , H01L21/823864 , H01L29/66545 , H01L29/6656 , H01L29/78
摘要： Semiconductor devices and methods for fabricating semiconductor devices are provided. In an embodiment, a method for fabricating a semiconductor device includes forming on a semiconductor surface a temporary gate structure including a polysilicon gate and a cap. A spacer is formed around the temporary gate structure. The cap and a portion of the spacer are removed. A uniform liner is deposited overlying the polysilicon gate. The method removes a portion of the uniform liner overlying the polysilicon gate and the polysilicon gate to form a gate trench. Then, a replacement metal gate is formed in the gate trench.
摘要翻译：提供了用于制造半导体器件的半导体器件和方法。在一个实施例中，制造半导体器件的方法包括在半导体表面上形成包括多晶硅栅极和帽的临时栅极结构。在临时栅极结构周围形成间隔物。盖子和间隔件的一部分被去除。均匀的衬垫沉积在多晶硅栅极上。该方法去除覆盖多晶硅栅极和多晶硅栅极的均匀衬底的一部分以形成栅极沟槽。然后，在栅极沟槽中形成替换金属栅极。

13. 发明授权

US08748309B2 Integrated circuits with improved gate uniformity and methods for fabricating same 有权
标题翻译：具有改善的栅极均匀性的集成电路及其制造方法
公开(公告)号：US08748309B2
公开(公告)日：2014-06-10
申请号：US13618035
申请日：2012-09-14
申请人： Ruilong Xie , Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz
发明人： Ruilong Xie , Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz
IPC分类号： H01L21/44
CPC分类号： H01L29/4958 , H01L21/28088 , H01L21/32134 , H01L21/32135 , H01L29/4966 , H01L29/66545
摘要： Integrated circuits with improved gate uniformity and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure including a first region and a second region and a structure surface formed by the first region and the second region. The first region is formed by a first material and the second region is formed by a second material. In the method, the structure surface is exposed to a gas cluster ion beam (GCIB) and an irradiated layer is formed in the structure in both the first region and the second region. The irradiated layer is etched to form a recess.
摘要翻译：提供了具有改善的栅极均匀性的集成电路以及用于制造这种集成电路的方法。在一个实施例中，一种用于制造集成电路的方法包括提供包括第一区域和第二区域以及由第一区域和第二区域形成的结构表面的结构。第一区域由第一材料形成，第二区域由第二材料形成。在该方法中，将结构表面暴露于气体簇离子束（GCIB），在第一区域和第二区域的结构中形成照射层。被照射的层被蚀刻以形成凹部。

14. 发明授权

US08735272B2 Integrated circuit having a replacement gate structure and method for fabricating the same 有权
标题翻译：具有替代栅极结构的集成电路及其制造方法
公开(公告)号：US08735272B2
公开(公告)日：2014-05-27
申请号：US13562659
申请日：2012-07-31
申请人： Xiuyu Cai , Ruilong Xie , Kangguo Cheng , Ali Khakifirooz
发明人： Xiuyu Cai , Ruilong Xie , Kangguo Cheng , Ali Khakifirooz
IPC分类号： H01L21/4763
CPC分类号： H01L21/76834 , H01L21/28518 , H01L21/76897 , H01L29/165 , H01L29/6653 , H01L29/66545 , H01L29/66628 , H01L29/7834
摘要： A method for fabricating an integrated circuit includes forming a temporary gate structure on a semiconductor substrate. The temporary gate structure includes a temporary gate material disposed between two spacer structures. The method further includes forming a first directional silicon nitride liner overlying the temporary gate structure and the semiconductor substrate, etching the first directional silicon nitride liner overlying the temporary gate structure and the temporary gate material to form a trench between the spacer structures, while leaving the directional silicon nitride liner overlying the semiconductor substrate in place, and forming a replacement metal gate structure in the trench. An integrated circuit includes a replacement metal gate structure overlying a semiconductor substrate, a silicide region overlying the semiconductor substrate and positioned adjacent the replacement gate structure; a directional silicon nitride liner overlying a portion of the replacement gate structure; and a contact plug in electrical communication with the silicide region.
摘要翻译：一种用于制造集成电路的方法包括在半导体衬底上形成临时栅极结构。临时栅极结构包括设置在两个间隔结构之间的临时栅极材料。该方法还包括形成覆盖临时栅极结构和半导体衬底的第一定向硅氮化物衬垫，蚀刻覆盖临时栅极结构的第一定向氮化硅衬底和临时栅极材料，以在间隔物结构之间形成沟槽，同时留下定向氮化硅衬垫覆盖半导体衬底就位，并在沟槽中形成置换金属栅极结构。集成电路包括覆盖半导体衬底的替代金属栅极结构，覆盖半导体衬底并邻近置换栅结构定位的硅化物区; 覆盖所述替代栅极结构的一部分的定向氮化硅衬垫; 以及与硅化物区域电连通的接触插塞。

15. 发明申请

US20140077274A1 INTEGRATED CIRCUITS WITH IMPROVED GATE UNIFORMITY AND METHODS FOR FABRICATING SAME 有权
标题翻译：具有改进的门盖均匀性的集成电路及其制造方法
公开(公告)号：US20140077274A1
公开(公告)日：2014-03-20
申请号：US13618035
申请日：2012-09-14
申请人： Ruilong Xie , Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz
发明人： Ruilong Xie , Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz
IPC分类号： H01L29/78 , H01L21/425
CPC分类号： H01L29/4958 , H01L21/28088 , H01L21/32134 , H01L21/32135 , H01L29/4966 , H01L29/66545
摘要： Integrated circuits with improved gate uniformity and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure including a first region and a second region and a structure surface formed by the first region and the second region. The first region is formed by a first material and the second region is formed by a second material. In the method, the structure surface is exposed to a gas cluster ion beam (GCIB) and an irradiated layer is formed in the structure in both the first region and the second region. The irradiated layer is etched to form a recess.
摘要翻译：提供了具有改善的栅极均匀性的集成电路以及用于制造这种集成电路的方法。在一个实施例中，一种用于制造集成电路的方法包括提供包括第一区域和第二区域以及由第一区域和第二区域形成的结构表面的结构。第一区域由第一材料形成，第二区域由第二材料形成。在该方法中，将结构表面暴露于气体簇离子束（GCIB），在第一区域和第二区域的结构中形成照射层。被照射的层被蚀刻以形成凹部。

16. 发明申请

US20130328112A1 SEMICONDUCTOR DEVICES HAVING IMPROVED GATE HEIGHT UNIFORMITY AND METHODS FOR FABRICATING SAME 有权
标题翻译：具有改进的门高度均匀性的半导体器件及其制造方法
公开(公告)号：US20130328112A1
公开(公告)日：2013-12-12
申请号：US13493865
申请日：2012-06-11
申请人： Ruilong Xie , Xiuyu Cai , Andy C. Wei , Robert Miller
发明人： Ruilong Xie , Xiuyu Cai , Andy C. Wei , Robert Miller
IPC分类号： H01L21/28 , H01L29/78 , H01L21/8238
CPC分类号： H01L29/6653 , H01L21/823828 , H01L21/823864 , H01L29/66545 , H01L29/6656 , H01L29/78
摘要： Semiconductor devices and methods for fabricating semiconductor devices are provided. In an embodiment, a method for fabricating a semiconductor device includes forming on a semiconductor surface a temporary gate structure including a polysilicon gate and a cap. A spacer is formed around the temporary gate structure. The cap and a portion of the spacer are removed. A uniform liner is deposited overlying the polysilicon gate. The method removes a portion of the uniform liner overlying the polysilicon gate and the polysilicon gate to form a gate trench. Then, a replacement metal gate is formed in the gate trench.
摘要翻译：提供了用于制造半导体器件的半导体器件和方法。在一个实施例中，制造半导体器件的方法包括在半导体表面上形成包括多晶硅栅极和帽的临时栅极结构。在临时栅极结构周围形成间隔物。盖子和间隔件的一部分被去除。均匀的衬垫沉积在多晶硅栅极上。该方法去除覆盖多晶硅栅极和多晶硅栅极的均匀衬底的一部分以形成栅极沟槽。然后，在栅极沟槽中形成替换金属栅极。

17. 发明申请

US20110159213A1 CHEMICAL VAPOR DEPOSITION IMPROVEMENTS THROUGH RADICAL-COMPONENT MODIFICATION 审中-公开
标题翻译：化学蒸气沉积通过辐射成分修饰改进
公开(公告)号：US20110159213A1
公开(公告)日：2011-06-30
申请号：US12905582
申请日：2010-10-15
申请人： Xiuyu Cai , Yue Zhao , Abhijit Basu Mallick , Nitin K. Ingle , Shankar Venkataraman
发明人： Xiuyu Cai , Yue Zhao , Abhijit Basu Mallick , Nitin K. Ingle , Shankar Venkataraman
IPC分类号： C23C16/40 , C23C16/56 , C23C16/455 , C23C16/50
CPC分类号： C23C16/345 , C23C16/505 , C23C16/56
摘要： A method of forming a silicon oxide layer is described. The method may include the steps of mixing a carbon-free silicon-containing precursor with a radical-nitrogen precursor, and depositing a silicon-and-nitrogen-containing layer on a substrate. The radical-nitrogen precursor is formed in a plasma by flowing ammonia and nitrogen (N2) and/or hydrogen (H2) into the plasma in order to allow adjustment of the nitrogen/hydrogen ratio. The silicon-and-nitrogen-containing layer may be converted to a silicon-and-oxygen-containing layer by curing and annealing the film.
摘要翻译：描述形成氧化硅层的方法。该方法可以包括以下步骤：将无碳的含硅前体与自由基 - 氮前体混合，并在基底上沉积含硅和氮的层。通过将氨和氮（N 2）和/或氢（H 2）流入等离子体中以在等离子体中形成自由基 - 氮前体，以便调节氮/氢比。通过固化和退火膜可以将含硅和氮的层转化为含硅和氧的层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式