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11. 发明申请

US20070122924A1 METHOD OF FABRICATING METAL OXIDE SEMICONDUCTOR TRANSISTOR 审中-公开
标题翻译：制备金属氧化物半导体晶体管的方法
公开(公告)号：US20070122924A1
公开(公告)日：2007-05-31
申请号：US11669952
申请日：2007-02-01
申请人： Wen-Shiang Liao , Wei-Tsun Shiau
发明人： Wen-Shiang Liao , Wei-Tsun Shiau
IPC分类号： H01L21/00
CPC分类号： H01L21/823418 , H01L21/823814 , H01L29/66636 , H01L29/7834
摘要： A masking layer is formed over a substrate. The substrate and the masking layer are patterned to form trenches that partitions the substrate into first doping type semiconductor strips. An isolation layer is formed inside the trenches such that the surface of the isolation layer is below the upper surface of the first doping type semiconductor strips. A gate oxide layer is formed on the sidewalls of the first doping type semiconductor strips. Gates are formed over the substrate. The gates cover the masking layer above the first doping type semiconductor strips and the isolation layer inside the trenches. The gates are set in a direction perpendicular to the first doping type semiconductor strips. Spacers are formed on the sidewalls of the gates and the first doping type semiconductor strips. Second doping type source/drain regions are formed in the first doping type semiconductor strips on each side of the gates.
摘要翻译：在衬底上形成掩模层。将衬底和掩模层图案化以形成将衬底分隔成第一掺杂型半导体条的沟槽。隔离层形成在沟槽内，使得隔离层的表面在第一掺杂型半导体条的上表面之下。栅极氧化物层形成在第一掺杂型半导体条的侧壁上。盖板形成在基板上。栅极覆盖第一掺杂型半导体条上方的掩模层和沟槽内的隔离层。栅极设置在垂直于第一掺杂型半导体条的方向上。隔板形成在栅极的侧壁和第一掺杂型半导体条上。在栅极的每一侧的第一掺杂型半导体条中形成第二掺杂型源极/漏极区。

12. 发明授权

US06888181B1 Triple gate device having strained-silicon channel 有权
标题翻译：具有应变硅通道的三栅极器件
公开(公告)号：US06888181B1
公开(公告)日：2005-05-03
申请号：US10708694
申请日：2004-03-18
申请人： Wen-Shiang Liao , Wei-Tsun Shiau
发明人： Wen-Shiang Liao , Wei-Tsun Shiau
IPC分类号： H01L21/336 , H01L29/786 , H01L31/0328
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/78687
摘要： A three-dimensional Triple-Gate (Tri-gate) device having a three-sided strained silicon channel and superior drive current is provided. The Tri-gate device includes a composite fin structure consisting of a silicon germanium core and a three-sided strained silicon epitaxy layer grown from surface of said silicon germanium core. A gate strip wraps a channel portion of the composite fin structure. Two distal end portions of the composite fin structure not covered by the gate strip constitute source/drain regions of the Tri-gate device. A high quality gate insulating layer is interposed between the composite fin structure and the gate strip.
摘要翻译：提供具有三面应变硅通道和优良驱动电流的三维三栅极（三栅极）器件。三栅极器件包括由硅锗芯和从所述硅锗芯的表面生长的三面应变硅外延层组成的复合鳍结构。栅极条包裹复合翅片结构的通道部分。复合鳍片结构的未被栅极条覆盖的两个远端部分构成三栅极器件的源极/漏极区域。在复合翅片结构和栅极条之间插入有高质量的栅极绝缘层。

13. 发明申请

US20050087811A1 Method for fabricating a double gate MOSFET device 有权
标题翻译：制造双栅极MOSFET器件的方法
公开(公告)号：US20050087811A1
公开(公告)日：2005-04-28
申请号：US10976278
申请日：2004-10-29
申请人： Wen-Shiang Liao , Wei-Tsun Shiau
发明人： Wen-Shiang Liao , Wei-Tsun Shiau
IPC分类号： H01L21/336 , H01L29/423 , H01L29/49 , H01L29/786 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/4908 , H01L29/66795 , H01L29/66803
摘要： A method of fabricating a double gate MOSFET device is provided. The present invention overetches a silicon layer overlying a buried oxide layer using a hard mask of cap oxide on the silicon layer as an etching mask. As a result, source, drain and channel regions are formed extending from the buried oxide layer, and a pair of recesses are formed under the channel regions in the buried oxide layer. The channel is a fin structure with a top surface and two opposing parallelly sidewalls. The bottom recess is formed under each opposing sidewall of the fin structure. A conductive gate layer is formed straddling the fin structures. The topography of the conductive gate layer significantly deviates from the conventional plainer profile due to the bottom recess structures under the channel regions, and a more uniformly distributed doped conductive gate layer can be obtained. Hence, the depletion effect of the conductive polysilicon gate while operating the device can be suppressed and the device drive-on currents can be further enhanced.
摘要翻译：提供一种制造双栅极MOSFET器件的方法。本发明使用硅层上的氧化碳膜的硬掩模作为蚀刻掩模来蚀刻覆盖掩埋氧化物层的硅层。结果，从掩埋氧化物层形成源极，漏极和沟道区，并且在掩埋氧化物层的沟道区的下方形成一对凹部。通道是具有顶表面和两个相对的平行侧壁的翅片结构。底部凹部形成在翅片结构的每个相对侧壁下方。导电栅极层跨越翅片结构形成。导电栅极层的形貌由于在沟道区下面的底部凹陷结构而显着地偏离常规的平滑轮廓，并且可以获得更均匀分布的掺杂的导电栅极层。因此，可以抑制在操作器件时导电多晶硅栅极的耗尽效应，并且可以进一步提高器件驱动电流。

14. 发明授权

US07732886B2 Pin photodiode structure 有权
标题翻译：引脚光电二极管结构
公开(公告)号：US07732886B2
公开(公告)日：2010-06-08
申请号：US12173807
申请日：2008-07-15
申请人： Hung-Lin Shih , Tsan-Chi Chu , Wen-Shiang Liao , Wen-Ching Tsai
发明人： Hung-Lin Shih , Tsan-Chi Chu , Wen-Shiang Liao , Wen-Ching Tsai
IPC分类号： H01L29/06
CPC分类号： H01L31/1055 , H01L27/1203 , H01L31/028 , H01L31/105 , H01L31/1808 , Y02E10/547
摘要： A PIN photodiode structure includes a substrate, a P-doped region disposed in the substrate, an N-doped region disposed in the substrate, and a first semiconductor material disposed in the substrate and between the P-doped region and the N-doped region.
摘要翻译： PIN光电二极管结构包括衬底，设置在衬底中的P掺杂区域，设置在衬底中的N掺杂区域和设置在衬底中并且在P掺杂区域和N掺杂区域之间的第一半导体材料。

15. 发明授权

US06740570B2 Method for forming a self-aligned silicide of a metal oxide semiconductor 有权
标题翻译：用于形成金属氧化物半导体的自对准硅化物的方法
公开(公告)号：US06740570B2
公开(公告)日：2004-05-25
申请号：US10188526
申请日：2002-07-03
申请人： Wei-Fan Chen , Wen-Shiang Liao , Ming-Lun Chang
发明人： Wei-Fan Chen , Wen-Shiang Liao , Ming-Lun Chang
IPC分类号： H01L21425
CPC分类号： H01L29/665 , H01L21/265 , H01L21/28518
摘要： The present invention discloses a method for forming a self-aligned silicidation of a metal oxide semiconductor. The feature of the present invention is to perform an ionic implanting step before carrying on the self-aligned silicidation. The implanted ion of the present invention, such as fluorine, chlorine, bromine, iodine, boron and trifluroborane, will react with the silicon on the surface of the gate structure and the silicon substrate and a barrier effect will be formed during silicidation. Therefore, a spike phenomenon because of the penetration of cobalt or the cobalt silicide into the gate structure or the source/drain regions is prevented. The junction leakage current and the breakdown voltage of the metal oxide semiconductor are avoided.
摘要翻译：本发明公开了一种形成金属氧化物半导体的自对准硅化物的方法。本发明的特征是在进行自对准硅化物之前进行离子注入步骤。本发明的注入离子如氟，氯，溴，碘，硼和三氟硼烷将与栅极结构和硅衬底的表面上的硅反应，并在硅化过程中形成屏障效应。因此，防止了钴或硅化钴渗入栅极结构或源极/漏极区域的尖峰现象。避免了金属氧化物半导体的结漏电流和击穿电压。

16. 发明授权

US06174753B1 Mask reduction process with a method of forming a raised fuse and a fuse window with sidewall passivation 有权
标题翻译：通过形成凸起保险丝的方法和具有侧壁钝化的保险丝窗口的掩模缩小工艺
公开(公告)号：US06174753B1
公开(公告)日：2001-01-16
申请号：US09252187
申请日：1999-02-18
申请人： Wen-Shiang Liao
发明人： Wen-Shiang Liao
IPC分类号： H01L2182
CPC分类号： H01L21/76804 , H01L23/5258 , H01L2924/0002 , Y10S148/055 , H01L2924/00
摘要： The present invention discloses a mask reduction process to reduce the number of mask processes employed in the post-process of metal line formation. A fuse window opening can be formed together with the defining of contact holes. A pad opening can also be formed at the same time with the etching of a fuse window. With the process integration proposed in the present invention, a raised fuse and a fuse window with sidewall passivation can be formed.
摘要翻译：本发明公开了减少金属线形成后处理中采用的掩模工艺数量的掩模还原方法。保险丝窗口可以与接触孔的限定一起形成。也可以在熔丝窗口的蚀刻的同时形成焊盘开口。通过本发明提出的工艺集成，可以形成具有侧壁钝化的凸起熔丝和熔丝窗。

17. 发明授权

US6096579A Method for controlling the thickness of a passivation layer on a semiconductor device 有权
标题翻译：用于控制半导体器件上的钝化层的厚度的方法
公开(公告)号：US6096579A
公开(公告)日：2000-08-01
申请号：US276260
申请日：1999-03-25
申请人： Wen-Shiang Liao , Wan-Yih Lien
发明人： Wen-Shiang Liao , Wan-Yih Lien
IPC分类号： H01L21/311 , H01L21/768 , H01L23/525 , H01L21/82
CPC分类号： H01L23/5258 , H01L21/31116 , H01L21/76802 , H01L2924/0002
摘要： A method for controlling the thickness of a passivation layer underlying with a fuse on a semiconductor device is disclosed herein. The anti-reflective coating on a metal layer is buried in the passivation layer, and the fuse is in a semiconductor device. The method includes the following steps. First, use a first etchant and Ar to etch the passivation layer till the anti-reflective coating is exposed, the first thickness of the passivation layer above the anti-reflective coating is smaller than the second thickness of the passivation layer above the fuse. Then, utilize a second etchant to etch the anti-reflective coating till the metal layer is exposed. The second etchant has a selectivity ratio from the anti-reflective coating to the passivation layer being at least 10. The second etchant mentioned above includes BCl.sub.3, Cl.sub.2, O.sub.2, and Ar.
摘要翻译：本文公开了一种用于控制半导体器件上的熔丝下面的钝化层的厚度的方法。金属层上的抗反射涂层被埋在钝化层中，并且熔丝处于半导体器件中。该方法包括以下步骤。首先，使用第一蚀刻剂和Ar蚀刻钝化层直到抗反射涂层露出，抗反射涂层上方的钝化层的第一厚度小于熔丝上方钝化层的第二厚度。然后，利用第二蚀刻剂来蚀刻抗反射涂层，直到暴露金属层。第二蚀刻剂具有从抗反射涂层到钝化层的选择比至少为10.上述第二蚀刻剂包括BCl 3，Cl 2，O 2和Ar。

18. 发明申请

US20090294903A1 ANTI-FUSSE STRUCTURE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：抗融合结构及其制造方法
公开(公告)号：US20090294903A1
公开(公告)日：2009-12-03
申请号：US12132111
申请日：2008-06-03
申请人： Hung-Lin Shih , Wen-Shiang Liao , Tsan-Chi Chu
发明人： Hung-Lin Shih , Wen-Shiang Liao , Tsan-Chi Chu
IPC分类号： H01L23/525 , H01L21/02
CPC分类号： H01L23/5252 , H01L27/0733 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure and a method of fabricating the same are described. The anti-fuse structure is disposed over a substrate having at least one device and a copper layer therein. The anti-fuse structure includes a bottom conductive layer, an insulating layer and a top conductive layer. The bottom conductive layer is disposed over and electrically connected with the copper layer. The insulating layer is conformally disposed over the bottom conductive layer covering a corner or a downward turning portion of the bottom conductive layer to form a turning portion of the insulating layer. The top conductive layer is conformally disposed over the insulting layer covering the turning portion of the insulating layer.
摘要翻译：描述了一种抗熔丝结构及其制造方法。反熔丝结构设置在其中具有至少一个器件和铜层的衬底上。反熔丝结构包括底部导电层，绝缘层和顶部导电层。底部导电层设置在铜层上并与铜层电连接。绝缘层保形地设置在覆盖底部导电层的拐角或向下转动部分的底部导电层上，以形成绝缘层的转动部分。顶部导电层保形地设置在覆盖绝缘层的转向部分的绝缘层上。

19. 发明授权

US06534402B1 Method of fabricating self-aligned silicide 失效
标题翻译：制造自对准硅化物的方法
公开(公告)号：US06534402B1
公开(公告)日：2003-03-18
申请号：US10025430
申请日：2001-12-19
申请人： Wen-Shiang Liao
发明人： Wen-Shiang Liao
IPC分类号： H01L2144
CPC分类号： H01L21/28044 , H01L21/26506 , H01L21/28052 , H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method of fabricating a self-aligned silicide (salicide). A gate and a source/drain region are formed in the substrate. An ion implantation process is performed to dope surfaces of the gate and the source/drain region with metal ions. A thermal process is performed to have the metal ions react with silicon in surfaces of the gate and the source/drain region, so as to form silicide layers on the gate and the source/drain region. The metal ions include cobalt ions, titanium ions, nickel ions, platinum ions and palladium ions.
摘要翻译：制造自对准硅化物（自对准硅化物）的方法。在衬底中形成栅极和源极/漏极区域。进行离子注入工艺以用金属离子掺杂栅极和源极/漏极区域的表面。执行热处理以使金属离子与栅极和源极/漏极区域的表面中的硅反应，以在栅极和源极/漏极区域上形成硅化物层。金属离子包括钴离子，钛离子，镍离子，铂离子和钯离子。

20. 发明申请

US20100012974A1 PIN PHOTODIODE STRUCTURE AND METHOD FOR MAKING THE SAME 有权
标题翻译： PIN光电结构及其制造方法
公开(公告)号：US20100012974A1
公开(公告)日：2010-01-21
申请号：US12173807
申请日：2008-07-15
申请人： Hung-Lin Shih , Tsan-Chi Chu , Wen-Shiang Liao , Wen-Ching Tsai
发明人： Hung-Lin Shih , Tsan-Chi Chu , Wen-Shiang Liao , Wen-Ching Tsai
IPC分类号： H01L31/0336 , H01L31/105 , H01L31/18
CPC分类号： H01L31/1055 , H01L27/1203 , H01L31/028 , H01L31/105 , H01L31/1808 , Y02E10/547
摘要： A PIN photodiode structure includes a substrate, a P-doped region disposed in the substrate, an N-doped region disposed in the substrate, and a first semiconductor material disposed in the substrate and between the P-doped region and the N-doped region.
摘要翻译： PIN光电二极管结构包括衬底，设置在衬底中的P掺杂区域，设置在衬底中的N掺杂区域和设置在衬底中并且在P掺杂区域和N掺杂区域之间的第一半导体材料。

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