专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07455021B2 Method and apparatus for controlling friction between a fluid and a body 有权
标题翻译：用于控制流体和身体之间摩擦的方法和装置
公开(公告)号：US07455021B2
公开(公告)日：2008-11-25
申请号：US11518694
申请日：2006-09-11
申请人： Avinoam Kornblit , Timofei Nikita Kroupenkine , Mary Louise Mandich , Tobias Manuel Schneider , Joseph Ashley Taylor , Donald Weiss , Shu Yang
发明人： Avinoam Kornblit , Timofei Nikita Kroupenkine , Mary Louise Mandich , Tobias Manuel Schneider , Joseph Ashley Taylor , Donald Weiss , Shu Yang
IPC分类号： B63B1/34 , B63B21/00
CPC分类号： B63B1/34 , B63H25/00 , Y02T70/121
摘要： A method and apparatus is disclosed wherein nanostructures or microstructures are disposed on a surface of a body (such as a submersible vehicle) that is adapted to move through a fluid, such as water. The nanostructures or microstructures are disposed on the surface in a way such that the contact between the surface and the fluid is reduced and, correspondingly, the friction between the surface and the fluid is reduced. In an illustrative embodiment, the surface is a surface on a submarine or other submersible vehicle (such as a torpedo). Illustratively, electrowetting principles are used to cause the fluid to at least partially penetrate the nanostructures or microstructures on the surface of the body in order to selectively create greater friction in a desired location of the surface. Such penetration may be used, for example, to create drag that alters the direction or speed of travel of the body.
摘要翻译：公开了一种方法和装置，其中将纳米结构或微结构布置在适于移动通过诸如水的流体的主体（例如潜水车辆）的表面上。纳米结构或微结构以这样的方式设置在表面上，使得表面和流体之间的接触减小，并且相应地减小了表面和流体之间的摩擦。在说明性实施例中，表面是潜艇或其他潜水车辆（例如鱼雷）上的表面。说明性地，使用电润湿原理使流体至少部分地穿透身体表面上的纳米结构或微结构，以便在表面的期望位置选择性地产生更大的摩擦。例如，可以使用这种穿透来产生改变身体行进方向或速度的阻力。

12. 发明授权

US08030199B2 Transistor fabrication method 有权
标题翻译：晶体管制造方法
公开(公告)号：US08030199B2
公开(公告)日：2011-10-04
申请号：US12689749
申请日：2010-01-19
申请人： Sailesh Chittipeddi , Taeho Kook , Avinoam Kornblit
发明人： Sailesh Chittipeddi , Taeho Kook , Avinoam Kornblit
IPC分类号： H01L21/00
CPC分类号： H01L29/7833 , H01L21/28518 , H01L29/665 , H01L29/66545 , H01L29/6659 , Y10S438/945
摘要： A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A variety of silicided and non-silicided) structures may be formed.
摘要翻译：公开了一种形成集成电路中没有通道的可控线宽的低堆叠高度晶体管的方法。使用掺杂玻璃的一次性硬掩模来限定栅极并且随后在形成源极和漏极的离子注入期间保护栅极（和下面的衬底）。可以形成各种硅化和非硅化的结构。

13. 发明授权

US08025271B2 Directed-flow conduit 有权
标题翻译：定向导管
公开(公告)号：US08025271B2
公开(公告)日：2011-09-27
申请号：US12080409
申请日：2008-03-31
申请人： Paul Robert Kolodner , Avinoam Kornblit , Thomas Nikita Krupenkin , Alan Michael Lyons , Todd Richard Salamon
发明人： Paul Robert Kolodner , Avinoam Kornblit , Thomas Nikita Krupenkin , Alan Michael Lyons , Todd Richard Salamon
IPC分类号： B01F3/04
CPC分类号： F15D1/065 , B33Y80/00 , Y10T137/0391 , Y10T137/87249
摘要： Device including channel having channel input and output. Channel has interior channel surface extending along channel path from channel input to output. In one implementation, channel includes plurality of channel sections in serial communication along channel path. Each of channel sections includes first internal circumference spaced apart along channel path from second internal circumference, in each of channel sections the first and second internal circumferences being substantially different. Each of channel sections includes sub-surface of interior channel surface. At least region of sub-surface of each channel section includes distribution of raised micro-scale features. As another implementation, at least first region of interior channel surface includes distribution of raised micro-scale features interrupted by plurality of raised barriers spaced apart along channel path on interior channel surface. Each raised barrier extends on interior channel surface in directions partially transverse to and partially parallel to longitudinal axis. Method also provided.
摘要翻译：设备包括具有通道输入和输出的通道。通道具有从通道输入到输出的通道路径延伸的内部通道表面。在一个实现中，信道包括沿着信道路径串行通信的多个信道段。每个通道部分包括沿着与第二内圆周的通道路径间隔开的第一内圆周，在每个通道部分中，第一和第二内圆周基本不同。每个通道部分包括内部通道表面的子表面。每个通道部分的子表面的至少区域包括凸起的微尺度特征的分布。作为另一实施方案，内部通道表面的至少第一区域包括由在内部通道表面上沿着通道路径间隔开的多个凸起的屏障中断的凸起的微尺度特征的分布。每个凸起的屏障在内部通道表面上沿与纵向轴线部分横向并部分平行的方向延伸。方法也提供。

14. 发明申请

US20080280403A1 TRANSISTOR FABRICATION METHOD 审中-公开
标题翻译：晶体管制造方法
公开(公告)号：US20080280403A1
公开(公告)日：2008-11-13
申请号：US12114589
申请日：2008-05-02
申请人： Sailesh Chittipeddi , Taeho Kook , Avinoam Kornblit
发明人： Sailesh Chittipeddi , Taeho Kook , Avinoam Kornblit
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L21/28518 , H01L29/665 , H01L29/66545 , H01L29/6659 , Y10S438/945
摘要： A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A variety of silicided and non-silicided) structures may be formed.
摘要翻译：公开了一种形成集成电路中没有通道的可控线宽的低堆叠高度晶体管的方法。使用掺杂玻璃的一次性硬掩模来限定栅极并且随后在形成源极和漏极的离子注入期间保护栅极（和下面的衬底）。可以形成各种硅化和非硅化的结构。

15. 发明授权

US06228277B1 Etch endpoint detection 有权
标题翻译：蚀刻端点检测
公开(公告)号：US06228277B1
公开(公告)日：2001-05-08
申请号：US09172456
申请日：1998-10-14
申请人： Avinoam Kornblit , Tseng-Chung Lee , Heon Lee , Helen Louise Maynard
发明人： Avinoam Kornblit , Tseng-Chung Lee , Heon Lee , Helen Louise Maynard
IPC分类号： H01L2166
CPC分类号： H01L22/26 , G01B11/0683 , H01J37/32935 , H01J2237/334
摘要： The specification describes an interferometric in-situ end point detection technique for plasma etching in which the end point is predicted before any overetching occurs. It is based on the recognition that the wavelength of the monitoring beam can be selected so that only a single interferometric fringe appears before clearing. Knowing there is only one fringe, detection is simplified and the etching process can be terminated while a finite but small thickness of the layer remains. This allows etching partial thicknesses of layers. It also allows a two step etch process wherein the etch chemistry can be changed to a highly selective etch to complete clearing of the layer.
摘要翻译：本说明书描述了用于等离子体蚀刻的干涉式原位终点检测技术，其中在任何过蚀刻发生之前预测终点。基于这样的认识，可以选择监测光束的波长，使得在清除之前仅出现单个干涉条纹。知道只有一个边缘，检测被简化，并且蚀刻过程可以终止，同时层的有限但较小的厚度保留。这允许蚀刻层的部分厚度。它还允许两步蚀刻工艺，其中蚀刻化学物质可以改变为高选择性蚀刻以完成层的清除。

16. 发明申请

US20050186118A1 Micro-channel chemical concentrator 有权
标题翻译：微通道化学浓缩机
公开(公告)号：US20050186118A1
公开(公告)日：2005-08-25
申请号：US10786199
申请日：2004-02-25
申请人： David Bishop , John Gates , Marc Hodes , Avinoam Kornblit , Stanley Pau , Brijesh Vyas
发明人： David Bishop , John Gates , Marc Hodes , Avinoam Kornblit , Stanley Pau , Brijesh Vyas
IPC分类号： B01D1/00 , B01D61/36 , B01D63/08 , B01L3/00 , B01L99/00 , G01N1/40
CPC分类号： B01D61/364 , B01D1/00 , B01D63/087 , B01D63/088 , G01N2001/4027 , Y10T436/255 , Y10T436/2575 , Y10T436/25875
摘要： Apparatus and method for increasing the concentration of a chemical substance in a fluid comprise a micro-fluidic elongated channel formed in a substrate, with the channel being in fluid-flow communication with an ambient region along its elongated dimension. In general, the fluid includes first and second chemical substances having different vapor pressures. The apparatus includes an evaporation controller for increasing the evaporation rate of the fluid from the channel into the ambient region, thereby increasing the concentration of the higher vapor pressure (HVP) substance in the portion of the fluid remaining in the channel and increasing the concentration of the lower vapor pressure (LVP) substance in the portion of the fluid evaporated into the ambient region.
摘要翻译：用于增加流体中化学物质浓度的装置和方法包括形成在基底中的微流体细长通道，其中通道沿其细长尺寸与环境区域流体流动连通。通常，流体包括具有不同蒸气压的第一和第二化学物质。该装置包括用于增加流体从通道进入环境区域的蒸发速率的蒸发控制器，从而增加通道中保留的流体部分中较高蒸气压（HVP）物质的浓度，流体部分中的较低蒸汽压（LVP）物质蒸发到环境区域。

17. 发明授权

US06511872B1 Device having a high dielectric constant material and a method of manufacture thereof 有权
标题翻译：具有高介电常数材料的装置及其制造方法
公开(公告)号：US06511872B1
公开(公告)日：2003-01-28
申请号：US09902358
申请日：2001-07-10
申请人： Vincent M. Donnelly, Jr. , Avinoam Kornblit , Kalman Pelhos
发明人： Vincent M. Donnelly, Jr. , Avinoam Kornblit , Kalman Pelhos
IPC分类号： H01L21336
CPC分类号： H01L29/517 , H01L21/28167 , H01L21/28194 , H01L21/31122 , H01L21/823828
摘要： The present invention provides a method of manufacturing a semiconductor device. The method includes depositing a metal oxide containing a dopant and having a high dielectric constant on a substrate; wherein the metal is aluminum or silicon and the dopant is zirconium or hafnium and etching the doped metal oxide with a plasma containing a halogenated compound.
摘要翻译：本发明提供一种制造半导体器件的方法。该方法包括在衬底上沉积含有掺杂剂并具有高介电常数的金属氧化物; 其中所述金属是铝或硅，并且所述掺杂剂是锆或铪，并用含有卤化化合物的等离子体蚀刻掺杂的金属氧化物。

18. 发明申请

US20100120216A1 TRANSISTOR FABRICATION METHOD 有权
标题翻译：晶体管制造方法
公开(公告)号：US20100120216A1
公开(公告)日：2010-05-13
申请号：US12689749
申请日：2010-01-19
申请人： Sailesh Chittipeddi , Taeho Kook , Avinoam Kornblit
发明人： Sailesh Chittipeddi , Taeho Kook , Avinoam Kornblit
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L21/28518 , H01L29/665 , H01L29/66545 , H01L29/6659 , Y10S438/945
摘要： A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A variety of silicided and non-silicided) structures may be formed.
摘要翻译：公开了一种形成集成电路中没有通道的可控线宽的低堆叠高度晶体管的方法。使用掺杂玻璃的一次性硬掩模来限定栅极并且随后在形成源极和漏极的离子注入期间保护栅极（和下面的衬底）。可以形成各种硅化和非硅化的结构。

19. 发明授权

US6051346A Process for fabricating a lithographic mask 失效
标题翻译：光刻掩模的制造工艺
公开(公告)号：US6051346A
公开(公告)日：2000-04-18
申请号：US121266
申请日：1998-07-23
申请人： Avinoam Kornblit , James Alexander Liddle , Anthony Edward Novembre
发明人： Avinoam Kornblit , James Alexander Liddle , Anthony Edward Novembre
IPC分类号： H01L21/027 , G03F1/20 , G03F1/22 , G03F9/00
CPC分类号： G03F1/22 , G03F1/20
摘要： The invention provides an improved process for fabricating masks suitable for use in SCALPEL and similar electron-based or ion-based lithographic processes. Specifically, the process allows use of commercially-available (100) oriented silicon substrates, and better control over the profiles of mask struts. Specifically, the struts of the mask are formed by plasma etching, using a fluorine-based gas, and a unique multilayer mask blank is fabricated to promote successful use of the plasma etch. According to an embodiment of the process, an etch stop layer is deposited onto the front surface of a silicon substrate, and a membrane layer is deposited over the etch stop layer. A scattering layer, typically tungsten, is deposited over the membrane layer. A patterning layer is deposited on the back surface of the substrate, and the desired grillage pattern for the struts is patterned into the patterning layer. The grillage structure is then etched into the silicon, to form the struts, by plasma etching with the fluorine-based gas. The etch stop layer acts to prevent the etch from damaging the membrane layer.
摘要翻译：本发明提供了一种用于制造适用于SCALPEL和类似的基于电子或基于离子的光刻工艺的掩模的改进方法。具体来说，该方法允许使用市售的（100）定向硅衬底，并且更好地控制掩模支柱的轮廓。具体地，通过使用氟基气体的等离子体蚀刻形成掩模的支柱，并且制造独特的多层掩模坯料以促进等离子体蚀刻的成功应用。根据该方法的一个实施方案，将蚀刻停止层沉积在硅衬底的前表面上，并且膜层沉积在蚀刻停止层上。散布层（通常为钨）沉积在膜层上。图案层沉积在衬底的背面，并且用于支柱的所需格栅图案被图案化成图形层。然后通过用氟基气体的等离子体蚀刻将格栅结构蚀刻到硅中以形成支柱。蚀刻停止层用于防止蚀刻损坏膜层。

20. 发明授权

US4824796A Process for manufacturing semiconductor BICMOS device 失效
标题翻译：制造半导体BICMOS器件的工艺
公开(公告)号：US4824796A
公开(公告)日：1989-04-25
申请号：US77953
申请日：1987-07-10
申请人： Tzu-Yin Chiu , Gen M. Chin , Ronald C. Hanson , Maureen Y. Lau , Kwing F. Lee , Mark D. Morris , Alexander M. Voshchenkov , Avinoam Kornblit , Joseph Lebowitz , William T. Lynch
发明人： Tzu-Yin Chiu , Gen M. Chin , Ronald C. Hanson , Maureen Y. Lau , Kwing F. Lee , Mark D. Morris , Alexander M. Voshchenkov , Avinoam Kornblit , Joseph Lebowitz , William T. Lynch
IPC分类号： H01L29/73 , H01L21/225 , H01L21/3215 , H01L21/331 , H01L21/82 , H01L21/8249 , H01L27/06 , H01L29/732 , H01L21/70 , H01L27/00
CPC分类号： H01L29/41783 , H01L21/2257 , H01L21/32155 , H01L21/8249 , H01L27/0623 , Y10S148/009 , Y10S148/01 , Y10S148/124 , Y10S148/151
摘要： A process for creating bipolar and CMOS transistors on a p-type silicon substrate is disclosed. The silicon substrate has typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer in contact with the epitaxial layer. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon in contact with the epitaxial layer is deposited outside the walls surrounding the stacks. All polycrystalline silicon layers in contact with the epitaxial layer are implanted with appropriate dopants such that these layers serve as reservoirs of dopant in order to simultaneously create the source and drain elements of the CMOS devices and the emitter elements of the bipolar devices during a heating step in the process. A tungsten layer is deposited over the polycrystalline layer in order to provide a conductive coupling to aluminum electrodes.
摘要翻译：公开了一种在p型硅衬底上制造双极和CMOS晶体管的工艺。硅衬底具有典型的n +掩埋阱和场氧化物区域以隔离各个晶体管器件。根据该过程，在CMOS器件的栅极元件和双极晶体管的发射极元件之上形成材料堆叠。在栅极元件上的堆叠材料具有与衬底的外延层接触的二氧化硅栅极层，并且在发射极元件上的材料堆叠具有与外延层接触的多晶硅层。在堆叠周围产生二氧化硅壁，以便将堆叠内的材料与沉积在壁外部的材料隔离。与外延层接触的多晶硅沉积在堆叠周围的壁的外部。与外延层接触的所有多晶硅层都注入合适的掺杂剂，使得这些层用作掺杂剂的储存器，以便在加热步骤期间同时产生CMOS器件的源极和漏极元件以及双极器件的发射极元件正在进行中。为了提供与铝电极的导电耦合，在多晶层上沉积钨层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式