专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US5452260A Semiconductor memory circuit 失效
标题翻译：半导体存储电路
公开(公告)号：US5452260A
公开(公告)日：1995-09-19
申请号：US215487
申请日：1994-03-21
申请人： Katsuaki Matsui , Sampei Miyamoto , Tamihiro Ishimura
发明人： Katsuaki Matsui , Sampei Miyamoto , Tamihiro Ishimura
IPC分类号： G11C11/413 , G11C8/10 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/408 , G11C8/00
CPC分类号： G11C8/12 , G11C8/10
摘要： A semiconductor memory circuit selects one memory cell group in response to an address signal having block selection information, first and second significant bit information. First, to third memory cell blocks respectively have memory cell groups each including memory cells. First, to third decoder groups respectively have first decoders each coupled to one memory cell group in the first memory cell block, second decoders each coupled to one memory cell group in the second memory cell block, and third decoders each coupled to one memory cell group in the third memory cell block. First and second logic circuits respectively output a first common block selection signal with respect to the first and second memory cell blocks in response to the block selection information of the address signal, and a second common block selection signal with respect to the second and third memory cell blocks in response to the block selection information of the address signal. Third and fourth logic circuits respectively, in response to the second and first significant information, apply first common decode signals to the first and second decoder groups upon the first common block selection signal being outputted, and a plurality of second common decode signals to the second and third decoder groups upon the second common block selection signal being outputted. In response to the first and second common decode signals, a second decoder in the second decoder group is activated to select one memory cell group in the second memory cell block.
摘要翻译：半导体存储器电路响应具有块选择信息的地址信号，第一和第二有效位信息来选择一个存储单元组。首先，对第三存储单元块分别具有各自包含存储单元的存储单元组。首先，第三解码器组分别具有耦合到第一存储器单元块中的一个存储单元组的第一解码器，每个耦合到第二存储单元块中的一个存储单元组的第二解码器，以及每个耦合到一个存储单元组的第三解码器在第三个存储单元块中。第一和第二逻辑电路响应于地址信号的块选择信息分别输出关于第一和第二存储单元块的第一公共块选择信号，以及相对于第二和第三存储器的第二公共块选择信号响应于地址信号的块选择信息的单元块。第三和第四逻辑电路分别响应于第二和第一有效信息，在第一公共块选择信号被输出时，将第一公共解码信号应用于第一和第二解码器组，并将多个第二公共解码信号施加到第二公共解码信号第三解码器组输出第二公共块选择信号。响应于第一和第二公共解码信号，第二解码器组中的第二解码器被激活以选择第二存储器单元块中的一个存储器单元组。

12. 发明授权

US5363331A Semiconductor memory with column line control circuits for protection against broken column lines 失效
标题翻译：具有列线控制电路的半导体存储器，用于防止断线损坏
公开(公告)号：US5363331A
公开(公告)日：1994-11-08
申请号：US994674
申请日：1992-12-22
申请人： Katsuaki Matsui , Sampei Miyamoto
发明人： Katsuaki Matsui , Sampei Miyamoto
IPC分类号： G11C7/12 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/04 , G11C7/02
CPC分类号： G11C29/70 , G11C7/12
摘要： A semiconductor memory device has plural memory cell blocks, each including memory cells storing data therein. A data bus and switching circuits transfer data from the memory cells to the data bus in response to a first logic level signal applied thereto. Column lines each have first and second ends. Each column line is connected to the corresponding switching circuit in each of the memory cell blocks. A column decoder, coupled to the first end of the column lines, provides the first logic level signal to one of the column lines upon the memory cell blocks being accessed. Potential setting circuits are coupled to the second end of the column lines, and preliminarily set the respective column lines to be in a predetermined potential so that each switching circuit is inactive prior to the column decoder providing the first logic level signal. All the memory cells in an array can be prevented from becoming inoperative even if a column line is broken.
摘要翻译：半导体存储器件具有多个存储单元块，每个存储单元块包括在其中存储数据的存储器单元。数据总线和开关电路响应于施加到其上的第一逻辑电平信号将数据从存储器单元传送到数据总线。列线各具有第一和第二端。每个列线连接到每个存储单元块中的相应的开关电路。耦合到列线的第一端的列解码器在访问存储器单元块时将第一逻辑电平信号提供给列线之一。电位设置电路耦合到列线的第二端，并且预先将各列线设置为预定电位，使得在列解码器提供第一逻辑电平信号之前每个开关电路不活动。阵列中的所有存储单元即使列线被破坏，也可以防止它们不起作用。

13. 发明授权

US5699316A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5699316A
公开(公告)日：1997-12-16
申请号：US542221
申请日：1995-10-12
申请人： Katsuaki Matsui , Tamihiro Ishimura , Sampei Miyamoto
发明人： Katsuaki Matsui , Tamihiro Ishimura , Sampei Miyamoto
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C11/409 , G11C11/4096 , G11C11/419 , G11C11/34 , H01L27/10
CPC分类号： G11C11/419 , G11C11/4096 , G11C7/1048
摘要： A semiconductor memory device according to the present invention comprise a plurality of arrays each supplied with a common column address signal. In an selected array, the potential of a data line is set to a potential corresponding to a potential supplied to a corresponding bit line in response to the potential of the bit line, the potential of the corresponding column address signal and the potential of a terminal. In non-selected array other than the selected array at this time, since the potential of a terminal in the non-selected array is set to a potential different from that of the terminal in the selected array, the potential of the data line remains unchanged irrespective of the column address signal.
摘要翻译：根据本发明的半导体存储器件包括多个阵列，每个阵列都具有公共列地址信号。在所选择的阵列中，响应于位线的电位，相应的列地址信号的电位和端子的电位，将数据线的电位设置为对应于提供给相应位线的电位的电位。在这个时候，除了所选择的阵列以外的非选择的阵列中，由于未选择的阵列中的终端的电位被设置为与所选择的阵列中的终端的电位不同的电位，所以数据线的电位保持不变不管列地址信号如何。

14. 发明授权

US5686752A Semiconductor device having a CMOS element as a buffer 失效
标题翻译：具有CMOS元件作为缓冲器的半导体器件
公开(公告)号：US5686752A
公开(公告)日：1997-11-11
申请号：US576614
申请日：1995-12-21
申请人： Tamihiro Ishimura , Sampei Miyamoto
发明人： Tamihiro Ishimura , Sampei Miyamoto
IPC分类号： G11C11/413 , G11C11/408 , G11C11/409 , H01L21/822 , H01L27/04 , H01L27/08 , H01L27/092 , H03K17/08 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/0948 , H01L29/76 , H01L29/94
CPC分类号： H03K19/00315 , H01L27/0921
摘要： A PMOS 21 and an NMOS 22, which are connected in series between a power supply potential Vcc and a ground potential Vss, perform ON and Off operation in accordance with data signals G1 and G2 from an output buffer control circuit 40, and generate an output signal. A Vpp generating circuit 50 generates a potential Vpp higher than the power supply potential Vcc and a back gate bias of the PMOS 21 is set at the potential Vpp. Even if a latch-up trigger current due to a surge voltage is produced, the back gate bias of the PMOS 21 is set at Vpp and therefore a potential difference caused in an N type well resistor becomes small and a base potential of a parasitic bipolar transistor disposed between the N type well 2 and a substrate 1 becomes approximate to the potential Vpp. Accordingly, the current which flows into the substrate 1 is suppressed and a latch-up tolerance is improved.
摘要翻译：串联连接在电源电位Vcc和接地电位Vss之间的PMOS21和NMOS22根据来自输出缓冲器控制电路40的数据信号G1和G2进行ON和OFF操作，并产生输出信号。 Vpp发生电路50产生高于电源电位Vcc的电位Vpp，并且将PMOS21的背栅极偏置设置为电位Vpp。即使产生由于浪涌电压引起的闭锁触发电流，PMOS21的背栅极偏置被设定为Vpp，因此在N型阱电阻中引起的电位差变小，并且寄生双极性的基极电位配置在N型阱2和基板1之间的晶体管接近电位Vpp。因此，流入基板1的电流被抑制，并且提高了闩锁公差。

15. 发明授权

US5502415A Booster power generating circuit 失效
标题翻译：增压发电电路
公开(公告)号：US5502415A
公开(公告)日：1996-03-26
申请号：US256228
申请日：1994-06-29
申请人： Katsuaki Matsui , Sampei Miyamoto , Hidekazu Kikuchi
发明人： Katsuaki Matsui , Sampei Miyamoto , Hidekazu Kikuchi
IPC分类号： H02M3/07 , G05F1/10
CPC分类号： H02M3/073
摘要： A booster power generating circuit according to the present invention comprises first to fourth booster circuits for supplying first to fourth booster potentials to first to fourth nodes in response to first to fourth pulse signals, a first precharge circuit for precharging the first node when controlled by the fourth booster potential from the fourth node, a second precharge circuit for precharging the third node when controlled by the second booster potential from the second node and a first output circuit for outputting the first booster potential of the first node to an output node, whereby a given booster potential can be output since there is no voltage drop of the boosted potential of the second and fourth nodes, there is obtained high potential between the first and third precharge circuits and the precharging speed of the first and third node is not slowed.
摘要翻译： PCT No.PCT / JP93 / 01683 Sec。 371日期：1994年6月29日 102（e）日期1994年6月29日PCT提交1993年11月17日PCT公布。公开号WO94 / 11943 日本1994年5月26日。根据本发明的增压发电电路包括：第一至第四升压电路，用于响应于第一至第四脉冲信号向第一至第四节点提供第一至第四升压电位;第一预充电电路，第一节点，当从第四节点被第四升压电位控制时，第二预充电电路，用于在由第二节点由第二升压电位控制时对第三节点进行预充电;以及第一输出电路，用于将第一节点的第一升压电位输出到输出节点，由于不存在第二和第四节点的升压电压的电压降，所以能够输出给定的升压电位，所以在第一和第三预充电电路之间获得高电位，并且获得第一和第三节点的预充电速度节点没有减慢。

16. 发明授权

US5422853A Sense amplifier control circuit for semiconductor memory 失效
标题翻译：半导体存储器的感应放大器控制电路
公开(公告)号：US5422853A
公开(公告)日：1995-06-06
申请号：US156360
申请日：1993-11-23
申请人： Sampei Miyamoto
发明人： Sampei Miyamoto
IPC分类号： G11C11/41 , G11C5/06 , G11C7/06 , G11C11/401 , G11C11/409 , H01L27/10 , G11C5/02
CPC分类号： G11C5/063 , G11C7/06
摘要： A sense amplifier control circuit supplies a first potential to the sense amplifiers of a semiconductor memory through a set of first control transistors, each coupled in parallel to at least two and at most four sense-amplifier nodes. The first transistors are switched by a first control signal line. A second potential may be supplied to the sense amplifiers through a similar set of second control transistors, which are switched by a second control signal line. The first and second control signal lines may be driven independently, or one or both control signal lines may be driven by a set of drivers coupled in parallel between the two control signal lines.
摘要翻译：读出放大器控制电路通过一组第一控制晶体管向半导体存储器的读出放大器提供第一电位，第一控制晶体管并联至少两个至多四个感测放大器节点。第一晶体管由第一控制信号线切换。可以通过由第二控制信号线切换的类似的第二控制晶体管提供第二电位给感测放大器。第一和第二控制信号线可以独立地驱动，或者一个或两个控制信号线可以由在两个控制信号线之间并联耦合的一组驱动器来驱动。

17. 发明授权

US5313426A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5313426A
公开(公告)日：1994-05-17
申请号：US986998
申请日：1992-12-07
申请人： Shinzo Sakuma , Sampei Miyamoto
发明人： Shinzo Sakuma , Sampei Miyamoto
IPC分类号： G11C11/409 , G11C5/06 , G11C7/00 , G11C11/401 , G11C11/4091 , G11C11/4097 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C11/40
CPC分类号： G11C11/4097 , G11C11/4091
摘要： A memory device according to the invention has a first pair of bit lines, having first and second bit lines, being coupled to a first memory cell which cause a first potential difference between the first and second bit lines; a second pair of bit lines, having third and fourth bit lines, coupled to a second memory cell which causes a second potential difference between the third and fourth bit lines; a first sense amplifier having first and second transistors each of which is a first conductivity type, the gate electrode of said first transistor being connected to said first bit line, the first electrode of the first transistor being connected to the second bit line, the gate electrode of the second transistor being connected to the second bit line, the first electrode of the second transistor being connected to the first bit line; a second sense amplifier having third and fourth transistors each of which is the first conductivity type, the gate electrode of the third transistor being connected to the third bit line, the first electrode of the third transistor being connected to the fourth bit line, the gate electrode of the fourth transistor being connected to the fourth bit line, the first electrode of the fourth transistor being connected to the third bit line; and the second electrodes of said first, second, third and fourth transistors constituting a first common diffusion region formed in a first area of the major surface.
摘要翻译：根据本发明的存储器件具有第一对位线，具有第一和第二位线，耦合到第一存储器单元，该第一存储单元引起第一和第二位线之间的第一电位差; 具有第三和第四位线的第二对位线，耦合到第二存储器单元，所述第二存储单元引起所述第三和第四位线之间的第二电位差; 具有第一和第二晶体管的第一感测放大器，每个第一和第二晶体管都是第一导电类型，所述第一晶体管的栅电极连接到所述第一位线，第一晶体管的第一电极连接到第二位线，栅极第二晶体管的电极连接到第二位线，第二晶体管的第一电极连接到第一位线; 具有第三和第四晶体管的第二感测放大器，每个第三和第四晶体管是第一导电类型，第三晶体管的栅电极连接到第三位线，第三晶体管的第一电极连接到第四位线，栅极第四晶体管的电极连接到第四位线，第四晶体管的第一电极连接到第三位线; 并且所述第一，第二，第三和第四晶体管的第二电极构成形成在主表面的第一区域中的第一公共扩散区域。

18. 发明授权

US5297105A Semiconductor memory circuit 失效
标题翻译：半导体存储电路
公开(公告)号：US5297105A
公开(公告)日：1994-03-22
申请号：US30708
申请日：1993-03-12
申请人： Katsuaki Matsui , Sampei Miyamoto , Tamihiro Ishimura
发明人： Katsuaki Matsui , Sampei Miyamoto , Tamihiro Ishimura
IPC分类号： G11C11/413 , G11C8/10 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/408 , G11C8/00
CPC分类号： G11C8/12 , G11C8/10
摘要： A semiconductor memory circuit selects one memory cell group in response to an address signal having block selection information, first and second significant bit information. First to third memory cell blocks respectively have memory cell groups each including memory cells. First to third decoder groups respectively have first decoders each coupled to one memory cell group in the first memory cell block, second decoders each coupled to one memory cell group in the second memory cell block, and third decoders each coupled to one memory cell group in the third memory cell block. First and second logic circuits respectively output a first common block selection signal with respect to the first and second memory cell blocks in response to the block selection information of the address signal, and a second common block selection signal with respect to the second and third memory cell blocks in response to the block selection information of the address signal. Third and fourth logic circuits respectively, in response to the second and the first information, apply first common decode signals to the first and second decoder groups upon the first common block selection signal being outputted, and a plurality of second common decode signals to the second and third decoder groups upon the second common block selection signal being outputted. In response to the first and second common decode signals, a second decoder in the second decoder group is activated so as to select one memory cell group in the second memory cell block.
摘要翻译：半导体存储器电路响应具有块选择信息的地址信号，第一和第二有效位信息来选择一个存储单元组。第一至第三存储单元块分别具有各自包括存储单元的存储单元组。第一到第三解码器组分别具有耦合到第一存储器单元块中的一个存储器单元组的第一解码器，每个耦合到第二存储器单元块中的一个存储器单元组的第二解码器和每个耦合到一个存储单元组的第三解码器第三个存储单元块。第一和第二逻辑电路响应于地址信号的块选择信息分别输出关于第一和第二存储单元块的第一公共块选择信号，以及相对于第二和第三存储器的第二公共块选择信号响应于地址信号的块选择信息的单元块。第三和第四逻辑电路分别响应于第二和第一信息，在输出第一公共块选择信号时将第一公共解码信号施加到第一和第二解码器组，并将多个第二公共解码信号施加到第二公共解码信号第三解码器组输出第二公共块选择信号。响应于第一和第二公共解码信号，第二解码器组中的第二解码器被激活，以便选择第二存储器单元块中的一个存储器单元组。

19. 发明授权

US5113088A Substrate bias generating circuitry stable against source voltage changes 失效
标题翻译：衬底偏置产生电路对源电压变化是稳定的
公开(公告)号：US5113088A
公开(公告)日：1992-05-12
申请号：US519572
申请日：1990-05-07
申请人： Takayuki Yamamoto , Sampei Miyamoto
发明人： Takayuki Yamamoto , Sampei Miyamoto
IPC分类号： G05F3/20
CPC分类号： G05F3/205
摘要： Substrate bias generating circuitry for generating a substrate bias to be applied to the substrate of an integrated circuit. The circuitry includes an oscillator circuit for generating oscillator pulses having a predetermined frequency. A charge pump circuit has a capacitor and charges and discharges the capacitor in response to the oscillator pulses for generating the substrate bias. A substrate bias level sensing circuit is responsive to the voltage level of the substrate bias for outputting a control signal associated with the sensed voltage level. The level sensing circuit has a level holding subcircuit for holding the control signal in an enabled state at least for a predetermined duration which is four times as long as a period of time necessary for the charge pump circuit to complete a pumping operation. The pumping operation of the charge pump circuit is controlled by the control signal.
摘要翻译：用于产生要施加到集成电路的衬底的衬底偏压的衬底偏置产生电路。电路包括用于产生具有预定频率的振荡器脉冲的振荡器电路。电荷泵电路具有电容器并且响应于产生衬底偏置的振荡器脉冲对电容器进行充电和放电。衬底偏置电平检测电路响应于衬底偏置的电压电平，用于输出与感测的电压电平相关联的控制信号。电平检测电路具有电平保持分支电路，用于将控制信号保持在使能状态，至少持续预定时间长度，其为电荷泵电路完成抽运操作所需的时间长度的四倍。电荷泵电路的泵浦操作由控制信号控制。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式